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Is Quartus Prime 16.0 available for 32 bit Windows?

September 20, 2016, 2:31 am
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I recently downloaded "QuartusLiteSetup-16.0.0.211-windows.exe" from Altera Download Center for my laptop running Winodws 7 - 32 bit. When I proceeded to install this, Quartus installer gave me a question. It said in a dialog box, "The Altera Software you are installing is 64-bit software and will not work on the 32-bit platform on which it is being installed. Do you want to continue to install the software?". Nevertheless I installed it, and as said by the installer, it did not run.

I am unable to find Quartus Prime 16.0 32-bit for Windows. Where can I get it?
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unused pins configuration in Aria 10

September 20, 2016, 4:45 am
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Hi,

I am a bit confused regarding proper configuration of unused pins in a design. I am using an Aria 10. Could i get some comments on the following questions?

1) what is the definition of the 'unused pins' in general? Pins that i do not use because of my top level hdl design or pins that have been left unused when placing the fpga to pcb?

2) when selecting options for unused pins (i.e. input tri-state weak pull up) does this affect all the pins that are not connected to any of my top level hdl signals?

3) i am using Aria 10 fpga and in the 'pin connection guidelines' document, some pins have a guideline to use the Quartus software but others have guidelines such as 'tie to ground or vcc via a xxx resistor'. I guess this is a guideline when developing the PCB connections. But when using a ready board what should the developer do if those pins are not used in the design?

4) in the same document sometimes it is referred: 'If the pins are not connected, use the Quartus Prime software programmable options to internally bias these pins' but elsewhere it says: 'connect this pin as defined in the Quartus Prime software'. Is there a difference in those two options?

Thanks,
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Not able to choose 2.5V LVCMOS standard

September 20, 2016, 4:47 am
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Hi,

if I am using VCCIO of 2.5V i want to select the 2.5 V LVTTL/LVCMOS standard when setting the pin properties. But in my dropdown there isn't any of these standards listed. So whats the problem here? In the DS this standard i given, but not in the Quartus ii software .

Any suggestions or solutions?

Regards
Jérôme
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Custom CycloneV Board based on DE1-SOC, USB3300 issue.

September 20, 2016, 6:27 am
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Hi all,

I integrate a part of DE1 board into my system. I'm using the same family of Cyclone V Soc (5CSEMA5F31C8N) and some useful peripherals of DE1. But I took the USB-otg part from DE0-nano(without usb hub) as reference.

With the sd card image provided by Terasic, I'm able to boot the linux. However, when I insert usb-gadget driver and connect my board to PC, I can't see anything under PC windows 7.
All peripherals are working well except the usb.

The driver module and kernel should be working well because I tested them on a DE-nano board and I was able to see the board detected as a device by PC.

I tried generating preloader and device-tree binary (.dtb) from GRHD found in DE-1 CD ROM, unfortunately it's wasn't better.
In the boot log, it seems that the usb1 is recognized by the kernel and the dwc driver is loaded correctly. (see attached bootlog.txt)

To understand why the usb is not working, we compared all pin signals connecting to USB3300 chip. We’ve found that all input/output signals are the same except the pin “ID” of USB3300.
Without sd card inserted, pin “ID” is in floating state(around 2V) when DE0 board and our board power supplied.
With sd card, pin “ID” turns to high (3.3V) on DE0 board, while it stays at 2V on our board.
When I remove Uboot(uboot.img), device tree file (*.dtb ) and kernel file(zImage), only Preloader remains in the sd card => there’s still a difference of “ID” pin level on two boards.
So the problem may come from preloader, but I’m sure that we are using the same hps_isw_handoff from DE0_NANO_SOC_GHRD to generate the preloader.

We are also sure that we use exactly the same schematic and components for USB (chips, resistances, capacities, etc…).

Please find attached the bootlog of our board. (boot + insmod usb driver + lsusb + dmesg | grep usb).

Do you have any idea on this issue?

Thank you for your help.
Attached Files
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Unable to install Flex license server

September 20, 2016, 7:25 am
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I just created my license for Quartus Std, Floating license edition. I then go to the instructions on how to start a new instance of the License Mgr (lmgrd), pointing at this license file. For some reason, it tells me "Invalid license file syntax" and gives error code: -2,40027.

Can somebody help resolve this?

Dave
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Altera Monitor Program resetting and pausing target processor: FAILED

September 20, 2016, 7:43 am
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I have a design for a simple NIOS II processor on the DE1-SoC board that assigns the value on the switches to the LEDs (standard hello world) but this design integrates the SDRAM on the board into it as per this tutorial Using the SDRAM on Altera’sDE1 Board with Verilog Designs.

I have ensured that the reset and exception vectors and interconnects are as per the tutorial, however when I attempt to load the current configuration and start the debug session i get the following error:

Code:
Using cable "DE-SoC [USB-1]", device 1, instance 0x00
Resetting and pausing target processor: FAILED
Leaving target processor paused
I guess the SDRAM is causing some problem when the processor tries to come out of reset, but I can't work out how...

Does anyone have any suggestions?
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good tool to draw diagrams?

September 20, 2016, 9:44 am
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Hi all, in all Altera documentation (Quartus, Embedded IP, other tools), Altera uses a neat software package that they use to draw everything.

Does anyone know what it might be? Or would anyone be able to suggest a professional software package that can be used to produce similar schematics?

I attached an example, but anything recommendations on something similar that is easy to use and produces good results would be great!

Thanks!
Attached Images
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Error (15684)

September 20, 2016, 12:14 pm
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Hi to all

When compiling a design on EP2C20 I have this error :

Error (15684): M4K memory block WYSIWYG primitive "video:inst9|vdp_vram:U_VRAM|altsyncram:r_rtl_0|al tsyncram_1nm1:auto_generated|ram_block1a4" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version of Quartus II software. Please refer to the Cyclone II FPGA Family Errata Sheet for more information on this feature.

This design compile well on my EP4CE6 but I need more MK4 block.

Files are attached

Someone can help me ?
Thanks
Attached Files
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opening message window causes fatal error in Quartus 16.0

September 20, 2016, 1:23 pm
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Hi,

Whenever I try to open the message window in Quartus 16.0 I get a fatal error and the tool closes.
Has anyone else seen this, and does anyone know a solution?
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DE1-SoC cycling through 7-segment display instead of acting as programmed

September 20, 2016, 1:48 pm
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I have a DE1-SoC board (ref. F) that is not working as I except. Last week, I designed a full adder in Altera Quartus Prime Lite, which I programmed onto the board successfully. I was able to verify that it worked by using the switches and red LEDs. When I tried testing the circuit again today, the board instead cycles through 7-segment LED values. It first displays all 0s, then all 1s, up to all Fs. Toggling the switches and pressing the buttons has no effect.

I tried re-programming it with a full adder again today. The programmer displayed "100% successful", but it did not change the behavior of the board, which is still cycling through 000000-FFFFFF, even after power-cycling. Have I entered some power-on self test mode? How do I get the board to work properly again?

Thank you.
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Barrel shifter coding using mux

September 20, 2016, 7:43 pm
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I need help building a barrel shifter that uses multiplexers and has three columns as stated in the attachment. Please help!
Attached Images
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Change between boards.

September 20, 2016, 11:57 pm
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Hello everyone,
I am out of ideas for fixing my issue so i hope some of you will can help me to.
I am using the hmc-dvi from terasic board with two development kits.
I made a design that just shorts the reciever and transmitted data, hs,vs,de and clk, and configures the transmitter.
When using a Cyclone IV development kit (veek) everything works perfectly.
When changing to a Cyclone V SoC development kit with same design (just reconfiguring pins) i see the image in my monitor like its less bits per color.
My guess is that the board makes some skew in clock or in data, but cant seem to find if thats the problem and if is, how to fix it.

It doesnt seems to be the transmitter as sending a pattern using test pattern generator works good

Hope someone will be able to help and thanks in advance
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Does Quartus's integrated synthesisor actually support modport in interface of SV?

September 20, 2016, 11:58 pm
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I have read Quartus Help, and it says the Modports in interface is not supported. but when synthesizing designs that contains modport, the Quartus does not report any error or warning for it.
In my design I used modport in some interface, when synthesizing it the quartus_map.exe crashes at elaborating step, without any error or warning message about modport. But while synthesizing a submodule in it which used modport, it just complete synthesizing successfully. So I can't determine if modport make quartus_map.exe crash. Could anyone tell me?

BTW: I'm using Quartus Prime v16.0.2.222, in windows 7 64bit
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Constrainst for data launched by negative edge

September 21, 2016, 1:29 am
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Hi,

What is the correct way to constrains source synchronous inputs in this case:
External device provides clock with data.
External device launches data on falling edge.
FPGA latches data on rising edge.

I asume that in this case data comes to FPGA center aligned so I created constraints:

Code:
#Base clock
create_clock -period "100MHz" -name CLK_IN [get_ports CLK_IN] -waveform {5 10}
#Virtual clock
create_clock -name CLK_IN_VIRT -period "100MHz"

set_input_delay -clock [get_clocks CLK_IN_VIRT ] -max $in_max_value [get_ports {DATA*}]
set_input_delay -clock [get_clocks CLK_IN_VIRT ] -min $in_min_value [get_ports {DATA*}]
I have atached TimeQuest waveform.



Do I have to add some exceptions to represent correct clock relationship, because with my constraints TimeQuest does not show that data is launched by falling clock edge?

Thanks
Attached Images
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aocl diagnose: No board diagnose routine supplied

September 21, 2016, 2:04 am
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I am configuring Xeon+FPGA development environment. I have installed an FPGA board using 'aocl install'. However, when I use 'aocl diagnose', the result is
--------------------------------------------------------------------
No board diagnose routine supplied.
Please consult your board manufacturer's documentation or support
team for information on how to debug board installation problems.
--------------------------------------------------------------------
I don't know how to deal with it.
Any suggestion is appreciated. Thanks
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vhdl for loop and synthesis

September 21, 2016, 3:01 am
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Hi,
I'm using
Code:
for i in 0 to idx-1 generate
idx could be 0. Is this a problem for Quartus?
Thanks.
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Quartus development kit bundled license?

September 21, 2016, 3:01 am
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Most development kits include a one year license. The kit I have in mind is the Arria 10 development kit if it matters.


1) Does this mean that Quartus stops working after one year, or will it continue to run after one year, but you're not entitled to upgrades or support?


2) Is the bundled license a node locked license only, or is it a floating license?

3) Will the bundled license work on Linux?

Thanks!
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1-Port ROM only outputting one byte

September 21, 2016, 5:14 am
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Hello all,

I used the Mega-Wizard in Quartus to instantiate a single clocked 1-Port ROM block, 64-bit wide, 256 words deep.
It's for a Cyclone II FPGA.
I created a Memory Initialization File to give it starting values.
Here's the beginning of it below:


DEPTH = 256; -- The size of memory in words
WIDTH = 64; -- The size of data in bits
ADDRESS_RADIX = HEX; -- The radix for address values
DATA_RADIX = HEX; -- The radix for data values
CONTENT -- start of (address : data pairs)
BEGIN
0 : 14 21 A1 4B 68 00 CA 9F;
1 : 19 D8 83 23 2B 90 28 4E;


I place the 64-bit output into a register, and send it out serially to another device, MSB first.
But when I check the serial stream, I see 00s except for the least significant byte.
So for Address 0 I see 0000000000000014 stream out, and for Address 1 I see 0000000000000019.

I don't see any warnings or errors associated with the memory after compilation.


Has anyone seen something like this before?
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How to move the Qsys folder

September 21, 2016, 6:32 am
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Hi,

I want to move the Qsys folder to a new position. What else do I need to change after moving/renaming the folder?

I tried this before, but got an error in Quartus.

Thanks for your support!
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Arria 10 Dev Kit -- USB-Blaster flash programming instructions

September 21, 2016, 7:14 am
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Re: The Arria 10 GX Dev Kit

Do instructions exist for programming the hardware1 area in flash with the USB-Blaster?

I need a faster way than:
1.) Remove dev kit from PC
2.) Set SW6.4 to ON (Factory BTS load)
3.) Load the new .flash file via the on-board web server.
4.) Push two buttons on the dev kit (PGM_SEL and PGM_CONFIG)
5.) Set SW6.4 to OFF (User)
6.) Re-install dev kit in PC
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