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CLKIN_SMA on Arria10 FPGA Development Kit

October 14, 2016, 2:35 pm
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I would like to have a common clock between two Arria10 FPGA boards. I would like to use the SMA_CLK_OUT to drive the CLKIN_SMA on the other board, and set the CLK_SEL to use this clock. However, the SMA_CLK_OUT is 1.8V and the CLKIN_SMA currently is 2.5V. Do I have to move L9 to L8 to modify U42 from a 2.5V to a 1.8V part? Why is this not configurable on the board?

Thanks,

Matt
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Connecting OV9655 Camera to Cyclone II Board (Qsys/Nios)

October 15, 2016, 12:48 pm
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Hi,
I'm a beginner at the FPGA domain, and would be grateful for any help.


I have a Cyclone II EP2C35 board with SDRAM and DM9000A Ethernet controller. I want to connect a small OV9655 camera module, and to transmit a single frame over Ethernet - just as a self learning project. (I'm using Quartus 11)

The camera has the same interface as other omnivision modules, which means 8-bit data (can use 10-bit mode but not in my setup), HSync, VSync and Pclk (pixel clock).
It also has Xclk pin which is the input clock - I'm using 25[MHz] clock from a PLL. An I2C interface is used for configuring the camera, I've connected a different microcontroller to the I2C interface in order to conveniently configure it to QQVGA mode as defined here:
https://github.com/mfauzi/STM32F4/bl.../dcmi_ov9655.c


As for the FPGA/Nios system so far I have done this:
- Built a qsys system which includes SDRAM controller, SGDMA (Stream-to-Memory), DC FIFO, and added interfaces for DM9000A and OV9655. The main clock input is 50[MHz].





- With the Nios II EDS IDE I've tested the DM9000A driver which is working fine - I'm succecfuly sending UDP packets over the net. Also writing and reading from the SDRAM works fine.
- I'm Using the code for SGDMA from http://www.alterawiki.com/wiki/SGDMA

Now I'm trying to run the DMA transfer of 160x120 QQVGA frame (which at RGB565 mode is 120x160x2 bytes long, and over the 32-bit wide SDRAM memory is actually 160x120x2/4 = 9600 words )
The problem is that the data I'm getting inside the SDRAM after running the DMA descriptor seems malformed..
For example, I've attached the Signaltap output of the first bytes of a frame:




As can be seen, it is supposed to be an alternating sequence of 0x80, 0xC3, 0x80, 0xC3 etc. (The camera is configured to Colorbar test mode)
But when I'm checking the SDRAM memory at the debugger, I can see it read a sequence like: 0x80, 0xC3, 0x80, 0x80, 0x80, 0xC3 etc.

The problem is probably somewhere along the OV9655->DCFIFO->SGDMA->SDRAM chain.
I've put the DCFIFO because I thought that the use of 25[MHz] pixel clock along with the 50[MHz] SGDMA driven clock may cause problem to the stream, but not sure if this is correct.

Attached the code for running for the SGDMA transfer:
Code:
    /* Open a SG-DMA for ST-->MM */    alt_sgdma_dev * transmit_DMA = alt_avalon_sgdma_open(SGDMA_ST_TO_MM_NAME);


    alt_sgdma_descriptor *transmit_descriptors, *transmit_descriptors_copy;


    alt_u32 return_code;


    /**************************************************************
    * Making sure the SG-DMAs were opened correctly            *
    ************************************************************/
    if(transmit_DMA == NULL)
    {
        printf("Could not open the transmit SG-DMA\n");
        return 1;
    }


    /**************************************************************
    * Allocating descriptor table space from main memory.      *
    * Pointers are passed by reference since they will be      *
    * modified by this function.                              *
    ************************************************************/
    return_code = descriptor_allocation(&transmit_descriptors,
            &transmit_descriptors_copy,
            NUMBER_OF_BUFFERS);
    if(return_code == 1)
    {
        printf("Allocating the descriptor memory failed... exiting\n");
        return 1;
    }


    for (n=0; n< NUMBER_OF_BUFFERS; n++)
    {
    alt_avalon_sgdma_construct_stream_to_mem_desc(&transmit_descriptors[n],  // descriptor
                                                      &transmit_descriptors[n+1], // next descriptor
                                                      (alt_u32 *)SDRAM_BASE + BUFFER_LENGTH*n,  // write buffer location
                                                      (alt_u16)BUFFER_LENGTH,  // length of the buffer
                                                      0); // writes are not to a fixed location
    }


    alt_dcache_flush_all();




    /**************************************************************
    * Register the ISRs that will get called when each (full)  *
    * transfer completes                                      *
    ************************************************************/
    alt_avalon_sgdma_register_callback(transmit_DMA,
            &transmit_callback_function,
            (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK),
            NULL);


    /**************************************************************
    * Starting both the transmit and receive transfers        *
    ************************************************************/
    printf("Starting up the SGDMA engines\n");


    /* Prime the SGDMA engines with the descriptor lists (first one, it's a linked list) */




    if(alt_avalon_sgdma_do_async_transfer(transmit_DMA, &transmit_descriptors[0]) != 0)
    //if(alt_avalon_sgdma_do_sync_transfer(transmit_DMA, &transmit_descriptors[0]) != 0)
    {
        printf("Writing the head of the transmit descriptor list to the DMA failed\n");
        return 1;
    }


    while(rx_done == 0) {}
        printf("The transmit SGDMA has completed\n");
Any help will be much appreciated.

Thanks,
Ofir
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cycloney gt dev board

October 15, 2016, 12:57 pm
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Hi to all!
Do the cyclonevGT fpga series has a internal tempereture sensor?
And the cyclonevGT dev board has a external sensor for temp mesurament of fpga?

Regards
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maximum memory allocation on openCL

October 15, 2016, 7:07 pm
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Hello,

I need to allocate more than available from openCL today (1/4 of global memory).

 Device max memory allocation: 128 mega-bytes
Device global mem: 512 mega-bytes


How can I increase the max memory allocation limit?

tks!

--
Ciro Ceissler
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JTAG Secure mode

October 15, 2016, 11:47 pm
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Hello guys,
I'm looking for more information regarding the JTAG Secure mode.
It's mentioned a little in the MAX10 Configuration Guide: https://www.altera.com/en_US/pdfs/li...m10_config.pdf
But I still don't get a full picture.
I wonder if the JTAG is "LOCKED" by user logic or is there some kind of permanent switch that forces the device to go into that mode right after power on.
If it's done by user logic, does it mean that, if I hold nCONFIG low, I will be able to erase the internal flash and get out of that "JTAG secure" mode?

I appreciate your sharing of knowledge.

Jeff
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Qsys 15.1 IP porting Problem

October 16, 2016, 6:25 am
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Hi y'all,

MAX 10M08SAE144 device...

I have a Qsys component that was written for ver 11 and it seems to be giving me some severe grief. It is, supposed to be an I2C master. The first issue I had was that I could not use multiple export signal types. I got around this by adding a new conduit interface and giving them unique signal types, It then all compiles correctly and all is good until I try to run my NIOS firmware. Nothing appears on the I2C bus, The I2C signals are connected to bidir pins on the device and external pull ups are in place.

I have had a search on here for a solution the nearest being http://www.alteraforum.com/forum/sho...e+signal+types

The file uploader appears not to be working so: I shall have to paste my tcl and vhd files here:

# TCL File Generated by Component Editor 15.1
# Sun Oct 16 12:48:51 BST 2016
# DO NOT MODIFY


#
# I2CMaster "I2CMaster" v1.0
# 2016.10.16.12:48:51
# I2CMaster
#
#
# request TCL package from ACDS 15.1
#
package require -exact qsys 15.1

#
# module I2CMaster
#
set_module_property DESCRIPTION I2CMaster
set_module_property NAME I2CMaster
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME I2CMaster
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false

#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL I2CMaster
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file I2CMaster.vhdl VHDL PATH IP/I2CMaster/I2CMaster.vhdl TOP_LEVEL_FILE

#
# parameters
#
add_parameter CLOCK_RATE INTEGER 100000000
set_parameter_property CLOCK_RATE DEFAULT_VALUE 100000000
set_parameter_property CLOCK_RATE DISPLAY_NAME CLOCK_RATE
set_parameter_property CLOCK_RATE TYPE INTEGER
set_parameter_property CLOCK_RATE UNITS None
set_parameter_property CLOCK_RATE HDL_PARAMETER true
add_parameter I2C_CLOCK_RATE INTEGER 100000
set_parameter_property I2C_CLOCK_RATE DEFAULT_VALUE 100000
set_parameter_property I2C_CLOCK_RATE DISPLAY_NAME I2C_CLOCK_RATE
set_parameter_property I2C_CLOCK_RATE TYPE INTEGER
set_parameter_property I2C_CLOCK_RATE UNITS None
set_parameter_property I2C_CLOCK_RATE HDL_PARAMETER true

#
# display items
#

#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1

#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1

#
# connection point avalon_slave_0
#
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave_0 address address Input 1
add_interface_port avalon_slave_0 writedata writedata Input 32
add_interface_port avalon_slave_0 readdata readdata Output 32
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 read read Input 1
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0

#
# connection point I2C
#
add_interface I2C conduit end
set_interface_property I2C associatedClock clock
set_interface_property I2C associatedReset ""
set_interface_property I2C ENABLED true
set_interface_property I2C EXPORT_OF ""
set_interface_property I2C PORT_NAME_MAP ""
set_interface_property I2C CMSIS_SVD_VARIABLES ""
set_interface_property I2C SVD_ADDRESS_GROUP ""
add_interface_port I2C SDA sda Bidir 1
add_interface_port I2C SCL scl Bidir 1




Thank you for any advice.

BTW I think there something wrong with this page and possibly IE as it keeps missing typed characters.!!!
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Circuit-level Simulations Verilog Cyclone IV E Project

October 16, 2016, 8:20 am
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Hi!

I have a project that involves me programming a Cyclone IV E in the Terasic DE0-Nano Board to function as a simple processor.

In my design, I am trying to throttle operating frequency based on a given power supply. So, I considered Altera Power Estimations to get the required power of my simple processor and tried to create a system using a variable power supply, a power sensing circuit, The ADC IC included in the DE0-Nano and the Cyclone IV E. The plan is to produce varying power from the supply, sense it, pass it to the ADC feed it to the Cyclone IV E and make it decide on the throttling

The problem is that the available power supply I can get my hands on cannot produce the variable power that my design needs in deciding throttling. For example, the results of the power estimation requires a 0.003A from a 5V supply but the available power supply can only be adjusted up to two decimal places (e.g. 0.00 to 0.01). Is it possible to simulate the system and attach virtual power supply using software?
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Launch Problem

October 16, 2016, 12:12 pm
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I need to run Quartus II v9 for a class I'm taking so I downloaded it, installed csh, ran the install script. But, when I tried to run it, I got this

Code:
[ rodrigo@rodrigo-Latitude-E6400: bin ]$ pwd
/opt/altera9.1sp2/quartus/bin
[ rodrigo@rodrigo-Latitude-E6400: bin ]$ ls
altgx_diffmifgen  jtagd      qcmd        quartus_cmd  quartus_g2b  quartus_pow  quartus_smew  tb2_install
altgx_mifgen      mif2hex    qmegawiz    quartus_cpf  quartus_jbcc  quartus_rpp  quartus_sta  tclsh
clearbox          mwcleanup  quartus      quartus_drc  quartus_jli  quartus_sh  quartus_staw
dmf_ver          mwcontrol  quartus_asm  quartus_eda  quartus_map  quartus_si  quartus_stp
jtagconfig        pll_cmd    quartus_cdb  quartus_fit  quartus_pgm  quartus_sim  quartus_tan
[ rodrigo@rodrigo-Latitude-E6400: bin ]$ ./quartus
quartus: /opt/altera9.1sp2/quartus/linux/libuuid.so.1: no version information available (required by /usr/lib/i386-linux-gnu/libSM.so.6)
quartus: symbol lookup error: /usr/lib/i386-linux-gnu/libXrender.so.1: undefined symbol: _XGetRequest
I am using Xubunutu 16.04 (Ubuntu 16.04 with XFCE desktop)

I don't understand that error nor have any idea how to fix, any help would be great.
Thanks in advance.

Rodrigo Martín del Campo Alcocer
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numbers of lanes QSYS Cyclone V hard IP for PCI Express

October 16, 2016, 3:01 pm
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Hi guys I need your helping please.

I'm using Qsys and I've selected a PCIe interface.
When I customized amount lanes I've selected x1 lanes, but when I watched the interface I've noticed that it has one Rx and Tx.
PCIe use a pair diferential....so my question is:

Why interfaces doesn't has two Rx and Tx???:confused:

lanes.jpg
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Mbox File Conversion

October 17, 2016, 12:20 am
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MBOX mail file which supports by various email client application some time need its conversion on some other email file format when we received it from unsupported email client application. Here I am looking for its conversion solution in an Outlook PST file format.
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Gpio driver example code for cyclone 5 not able to compile ...kernel headers missing

October 17, 2016, 12:50 am
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Hi all,
I am trying to compile the gpio driver which comes with ds-5 examples .when i try to run the make file for it .it doesnt compile and says missing linux/init.h no such file .on googling i redirected make file to downloaded kernel source bt then it finds init.h bt gives errors in init.h itself .i am using linaro tool chain that comes with yocto source package to cross compile for cyclone v on my ubuntu host machine. Is there any source code and compiler version mismatch issue?? Plz help
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cyclone 5 not available in device family options

October 17, 2016, 1:21 am
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While creating a new project cyclone 5 is not available in device family options. i am using quartus prime version 16.0.2
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Programm FPGA from HPS over jtag

October 17, 2016, 2:06 am
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Hi all,
I am using CycloneV platform.
Can I programm FPGA from HPS over JTAG-AP (TAP-controller) independently of the MSEL value? Where can I found some sample code?
I plan to use *.svf file to programm.
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Cyclone VGX Error(175012)

October 17, 2016, 4:42 am
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Hello All,

I have started pin assignment for one of the design , selected Device is cyclone v gx.
when i have assigned clock pin to one pin location using pin_assignment window , the quartus while running fitter come out with an error stating


Error (175012): There are no HSSI reference clock input locations on the device that are compatible with the region constraints on the following logic.
Info (175015): The I/O pad is constrained to the location PIN_L8 due to: User Location Constraints (PIN_L8)
Info (175028): The HSSI reference clock input name: HSSI_REFCLK_CLUSTER0~Clk78~input~FITTER_INSERTED

while the pin has following properties

8A VREFB8AN0 IO CLK8p,FPLL_TL_FBp DIFFIO_RX_T57p DIFFOUT_T57p L8


even searched google regarding the solution but coulnt find answer.


Does anyone knows how to resolve it???
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pcie for dummies

October 17, 2016, 5:41 am
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Hello to all.
I would need a text on the fundamentals of the PCIe.
I would like to study the concepts of Endpoint, Root, and Protocol.

I'm using the example hip_cvgt_g2_x4_avmm_dma128_1602.qar, downloaded from the altera's site, but I do not understand what should I change in order to read and write on the PCIe my custom data (from other logic FPGA).

Can you help me?

Regards, Luca
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Altera USB-Blaster driver for Window10

October 17, 2016, 6:06 am
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Hi Everybody,

I'm a newbie in Altera tools, and I encountered following problem
when trying to install the Altera USB-Blaster periperal on a computer
running Windows 10.

I use the Quartus II 10.0sp1 Programmer.

"Windows encontered a problem during the driver installation of your peripheral
Windows find a driver for the peripheral, but has encontered an error while trying to install it.
The hashing of this file is absent in the file catalog specified.
The file is probably damaged or falsified
If you know th chip manufacturer, you can visit its web site and consult the technical support section, or Download section to find a pilot for this peripheral."


Any help or idea is welcome
Thanks in advance
BR
adie,
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Cyclone V GX PLL not locking

October 17, 2016, 9:32 am
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I have a cyclone V GX on a custom board on which the PLLs do not consistently lock on to the reference clock. The board is based on the terasic Cyclone V GX development board and has the same SiLabs 5338 external PLL generating 125Mhz and 50Mhz along with a 50Mhz oscillator fed into the FPGA through a clock buffer. This provides 4 50Mhz reference clocks and 1 125Mhz reference clock. When I try to generate 2 100Mhz clocks from 2 separate PLLs fed by a 50Mhz and the 125Mhz one PLL will lock and the other will not. When I load the same design into 2 different boards I get inconsistent results, on one board the 125Mhz derived PLL will lock and the 50Mhz will not. While on the other board the 50Mhz derived PLL will lock and the 125Mhz will not. If I change which 50Mhz oscillator is fed to the 50Mhz PLL the results also change with a working 125Mhz sometimes failing to lock and the 50Mhz becoming functional. I have examined the clocks with an oscilloscope and the signal is clean and there is little jitter. I have also looked that the FPLL power supply and there is only 10mVpp-20mVpp ripple. The compile to compile variation seems to be due to which physical PLL quartus assigns, but I can't find anything which would cause the board to board variation. Any suggestions for how to debug or what the issue might be would be very appreciated.
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Convert VHDL to schamatic drawing

October 17, 2016, 1:54 pm
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I am new to the software and I have a large VHDL design. Is there a way to convert it to schematics? it will ease my understanding of the design.
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Reserve all unused pins: As input tri-stated with weak pull-up-Leds are glow faintly

October 17, 2016, 3:27 pm
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Hello everyone,
i am new to FPGA programming.
I have set the unused pins to tri-stated with weak pull-up. As a result, all the unused LEDs are dim.
Is there a way to prevent this without having to assign the pins to the LEDs and set them to 0?
Thanks in advance and apologies for my english.
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Using EPCQ to load Nios

October 17, 2016, 5:26 pm
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1) Why can't I get past "No EPCS registers found"?
If I try "nios2-flash-programmer --device=1 --base=0x42000000 --epcs --debug"
I get:
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Processor data bus width is 32 bits
Looking for EPCS registers at address 0x42000000 (with 32bit alignment)
Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x42000100 (with 32bit alignment)
Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x42000200 (with 32bit alignment)
Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x42000300 (with 32bit alignment)
Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388
Not here: reserved fields are non-zero
Looking for EPCS registers at address 0x42000400 (with 32bit alignment)
Initial values: 01000098 0000203A 01883A01 42370100 3A010880 01C8B388
Not here: reserved fields are non-zero
No EPCS registers found: tried looking at addresses
0x42000000, 0x42000100, 0x42000200, 0x42000300 and 0x42000400
Leaving target processor paused

Now, I've read various other threads and app notes and have done the following:
My EPCS controller has reset connected to system reset and Nios JTAG Debug port reset.
My EPCS controller is clocked with a 25 MHz clock.
My NIOS processor is clocked with a 25 MHz clock.
0x42000000 is the address base for the EPCS CSR bus, but it does the same if I use 0x41000000 which is the memory base.
I can program the EPCS device using a JIC file for the FPGA program, but was hoping to use nios2-flash-programmer to get a software image on there because that doesn't erase the whole device each time. So I know the EPCS device can be programmed via JTAG, and I know the FPGA can boot from it as it recognises my NIOS processor.

2) When I started this post I had assumed I'd got past question 1, but sadly not. Question 2 is - am I really forced to run the NIOS at 25MHz because the EPCS controller is limited to 25MHz? Does QSYS not put in a clock crossing buffer if I have NIOS running at 100MHz and EPCS at 25MHz? It's going to make everything else run very slowly if I'm forced to run NIOS at 25MHz.

Any clues gratefully received.
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