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No more programming files out of QuartusII V15light, V16light, V16 puchased

October 17, 2016, 5:57 pm
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Hey folks,
since around 2 weeks i get no more programming files, but all the other compiler generatet files like *.rpt, *.eqn, *.fit etc. are at the right folder and being updatet at each compile.

Because my V15Light Edition just growes exactly 1 yar old, i thought this could be the reason and installed the V16 30day free trial version.
--> Ok. i found out, that "free trial" doesn't give promming files....(so what can be testet??)
So, after some tests i complely deinstalled everything what has to do anything with Altera or Quartus, even in the registry. Then i installed the V16light version with the same result.
Now i have an licensed V16 installed and it works "fine"² but also dont give any promming file.
What i need is an *.rbf for ps-promming, but all others, if requestet, are also not produced.

The compilation summary gives several warning's, because several in and out pins are still not used, but no error.

Someone an idea?
Thomas

². fine working excludes the very embarrassing representation autogeneratet schematic block's.....
I think this hangs at the twice reserved space for the names.
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!! DONT'T USE FILENAME kernel.cl !!

October 17, 2016, 11:00 pm
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the compiler gets crazy.
The functions inside the file were named completely different from "kernel".
I tried :

  1. aoc --report kernel.cl -o kernel.aocx

I got :
  1. Error: Compiler Error, not able to generate hardware

and in the log :
  1. kernel/quartus_sh_compile.log:Error (16169): Instance "" has an ambiguous entity binding
  2. kernel/quartus_sh_compile.log: Error (16170): Could be "kernel_system.kernel_system"
  3. kernel/quartus_sh_compile.log: Error (16170): Could be "kernel_system_140.kernel_system"
  4. kernel/quartus_sh_compile.log:Error: Quartus Prime Spectra-Q Synthesis was unsuccessful. 3 errors, 1236 warnings
  5. kernel/quartus_sh_compile.log: Error: Peak virtual memory: 3626 megabytes
  6. kernel/quartus_sh_compile.log: Error: Processing ended: Mon Oct 17 16:21:45 2016
  7. kernel/quartus_sh_compile.log: Error: Elapsed time: 00:02:39
  8. kernel/quartus_sh_compile.log: Error: Total CPU time (on all processors): 00:08:02
  9. kernel/quartus_sh_compile.log:Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
  10. kernel/quartus_sh_compile.log:Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings

I renamed the file :
  1. cp kernel.cl tohuwabohu.cl
  2. aoc --report tohuwabohu.cl -o tohuwabohu.aocx

and everything worked
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Problem with while loop in an array

October 17, 2016, 11:29 pm
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I need to check how many cells in an array are "filled" and how many are zeroed.

The array is a one-dimensional array of 64 bits vector.
Declaration in package:
Code:
package my_pack is

    type commands_array is array (natural range <>) of std_logic_vector(63 downto 0);

end package;
Declaration in entity port:
Code:
packets_in        : in commands_array(0 to 17);
This is the while loop:
Code:
    process(packets_in)
    Begin
        while (packets_in(num_packets) /= X"00000000") loop
            num_packets <= num_packets + 1;
        end loop;
    end process;
This is the declaration of the signal num_packets:
Code:
signal num_packets        : integer range 0 to 20:= 0;
So the logic behind this is that I have several functions that fill the array with packets (each of 64 bits, as I've stated before). Initially, each function zeroes all cells of the array.
Theoretically this array can have 18 packets, but in truth each function inserts between 10-12 packets into the array.
The array is an output from one module and an input in the next one (where the while loop is).

I want the while loop to understand on it's own how many cells were filled with packets and insert the number into num_packets.
I'm getting this error:
Error (10536): VHDL Loop Statement error at <vhdl file>: loop must terminate within 10,000 iterations

I'm not sure why the loop doesn't terminate within 10,000 iterations, it should terminate after 18, the way I see it.

I've thought about having the clock in my sensitivity list and doing a simple counter, but I don't want it to be clock dependent, and thought this could be a chance to learn about while loops in VHDL.

Any help would be appreciated, thank you.

Edit: another question, if I had a much larger vector, say 128 bits - is there a way to check if it is completely zeroed by doing something like this?
if (my_vector = (others => '0'))
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Cyclone SoC

October 17, 2016, 11:47 pm
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I am looking for a Cyclone Soc ARM Boards. I found a couple of them from Terasic, but some of these boards are bigger and weigh a lot. However, my application requires using my overall product to be less weight. I am working on payload integration for UAVs. I found some FPGA SoC boards that weigh as low as 100g but they are Zynq SoC, and I prefer Altera over Zynq ones. I definitely don't have time to develop my own integration board and I am just kick starting my project and will be happy to hear any suggestions or reference links.

Thanks
Bala.
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QSYS FFT 16.0 issue

October 18, 2016, 1:58 am
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Hi,

I’m trying to generate FFT 16.0 Core with QSYS. With the setting shown in the attached file the generated code can be synthesized. If I change Data Input Width and Twiddle Width to 32 Bit the .hex files will be generated wrong.

fft_core_fft_ii_0_1n64sin.hex
:03000000000000fd
:030001000c8bd35c36
:0300020018f8b83cf7

As you can see fft_core_fft_ii_0_1n64sin.hex the length of the first doesn't match to the length of other lines.

Output from Quartus: Error (113029): Data size does not match the number of bytes at line 2 in Hexadecimal (Intel-Format) File "fft_core_fft_ii_0_1n64sin.hex"

How to fix this problem?

Best regards
Samuel
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How to write a c application for stratix v altera?? Does nios ii ide support stratix?

October 18, 2016, 2:56 am
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Hi,
I am new to FPGA please help me, I am trying to write a sample application to read and write memory which is connected with nios-ii, I have developed the qsys file connections and I have dumped the .sof file in STRATIX V altera. And I tried to develop a sample program in NIOS II ide with creating a the application with SOPCINFO file. But I can't develop the BSP its failing. Whether stratix v is not supported by Nios-ii ide or is there any other problem??
My idea is to use other working code for Max 10 - DECA board. If I use the Bsp folder of that board and generate the .elf file will it be working for Stratix v board. Please help me with a solution!!

Thanks in advance,

Regards,
prasanth
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What is the best Floating number method?

October 18, 2016, 4:35 am
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Hello friends...

I want to know what is the efficient code to implement this equation :
1/4 ( x+y) + 1/2

However, inputs are integers , and the output will be also rounded to integer. But the intermediate calculations needs to use 1/4 and 1/2.

Kindly inform me about the best way to code this equation.

Thanks...:)
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Qsys16 Custom Peripheral Problem

October 18, 2016, 5:36 am
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Hi there folks,
I recently posted a problem I have been having to integrate a custom peripheral into Qsys. The problem seems to manifest itself in both 15.1 and 16. I am using a MAX10SAE144GES device.

Basically I am trying to create a Qsys peripheral from the vhd file attached, that will acts as a basic I2C master.

1.In order to do this I create a new component within qsys, and then analyze the file. and set up the corresponding signals and interfaces that require my attention (ie those not automatically assigned).

2.I then finish this and Qsys creates the HW tcl file I have attached.

3.I then put my new component into my qsys system, which I have also attached (albeit with the .txt extension which will need renaming to .sopcinfo).

4.FOr sanity I also included a GPIO pin that I can toggle to check everything else is ok.

5.The Qsys sytem then generates without any errors.

6.I then import it into my top level bdf file within quartus connect up the relevant pins and compile. Whcih all works fine!

7.I then generated a BSP and APP in the NIOS EDS tools and all that goes swimmingly.

8.In my software I can drive the GPIO pin perfectly however there is no response from the I2C peripheral even though it is present in the system.h file.

SO I then started delving into things a little,

In my VHDL file you will notice a line that outputs the avalon write signal to an output pin, at present this pin is assigned asynchronously but I have also done it under clkd assignment (registering). at no point EVER does this write signal change state (observed externally with a scope) when I try and talk through software to the peripheral. and more to the point if i try and examnine the signal in siognal tap i get no state change either.

It looks to me as though there is a problem with the connection to the avalon bus, but examining the RTL netlist in quartus seems to suggest everything is connected ok.

I would be grateful if someone could take a look at this please as hindering some critical work.

Many thanks
in advance
deBoogle
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Using Package Constant within another Package

October 18, 2016, 11:21 am
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I have a Package file (System_Config) that defines a set of system Constants used drive generics and signal widths in various VHDL files in a project. A second Package file (Channel_Config) defines a set of channel Constants derived from System_Config. Note that the ultimate goal is to generate the System_Config Package via script and automate builds targeting multiple systems.

Using the Package Constants from any project VHDL file via "use work.Channel_Config.all" and "use work.System_Config.all" works fine. Rolling the two separate packages into and single Config Package works fine. However, having Channel_Config read a constant (say NUM_CHANNELS) from System_Config throws an error that NUM_CHANNELS is undefined. Is there a know issue with a Package using a Constant from a another Package?

For Example:

System_Config_Package.vhd:
Code:
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

------------------------------------------------------------------------------
-- Package Declaration -------------------------------------------------------
------------------------------------------------------------------------------
package System_Config_Package is

  ------------------------------------------------------------------------------
  -- System Constants -----------------------------------------------------
  ------------------------------------------------------------------------------
  constant SYSTEM_TYPE  : integer := 200;
  constant NUM_CHANNELS  : integer := 32;

end package System_Config_Package;
Channel_Config_Package.vhd:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.System_Config_Package.all;

------------------------------------------------------------------------------
-- Package Declaration -------------------------------------------------------
------------------------------------------------------------------------------
package Channel_Config_Package is

  ------------------------------------------------------------------------------
  -- Constants -----------------------------------------------------------------
  ------------------------------------------------------------------------------
  -- Data Arrays
  type SomeDataArray  is array(0 to NUM_CHANNELS-1) of unsigned(11 downto 0);

  ------------------------------------------------------------------------------
  -- Functions -----------------------------------------------------------------
  ------------------------------------------------------------------------------
  function ADC_CHANNEL_MAP(AdcNumber:integer; AdcChannel:integer) return integer;

end package Channel_Config_Package;

------------------------------------------------------------------------------
-- Package Body --------------------------------------------------------------
------------------------------------------------------------------------------
package body Channel_Config_Package is

  ------------------------------------------------------------------------------
  -- System Channel Mapping ----------------------------------------------------
  ------------------------------------------------------------------------------
  -- Map ADC input channels to real channels
  function ADC_CHANNEL_MAP(AdcNumber:integer; AdcChannel:integer) return integer is
      variable DChannel : integer range 0 to NUM_CHANNELS-1;
  begin

....<SOME CALCS HERE BASED ON SYSTEM_TYPE>....

      -- Return Channel Number based on System Type
      return(DChannel);

  end function ADC_CHANNEL_MAP;

end package body Channel_Config_Package ;
This results in the following error:

Error (10482): VHDL error at Channel_Config_Package.vhd(17): object "NUM_CHANNELS" is used but not declared

I would rather not roll everything into Channel_Config_Package, as it is rather large. I would like the build script to generate the only Constants that would change between builds.

Thanks,
Aaron
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Door Security lock with hex keypad and lcd display

October 18, 2016, 11:45 am
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I want vhdl code for door lock where the pin is entered from 4*4 hex keypad and password is shown on lcd
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need fpga with a small footprint that can handle 1080p @ 30 fps video

October 18, 2016, 12:07 pm
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Which of your parts can handle at least 1080p @ 30fps video? I also need the solution to be low power and to be as small as possible (i.e. fit the stem of an eyeglass)
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Design to use with Transceiver Toolkit

October 18, 2016, 2:16 pm
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Hi,

I am trying to create a verilog design so that I can connect two SFP+ ports with an external cable and do BER tests on the loop using the transceiver toolkit. Can anyone help me get started with setting up a design to do this?

Also, I am having trouble with the pin assignments for the SFP+ ports. I am trying to assign one port as a transmitter by assigning the pin associated with SFPA_TX_n and assigning the other port as a receiver by assigning the pin associated with SFPB_RX_n. However, this leads to errors (ex. Error: The output pin SFP_TX assigned to HSSI Pin_XYZ has no fanin.). For each SFP port, there are multiple different pins, one of them being SFPA_MOD2_SDA for serial wire data. I am wondering if I should be using these pins instead, regardless of if I want to assign a port as input or output.
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Can we pass inputs to design/core through signaltapII?

October 18, 2016, 3:07 pm
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Hi,

Is it possible to drive nets in the core via SignaltapII tool? I do not find much information regarding this online.

Thanks
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ALTLVDS_RX Old & New

October 18, 2016, 5:43 pm
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Can anyone tell my why ALTLVDS_RX with an external PLL requires;

1 clock at data_rate/2 when using Quartus 13.1

1 clock at data_rate + 1 clock at data_rate/deser-factor when using Quartus 16.1

This is annoying.
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Tool for VHDL/Verilog code documentation

October 19, 2016, 1:49 am
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Hi,

Can someone share experience on writing documentation for FPGA design? How do you write it?


I want to write documentation for FPGA project, describe which top modules are responsible for what, and main source files should also be documented.
The main purpose of this documentation should be that other designer can easily take and modify my project or quickly understand structure of my project.


I have found some tools for creating documentation like Doxygen and Sigasi. But Doxygen has only few features to support VHDL language and Sigasi is not free tool.


Thanks
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Low Latency PHY IP Core Transmitter

October 19, 2016, 1:51 am
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Hello everyone,

For the project I am working with, I need to use my stratix V GT transceiver SI board as a transmitter . I dont need to use the PRBS generator, the data i will send i already created. So basically what i need is by using the low latency PHY IP-Core transmit the data ( defined in an array ) from SMA ports. I wrote a VHDL code for this but I cannot simulate it . it gives an error when the nativelink program is starting. I have added the error log . Can someone please help me with this?

Also, is there an example code for this purpose ( i thought there might be something due to it is really basic).

Thank you in advance.



Info: Start Nativelink Simulation process
executing command line: ip-make-simscript --nativelink-mode --output-directory=Tx1_iputf_input --spd=Z:/Chalmers/1-1/Project/FPGA/Projects/Learning and Trials/Transmitter 1/tx_core.spd
Internal error: Failed to run ip-make-simscript: 2016.10.19.10:35:53 Error: Unrecognized switch <b>1</b>
2016.10.19.10:35:53 Error: Unrecognized switch <b>2</b>
2016.10.19.10:35:53 Error: Unrecognized switch <b>3</b>
Internal error: Failed to run ip-make-simscript: 2016.10.19.10:35:53 Error: Unrecognized switch <b>1</b>
2016.10.19.10:35:53 Error: Unrecognized switch <b>2</b>
2016.10.19.10:35:53 Error: Unrecognized switch <b>3</b>
Error: NativeLink simulation flow was NOT successful






================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode: 1
Nativelink TCL script failed with errorInfo: 1
(procedure "iputf_call_script_gen" line 25)
invoked from within
"iputf_call_script_gen $spd_file_list"
(procedure "iputf_setup_info" line 45)
invoked from within
"iputf_setup_info"
(procedure "run_eda_simulation_tool" line 178)
invoked from within
"run_eda_simulation_tool eda_opts_hash"
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Arrays - detect signal changes and simulate in Modelsim

October 19, 2016, 4:08 am
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I have two problems with a 1-d array I'm using. The array's cells are 64 bit vectors.
Declaration:

Code:
package my_pack is

    type commands_array is array (natural range <>) of std_logic_vector(63 downto 0);

end package;
The same type of array is an output of one module and an input of another. In one of the modules the array port is this:
Code:
packets_in        : in commands_array(0 to 17);
1. I want to detect a change in the array, because the array is different depending on some switches. Whenever there is a change, I want some signal (tx_cmd) to be HIGH.
Also, it's possible that the array will be all zeroes. In that case I want tx_cmd to be LOW.
Here is what I did:

Code:
if (prev_cmd_array /= packets_in) then
prev_cmd_array <= packets_in;
arr_change <= '1';
else
arr_change <= '0';
end if;

               
if ((arr_change = '1') and packets_in(0) /= X"00000000")  then
tx_cmd <= '1';
end if;
(I am checking only the first cell of the array since I don't know how to check if all of the cells are zeroed. I think this is okay for my design but I would love to also know how to check all of the cells).
I am not sure what this doesn't work. I'm checking my design in SignalTap and tx_cmd doesn't seem to go HIGH whenever I raise the respective switch HIGH (switch HIGH = array changes).

2. I'm also trying to simulate this using Modelsim, but am getting the following error:
too many indices (2) for array type work.my_pack.commands_array (dimensionality 1).

This is the code line with trouble:
Code:
packets_in : IN commands_array(0 TO 17 , 63 DOWNTO 0);
3. I'm trying to use SignalTap to view the arrays but they are always 0. Even when my code worked (though not in the way I wanted) I saw that my outputs, the array's cells, are correct, so the problem is not with the arrays. Is there anything I can do about that?

Thank you!
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custom data types

October 19, 2016, 6:15 am
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Hi, is it possible to create data type with a custom width? Like in vhdl I can have std_logic_vector(17 downto 0). I didn't find anything in documentation. I know its not a standard in OpenCL, but it's quite important feature of fpga, maybe there is something specific. If not, are there any plans to do so?
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OpenCL with Python on Altera FPGA

October 19, 2016, 6:37 am
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Hello,

I want to use Python as host code on OpenCL, any one here use it befor on Windows OS?
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Not correctly read silicon ID from the EPCS64.

October 19, 2016, 8:03 am
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Hi.
For access with EPCS64 from Cyclone IV I use IP-core ALTASMI_PARALLEL.
When I read silicon ID from the EPCS64, epcs_id[7..0] = 0x0B (0000.1011), but should be 0x16 (0001.0110).

The clock frequency of ALTASMI_PARALLEL - 20 MHz.

I brought on SignalTap epcs_id[7..0] and read_dout_reg[7..0] (the shift register of the ALTASMI_PARALLEL).
After reading the silicon ID on Signal Tap epcs_id[7..0] = 0x0B, read_dout_reg[7..0] = 0x16.

There is an assumption that the value on the bus epcs_id[7..0] is latched on the 1 cycle before.

Has anyone such a problem?
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