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Cyclone V ALTLVDS_RX output clock at half the expected rate

October 19, 2016, 9:54 am
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I am using Quartus Prime Standard for a Cyclone V design to instantiate an interface to an 8 channel 12-bit ADC in 2-wire mode. I'm using the ALTLVDS_RX megafunction and I have configured it for 16 channels each running at a deserialization factor of 6. I am using the frame clock out of the ADC which is running at 30 MHZ (which is actually half the ADC sample rate of 60MHz because the frame clock is intended to be DDR). So here are my inputs to the ALTLVDS_RX module:
Input clock: 30 MHz
Deserialization factor: 6
Number of channels: 16
Data rate: 360 MHz
The documentation (https://www.altera.com/content/dam/a...ug_altlvds.pdf page 3) claims that the output clock rx_outclock rate will be the Data rate divided by the deserialization factor (360/6 = 60), however, the rx_outclock rate that the FPGA is generating is at half that rate (30 MHz).
Why?
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bug in Qsys(?). Avalon-ST 'valid' signal broken by Qsys adapters

October 19, 2016, 10:12 am
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This works as connected in Qsys (Avalon-ST):
TSE recieve --> error packet discard module --> TSE transmit

This does NOT work and valid signal disconnected at point marked by **:
TSE recieve --> error packet discard module --> additional logic module -->** TSE transmit

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Hi all. I tried connecting a custom Avalon-ST source to the Triple Speed Ethernet (TSE) Megacore sink. Using SignalTap, I discovered the 'valid' signal of my source would not drive the sink of the TSE module transmit. Has anyone else had this issue? Is this a bug?

My guess is it that the Avalon-ST adapter that QSYS automatically generates disconnected it. I was able to solve by exporting both signals and connecting them manually in my top-level instantiation template, but I'd rather have it internally connected. Anyone experience this before?

I tried hard to figure this out for three days straight. I tried the Avalon-ST Error Adapter IP as well as tried writing my own adapter, but I could not drive the valid signal using Qsys. I triple checked my signals to make sure they were associated properly. I tried forcing a constant 'valid' signal. It simply wouldn't drive. I did notice that Qsys made an adapter for me, and it was at that adapter connection point that the signal would not transmit. Definitely was pulling out my hair trying to figure it out. Good thing my hair is short and I couldn't pull too much out. ;-) Any comments would be much appreciated.
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Error: The output interface has no empty signal....

October 19, 2016, 10:37 am
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Error: avalon_st_adapter_001.data_format_adapter_0: The output interface has no empty signal, but this adapter has been configured to adapt a narrow input interface symbols per beat(6) to a wide output interface symbols per beat(12).

There is no mismatch between source and sink interfaces as far as databitspersymbol and symbols per beat. I created a custom adapter that solves uncommon signal issues between interfaces (the empty and ready signals), but I still keep getting this error. Interesting part is that I could generate HDL in QSYS if I remove irrelevant modules. Did anyone experience such issue?
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Power up sequence in Arria10 SoC Development kit

October 19, 2016, 10:47 am
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Hi All ,

We are using the Arria 10 SoC Development Kit.
Could anyone point me in the right direction as to where i can find a good document explaining the arria10 power up sequence?In the schematic , i could find the power up sequencing for Arria10 devices are divided into 3 groups (Group1,Group2,Group3), is there any place where i can find an explanation on what components are impacted on boot up, and whats its sequence , also after boot up , at what point the SD card becomes available ?

Thank you ,
Kruttika.
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Unable to program EPSQ1024 on Altera Arria 10 Soc Dev Kit using Quartus Programmer

October 19, 2016, 11:37 am
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I'm stumped.

I've been tying to program an FPGA configuration into the EPSQ1024 on an Altera Arria 10 Soc Development Kit (10AS066N3F40E2SGE2 silicon). I've tried setting Switch 4 to both 011 (Fast ASx4 configuration) and 010 (Standard ASx4 configuration). The .sof has been successfully used to config the FPGA via JTAG, but the .jic is unsuccessful with the config of the Factory default SFL image always failing at 95%.

I have also tried to simply do a Blank-Check of the EPSQ1024 device without my .jic file in the JTAG chain configuration and they always fail at exactly 95% loading the Factory default SFL image.

I have tried every 10AS066N3... variant as the target FPGA (I believe it should be 10AS066N3E2, but I'm not completed positive) and the Factory default SFL image either fails at 95% or fails to start. (Screenshot of Quartus Programmer window attached).

Has anyone been successful programming an FPGA image into the Arria 10 Soc Dev Kit's EPSQ device?

Thanks,
Klinker
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10G Base-R PHY IP Core

October 19, 2016, 4:14 pm
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Hi,

I am trying to add the 10G Base-R PHY IP Core to my design so that I can use SFP+ Connectors as part of external loopback for BER testing. I successfully created an instance of this core, but since I am new to Quartus II, I do not know how to implement it into my design. Can anyone help me with this step? Thanks in advance
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Help to make and simulate a PCIe comunication

October 19, 2016, 11:02 pm
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Hi.
I'm trying to simulate a PCIe comunication.
I must send a "data" to my interface PCIe and the FPGA must to take it.
Next I must know what "data" the FPGA has recived and depending of the "data" the FPGA must turn on Leds.
For example:
If I send to my inteface PCIe a word "A", my FPGA must turn on one led.
If I send to my inteface PCIe a word "B", my FPGA must turn on two leds, and so on.


Now I've made a componen in QSYS, it's builds with next devices:
- 1 Avalon-MM Cyclone V Hard IP for PCIe
- 1 Clock
- 1 PIO (Parallel I/O)


Do I need other divices from IP library?? :confused::confused:
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Basic Roofline Model for Arria 10

October 20, 2016, 1:55 am
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In the HPC community a rough model based on 2 ceilings : the peak flops and the bandwidth is used as
a framework to evaluate architectures and algorithms (Sam Williams,D.Patterson The Roofline Model).
This one is for the Arria 10 FPGA, where the measured PCIe gen3 b/w is around 6GB/s and the peak flop/s is around 1.5 Tf/s.
A simple vector addition c[i] = a[i] + b[i] makes 1 flops every 12 bytes transferred therefore the
Arithmetic Intensity is 1/12 and the limit performance is 6*1/12 = 0.5 gflop/s.

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FreeRTOS

October 20, 2016, 4:03 am
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Hi,
i have design for Be Micro MAX10 kit and project with source codes with freeRTOS for NIOS2, which is possible to compile and run, but after first messages
Spoustim RTOS.
1.uloha spustena.
2.uloha spustena.
3.uloha spustena.
Spoustim scheduler.
3.vSign.
3.vSign Back.
1.vMain.
1.Main arg.
1.Look back.
2.vMoin.
2.Moin, Porter (0

it stops, but i dont know why?
In attachment i include the source code, listing of compiler and sopcinfo created by QSYS in Quartus 15.0. I dont know, if the hardware timer is setting ok, if the bsp is setting ok for working with timer functions and/or the scheduler may be bad or stack setting is bad.....

Have you somebody some project and design, which works ok ?

Thank you for your answer.

Jan Naceradsky
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Quartus II Freezing Issue

October 20, 2016, 7:16 am
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Hello I am a college student in which we use Quartus II version 9.1 sp 2 for our labs. During my lab I am able to successfully get to the point of creating a waveform with my inputs and outputs. However, when I need to simulate my waveform to acquire my output waveform my program freezes. It will say that the simulation was successful with no errors when it does this. After a few minutes it will ask me to either close the program or wait for a response. I have tried waiting for it to respond (for a few hours) with no success. Before hand I do have successful compilation and I follow my textbook religiously. The family I'm using is Cyclone II (I've also tried it with Cyclone IV) with the device EP2C35F672C6 which is what is listed in my textbook. Please any help would be appreciated!
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Chain description file (CDF) working in Quartus Programmer GUI but not in CMD tools

October 20, 2016, 8:46 am
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Hello all!

I am currently using the following method to program and verify a CFI Flash device that's not serially on the JTAG chain:

https://www.altera.com/support/suppo...22014_736.html

This method calls for the use a .cdf file, which I made using the Quartus programmer. This method has worked before, but recently, I'm experiencing new trouble where the Flash device would fail to verify whenever I call up the CDF through the CMD line tool (quartus_pgm) but would pass when I open up the same CDF through the quartus programmer. Here's exactly what I got:

When running through CMD, I failed with the following response:

C:\altera\15.0\quartus\bin64>quartus_pgm -c USB-Blaster[USB-0] C:\Firmware\FPGA_VERIFY.cdf
Info: ************************************************** *****************
Info: Running Quartus II 64-Bit Programmer
Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
Info: Your use of Altera Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Altera Program License
Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details.
Info: Processing started: Wed Oct 19 16:27:31 2016
Info: Command: quartus_pgm -c USB-Blaster[USB-0] C:\Firmware\FPGA_VERIFY.cdf
Info (213045): Using programming cable "USB-Blaster [USB-0]"
Info (209060): Started Programmer operation at Wed Oct 19 16:27:39 2016
Info (209006): Device 1 CFI Flash 1 is Spansion S29GL01GS (16 bits data bus)
Info (209005): Programming status: verify on flash device 1 (Spansion S29GL01GS)
at device chain position 1
Info (209021): Performing CRC verification on device(s)
Error (209048): Verify (Block 0x03086000-0x03086800) failure on device number 1
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Wed Oct 19 16:29:26 2016
Error: Quartus II 64-Bit Programmer was unsuccessful. 2 errors, 0 warnings
Error: Peak virtual memory: 1033 megabytes
Error: Processing ended: Wed Oct 19 16:29:26 2016
Error: Elapsed time: 00:01:55
Error: Total CPU time (on all processors): 00:00:22

C:\altera\15.0\quartus\bin64>


When running through the Quartus programmer GUI, however, I would always pass with the following response:

Info (209060): Started Programmer operation at Wed Oct 19 16:32:32 2016
Info (209006): Device 1 CFI Flash 1 is Spansion S29GL01GS (16 bits data bus)
Info (209005): Programming status: verify on flash device 1 (Spansion S29GL01GS) at device chain position 1
Info (209021): Performing CRC verification on device(s)
Info (209005): Programming status: verify on flash device 1 (Spansion S29GL01GS) at device chain position 1 is successful
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Wed Oct 19 16:37:28 2016


Trying multiple times, I found that this behavior was repeatable. Does anybody have any idea why this would happen? The CDF file should be good as it works in the Quartus Programmer GUI and it works in the CMD line for other cards in the past. At first, I wanted to think that it was my card that was defective, but it passes via the Quartus Programmer GUI! What an odd contradiction! Any help with this would be greatly appreciated!
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wait for [variable] ns - Wait statement for a variable time possible?

October 20, 2016, 8:56 am
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Hello Community,

I got a problem with my current coding task: I want to create a small microprocessor in VHDL to work with assembly language via my mif-file. One of my tasks should be a wait statement.

The problem: it should be variable in time. I want to be able to wait as long as the number in my loaded memory is.

This code I tried to implement but it didn't compile:

Code:
when execute_wait =>               
                wait for memory_data_register ns;
                state <= fetch;
In this example my memory_data_register is the content which is read from my memory. It's type is unsigned.

I'd be perfect, if somebody can help me ;)

Best,
orPoG
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ModelSim doesn't launch in VM

October 20, 2016, 9:35 am
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Hello! I've installed Quartus II v 13.1 along with ModelSim in a virtual machine with Windows XP SP3 (I'm using VirtualBox) and I can't launch ModelSim. I see the opening blue image with the version as if the program was starting but it never does. Even if I try to open ModelSim directly it doesn't ork. Did anyone have face this problem before? I have the following configuration on Tools > Options > EDA Tools Options:

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Quartus-II Simulation WVF

October 20, 2016, 10:23 am
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Hello,
I have done the simulation on other computer before, I installed Quartus on mine too. When I try to start simulation this little box supposed to appear and write what's the progress on starting the progress, opens and disappears in less than a second. Is there any log file for this I can check? I use Win10 and I use 64 bit version, Cyclone-III.

Thanks.
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Use locked signal from PLL as reset

October 20, 2016, 10:43 am
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Hi guys,
I have some troubles by using a PLL in combination with a Qsys (HPS) system.
On the arria10 development board, I try to increase the fpga clock (100MHz) with a PLL to 200MHz.
For this, I instance a PLL from the IP Catalog. The 'refclk' is the 100MHz clock and the 'rst' signal is the fpga reset signal (from a button).
I connect the outclk_0 (200MHz) to the Qsys component which includes a HPS and some other peripheral. I like to use the Avalon Bus in the 200MHz clock domain.
After the synchronisation from the PLL 'locked' signal, I added the signal as reset to the Qsys component.

Now, in the TimeQuest Analysis, I become a Recovery error on the reset signal. I saw, that Qsys added a "altera_reset_controller" block which include also a "altera_reset_synchronizer" block.
In my designe, the timing violation is between this sync block ('altera_reset_synchronizer_int_chain_out' signal) and some Qsys component.

Do somebody know why I receive this timing issue? By the way, when I use directly the external reset (from the button) the timing closure.. But in this case, I didn't checked the start up from the PLL...

Thanks for your help and best regards,
Moudi
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LPM Divider execution time

October 20, 2016, 11:49 am
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What is the maximum time to perform a division with Altera LPM_DIVIDE without clock (only combination divider). I am using only unsigned integers and I don't care about the remainder. The numerator is 13 bits and the denominator 8 bits. I am using an EP4CE22F17C6N.
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PHY IP Base-R Compilation Error Peak Memory

October 20, 2016, 3:11 pm
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Hi,

I am trying to use the SFP+ connectors from the 10G BASE-R megafunction on a Stratix V FPGA. I just want to connect the two SFP+ ports with a external cable and do BER testing on the system. However, when I try to compile the design with the PHY IP core, I get the error:

Error: Peak virtual memory: 844 megabytes
Can anyone help me with debugging this?
Thanks
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PCIe card not detected after host computer warm reset (FPGA still powered)

October 20, 2016, 11:30 pm
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Good morning,

I have a misfunction concerning (I think) a PCIe module embedded in a Cyclone V FPGA.

Please, find below my setting as well as the observations I made.

- My setting :
- A laboratory power supply powers the host computer,
- The host computer running GNU/Linux.
- My mini PCIe card is connected to the mini PCIe connector inside the host computer,
- The Cyclone V FPGA is located on this mini PCIe card.

- What I observed and I consider OK:
- When I first switch-on the laboratory power supply, the mother board is powered and the mini PCIe card also,
- Thus, the FPGA is programmed. For information, the programmation time is less than 100ms (checked with an oscilloscope),
- When I push-down the power button of the host computer, it starts and it detects the Mini PCIe card.

- What I observed and I consider not OK and I have difficulties to find out why:
- When a warm reset is done (push-down on reset button), after a random number of time (around 2 -> 20), the mini PCIe card is not detected anymore.
It will be detected again after a cold reset (cut-off the lab. power supply and re power-up the host, etc...).

For information : after the reset, the FPGA is still configured as the motherboard and thus the mini PCIe card are staying powered.

- When a shutdown is done (systemctl poweroff --force --force), the same behavior is observed.

I checked the PCIe configuration (under QSys) as well as the connection to the npor and perst signals.
I have seen nothing wrong.
I checked the user guide from Altera, as well as its forum but unfortunately I couldn't find relevant informations. Also, I'm new in this PCIe topic, so maybe I missed something obvious.

Also :
- my design uses a PLL (Altera_PLL) to clock my cpu plus some others modules.
- The PCie parts (Avalon-MM Cyclone V Hard IP for PCI Express, Altera PCIe Reconfig Driver, Transceiver Rconfiguration Controller) are depending on their own clock : pin_L4, the dedicated PCIe clock input.

I discovered that if I connect the PERST signal to the reset (rst) input of the PLL (Altera_PLL, used to clock my cpu plus some others modules) then this "PCIe detection card" issue is gone. I consider it gone as I did around 60 times a warm reset and the PCIe was still detected.
Before I did that, the "rst" input was grounded (not sure if it is the right thing to do by the way).
Basically, I wanted to check the effect on the functionality when the host PC assert the PERST signal after a reset. As the reset input of the PLL is active High, I use an inverter. In that way, the PLL is reset when the PERST signal is asserted.

That "work around" seems to solve this issue but I am not sure if it is the right way to do and if it was the origin of this issue.

Do you have an idea or any suggestion where to investigate please?

Thank you for your help.
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High speed signal routing on Arria 10 GX signal integrity dev kit

October 21, 2016, 1:14 am
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Noticed that the GXBL differential pair on Arria 10 GX SI dev kit are routed in a curve way instead of straight line with 45 degree bending.
May I know what is the advantage of routing it such a way in term of signal integrity?
Thanks.
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Beginner lost

October 21, 2016, 2:00 am
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Hi, my name is Onofre Garrido and I'm currently working for a company called MECWINS. We have developed some prototype devices to test biological parameters. So far since we are on prototype stage we have built our devices around daq cards from N.I,, labview software and dedicated PC to manage all the components. Our last device uses a matlab software running on several pc cores in order to process images.

My current work focus is on exploring the possibility for using fpga's instead of dedicated pc's for instance in our last device. My knowledge about fpga’s is quite limited so now I think I need some support in order to go in the proper direction.

I have seen for example that there are several softwares to convert matlab code to vhdl that could be potentially implemented on a fpga, but many doubts come up to my mid. How would be the interface for the fpga to be connected to the external world, for example to open a file in any kind of data format? What kind of fpga do I need for processing images? how to interface with the daq world, for example to receive signals from a PSD ...?

May be we need a development card that surround a fpga with kind of peripheral hardware such memory, A/D converters, etc..

I've got a DEO-nano board that I am currently testing in order to get into the fpga world, but I need some support for sure.



I know that perhaps this mail is a crazy mix of probably not well digested ideas. Sorry for that.

Thank you in advance for your support.i
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