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de0_nano_soc pin assignment problem in quartus

November 12, 2016, 2:39 am
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hi,
i am using quartus to connect a DAC daughter board to de0 nano soc through LTC connector. i am using i2c protocol.but when i do the pin assignments , its saying that ""value entered is not a valid location" .

i am trying to connect i2c_sda to PIN_A21 & i2c_scl to PIN_B21 in pin planner

my module initiation is
Code:
module fpga_i2c(

input clk,input reset,input i2c_select,inout reg i2c_sda,output wire i2c_scl );


pin assignment table manual


ltc connector is describe in de0_nano_soc user manual page 41.

after thiis i tried with assignment editer. then i am able to assign the pins. but when i complied it it generated follwing error

[HTML]
Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Altera Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175020): The Fitter cannot place logic pin in region (60, 61) to (60, 61), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): i2c_scl
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended output pin locations available (1 location affected)
Info (175029): B21
Info (175015): The I/O pad i2c_scl is constrained to the location PIN_B21 due to: User Location Constraints (PIN_B21)
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (60, 61) to (60, 61), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): i2c_sda
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended bidirectional pin locations available (1 location affected)
Info (175029): A21
Info (175015): The I/O pad i2c_sda is constrained to the location PIN_A21 due to: User Location Constraints (PIN_A21)
Info (14709): The constrained I/O pad is contained within this pin
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.


[/HTML]


i wanted to connect a dac daughter board to de0 nano soc through LTC connector using i2c interface. after that need to send a 32 bit data(as specified in 2607 manual) to dac and read the voltage on output.i am using LTC 2607 as daughter board.


can anybody help me on this issue.

thanks and regards
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Aria 10 Nios II: Can not activate Single Socket Server example

November 13, 2016, 2:03 am
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Problem to activate Simple Server Socket example on Altera evaluation board

We have Altera Aria 10 evaluation board DK-DEC-10AX115S-A (the card) .
Our goal is to activate Ethernet on the board. We took as a basis the Triple Speed Internet Project Template on the Eclipse IDE. We did all preparations as in the HW, as well in the SW, but we cannot succeeded to connect to the card through TCP/IP.
Details.

1. HW configuration

We defined Nios II and IP on the Altera. See cut from system.htm file.
jtag_uart_0 0x40102CE8 - 0x40102CEF 8 printable
sysid_qsys_0 0x40102CE0 - 0x40102CE7 8
timer_0 0x40102CC0 - 0x40102CDF 32 timer
pio_0 0x40102CA0 - 0x40102CBF 32
spi_0 0x40102C80 - 0x40102C9F 32
sgdma_tx 0x40102C40 - 0x40102C7F 64
sgdma_rx 0x40102C00 - 0x40102C3F 64
eth_tse_0 0x40102800 - 0x40102BFF 1024
mm_bridge_0 0x40102400 - 0x401027FF 1024
mm_bridge_2 0x40102000 - 0x401023FF 1024
descriptor_memory 0x40100000 - 0x40100FFF 4096 memory
onchip_memory2_0 0x40080000 - 0x400FFFFE 524287 memory
mm_bridge_1 0x00000000 - 0x3FFFFFFF 1073741824


BSP configuration.

We has changed the BSP configuration as the following:
enable_dhcp_client is unchecked. We disabled the DHCP package according with "Using the NicheStack TCP/IP Stack - Nios II Edition" document, page 1-9 (13), see the quote below.
"If a DHCP server is available on your network, turn on enable_dhcp_client. If no
DHCP server is available, turn off enable_dhcp_client and specify your IP
addresses, gateway, and network mask in
<tutorial_files>\nichestack_tutorial\niosII_simple_socket_server.h."

Also the simple_socket_server.h file has changed as the following (static IP address):
#define IPADDR0 10//0
#define IPADDR1 0 //0
#define IPADDR2 0 //0
#define IPADDR3 1 //0

#define GWADDR0 10//0
#define GWADDR1 10//0
#define GWADDR2 1 //0
#define GWADDR3 1 //0

#define MSKADDR0 255
#define MSKADDR1 255
#define MSKADDR2 255
#define MSKADDR3 0

2. Successful download HW and SW to the card

After successful compilation and download HW and SW components the card did restart and printed the following on NiosII console.

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.
prep_tse_mac 0

Can't read the MAC address from your board. We will assign you
a MAC address.

Your Ethernet MAC address is 00:07:ed:ff:ad:4e
Static IP Address is 10.0.0.1
prepped 1 interface, initializing...
[tse_mac_init]
INFO : TSE MAC 0 found at address 0x40102800
INFO : PHY Marvell 88E1111 found at PHY address 0x00 of MAC Group[0]
INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]
INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...
INFO : PHY[0.0] - Auto-Negotiation PASSED
INFO : PCS[0.0] - Configuring PCS operating mode
INFO : PCS[0.0] - PCS SGMII mode enabled
INFO : PHY[0.0] - Checking link...
INFO : PHY[0.0] - Link established
INFO : PHY[0.0] - Speed = 100, Duplex = Full
OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203
[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created
mctest init called
IP address of et1 : 10.0.0.1
Created "Inet main" task (Prio: 2)
Created "clock tick" task (Prio: 3)

Simple Socket Server starting up
[sss_task] Simple Socket Server listening on port 30
Created "simple socket server" task (Prio: 4)

These messages above indicate that components are successfully started.

3. Test of Simple Socket Server failed

As described in the mentioned above "Using the NicheStack TCP/IP Stack - Nios II Edition" document on page 17 (see the quote below), I run the "telnet 10.0.0.1 30" session in my PC's cmd window. But the try failed.

"After the NicheStack TCP/IP Stack is ready, you can start a telnet session to interact
with the stack. To start a telnet session, follow these steps:
1. From your operating system, open a command shell.
On Windows, you can also use Run on the Start menu.
2. Type the following command, specifying either the static IP address or the DHCP
server-provided IP address:
telnet <IP address> 30

If the connection to port 30 on the development board is successful, the menu of
available commands displays in a command window."

See below a copied text from my PC's CMD window:

Microsoft Windows [Version 6.1.7601]
Copyright (c) 2009 Microsoft Corporation. All rights reserved.

C:\Users\yakov.e>telnet 10.0.0.1 30
Connecting To 10.0.0.1...Could not open connection to the host, on port 30: Connect failed

C:\Users\yakov.e>

Please help to find the problem
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Stand current of Max V

November 13, 2016, 5:59 am
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Hi. I use 5m160E64.The handbook says that the standby current ICCSTANDBY is 25uA，but I have measured the current is about 10mA when Vccio is 3.3V. I don't know why there are so different.
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BeMicro Max 10 Board - LED Blink Project Using Quartus Prime 16.0.0 Lite

November 13, 2016, 1:37 pm
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Hello,

I am creating my first LED Blink project using the BeMicro Max 10 FPGA Kit. I am following an example from YouTube that uses a previous version of Quartus 15.0, and the code is written in Verilog. When I compile, I get this error: Error (12007): Top-level design entity "LEDBlink" is undefined. How do I define the top-level?

NOTE: The project file is saved in Desktop\Blink\LEDBlink.qpf, and the verilog file is saved as Desktop\Blink\blink.v.

Here is the verilog code...

module blink(clk, LED);
input clk;
output LED;
reg [31:0]count;
assign LED = count[25];
always@(posedge clk)
begin
count <= count + 1;
end
endmodule

Thanks!
Dan
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preferred way to eliminate sdc time value truncated messages

November 13, 2016, 9:29 pm
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Hi,

In my sdc file I calculate various timing values based on a constant that I set in the file. For example:

Code:
# Clock frequency in MHz
set clk_base_freq 14.0

# Clock period in ns
set clk_base_period [expr 1000.0 / $clk_base_freq]

create_clock -period $clk_base_period [get_ports clk_base]
When I use the above code, I get truncation warnings like this:
Quote:
Time value "71.4285714286 ns" truncated to "71.428 ns"
I could put rounding/truncation code, such as the following, into every expression, but that's a bit painful.
Code:
set clk_base_period [expr double(round(1000*(1000.0 / $clk_base_freq)))/1000]
A better solution would be some sort of function, like this:
Code:
proc rndto {value places} {
    set retval [expr {  double(round(10**$places*$value))/10**$places  }]
    return $retval
}

set clk_base_period [expr rndto(1000.0 / $clk_base_freq, 3)]
Unfortunately, this doesn't seem to work, or I can't find the appropriate syntax.

What's the best solution to allowing calculations such as these, while avoiding the time value truncated messages?

thanks,
galen
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Timequest Timing constrain Problem: Where can I get the PLL clock delay

November 14, 2016, 12:00 am
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Hello,

I'm working on a project that receive HDMI video on one end, re-scale it then output it on the other end.
but I have a problem, I don't know where to get the value of TX_CLK_TO_FPGA_min/max, please refer to the figure below.
------------------------------------------------------------------------------------------------------------------------------------------
HDMI Receiver: ADV7611
HDMI Transmitter: ADV7513
FPGA: CYCLONE V C7D6


Question: Where can I find the delay for clock TX_CLK_TO_FPGA_min/max?
Since it is generated by PLL, but I need a value to complete the formula.
---------------------------------------------------------------------------------------------------------------
Here is the ADV7513 TX Timing:

----------------------------------------------------------------------------------------------------
Here is the ADV7611 RX Timing:

---------------------------------------------------------------------------------
Here is the SDC script:

Code:


#**************************************************************
# Time Parameters
#**************************************************************


#-----------------------------------------
#ADV7611
#specify the maximum clock-to-out of the external device
set tCO_RX_max 0.300
#specify the minimum clock-to-out of the external device
set tCO_RX_min -2.200


#-----------------------------------------
#ADV7513
#specify the maximum setup time of the external device
set tSU_TX 1.0
#specify the hold time of the external device
set tH_TX 0.7


#**************************************************************
# RX Time Information
#**************************************************************


#create the input clock
create_clock -name CLK_RX -period 6.734 [get_ports HDMI_RX_CLK]
#create the associated virtual input clock
create_clock -name CLK_RX_virt -period 6.734


#----------------CLK_RX delay---------------------
#----clock delay is included by tco----
#create the input delay referencing the virtual clock


#NOT EXIST IN ADV7611 DATASHEET
#specify the maximum external clock delay from the external device
set RX_CLK_TO_HDMI_RX_max 0.0
#specify the minimum external clock delay from the external device
set RX_CLK_TO_HDMI_RX_max 0.0


#specify the maximum external clock delay to the FPGA
set RX_CLK_TO_FPGA_max 0.200
#specify the minimum external clock delay to the FPGA
set RX_CLK_TO_FPGA_min 0.100


#----------------board_delay_in---------------------
#specify the maximum board delay
set BD_RX_TO_FPGA_max 0.180
#specify the minimum board delay
set BD_RX_TO_FPGA_min 0.120




#**************************************************************
# TX Time Information
#**************************************************************
#create the output clock
#create_clock -name CLK_HDMI_M_OUT -period 6.734 [get_ports HDMI_TX_CLK]


create_generated_clock -name {CLK_TX} -source [get_pins {u0|pll_vid_m|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] -master_clock {u0|pll_vid_m|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk} [get_ports {HDMI_TX_CLK}]


#----------------CLK_TX delay---------------------
#CAN NOT FIGER IT OUT
#specify the maximum external clock delay to the FPGA
set TX_CLK_TO_FPGA_max unknow
#specify the minimum external clock delay to the FPGA
set TX_CLK_TO_FPGA_min unknow


#specify the maximum external clock delay to the external device
set TX_CLK_TO_TX_max 0.100
#specify the minimum external clock delay to the external device
set TX_CLK_TO_TX_min 0.050


#----------------board_delay_out---------------------
#specify the maximum board delay
set BD_FPGA_TO_TX_max 0.180
#specify the minimum board delay
set BD_FPGA_TO_TX_min 0.120


#**************************************************************
# Set RX Input Delay
#**************************************************************


#create the input maximum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock_fall -clock {CLK_RX_virt} -max [expr $RX_CLK_TO_HDMI_RX_max + $tCO_HDMI_RX_max + $BD_RX_TO_FPGA_max - $RX_CLK_TO_FPGA_min] [get_ports {HDMI_RX_DAT[*] HDMI_RX_HS HDMI_RX_VS HDMI_RX_DE}]


#create the input minimum delay for the data input to the
#FPGA that accounts for all delays specified
set_input_delay -clock_fall -clock {CLK_RX_virt} -min [expr $RX_CLK_TO_HDMI_RX_min + $tCO_HDMI_RX_min + $BD_RX_TO_FPGA_min - $RX_CLK_TO_FPGA_max] [get_ports {HDMI_RX_DAT[*] HDMI_RX_HS HDMI_RX_VS HDMI_RX_DE}]




#**************************************************************
# Set TX Output Delay
#**************************************************************


#create the output maximum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock CLK_HDMI_M_OUT -max [expr $TX_CLK_TO_FPGA_max + $tSU_HDMI_TX + $BD_FPGA_TO_TX_max - $TX_CLK_TO_FPGA_min] [get_ports {HDMI_TX_DAT[*] HDMI_TX_HS HDMI_X_VS HDMI_TX_DE}]


#create the output minimum delay for the data output from the
#FPGA that accounts for all delays specified
set_output_delay -clock CLK_HDMI_M_OUT -min [expr $TX_CLK_TO_FPGA_min - $tH_HDMI_TX + $BD_FPGA_TO_TX_min - $TX_CLK_TO_TX_max] [get_ports {HDMI_TX_DAT[*] HDMI_TX_HS HDMI_M_VS HDMI_TX_DE}]
--------------------------------------------------------------------------------------------------------------------------
I write a sdc script base on "Altera Timequest Cookbook". I also read this wiki but I don't think it's completely correct. http://www.alterawiki.com/wiki/Constrain_SPI_Core

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How to add a buffer chip to JTAG pins

November 14, 2016, 12:45 am
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If there are multiple FPGAs on the JTAG chain, altera recommends using JTAG buffer chip on TMS, TCK and TDI pins. I could not find a proper schematic for this.
Anyone can help?
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Transfering data from FPGA into HPS with one-port-RAM in DE0-nano-soc.

November 14, 2016, 6:51 am
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Hello!


I am a newbie in digital design and just started to study this field. I own an DE0-Nano-SoC board and after some experiments with Verilog and FPGA part I want implement such design which read the values from the ADC and store they into the memory in FPGA part and simultanously read this memory in HPS and process in C-written program. And then probably send via network interface.


I implemented the driver to work with the ADC and some other modules in Verilog and a top level entity in BDF, inserted an IP-core for one-port-ram and inserted the block entity of it into my top-level BDF, connected the memory with my driver and so on.
Then I launched Qsys, inserted the HPS and one-port-RAM from the catalogue, conncted the LW bridges, the clocks and the resets and generat the Verilog files.


Then I was executed the TCL scripts that was generated by Qsys. hps_sdram_p0_parameters.tcl was OK and I performed Analysis and sintesis after it succesfully. But when I launched _pin_assignments.tcl I got an error with the message that sdram is never instantiated.


Could anybody explain how such projects must be organized step by step? The example that Terasic provide with the board is not very clear because a lot of important steps were skiped and also it shows usage not of the memory but of PIO.
After reading many altera's documents I stll can't understand how to use the same memory in FPGA and HPS because of the complexity of the EDA and the device itself. Maybe somebody knows any examples of the projects with interconnection betwin FPGA and HPS that could help me?
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USB Bulk IN slow on Cyclone V

November 14, 2016, 12:21 pm
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In our company we have a custom board using Cyclone V 5CSEBA2U19C8SN and USB 3300. We use Linux 4.1.15, build it with Buildroot 2015.11.1. One of my tasks is to setup USB Gadget subsystem. I use combination of FunctionFS and ConfigFS to create a configuration with two bulk endpoints (in and out). It works, but I noticed that while bulk out (host to device) transfers at 20MB/s, bulk in (device to host) transfers at 10MB/s only. I tried mass storage gadget (g_mass_storage, alone, not in combination with my configuration) and got the same results: host to device at 20MB/s, device to host at 10MB/s. It seems odd to me that reading would be 50% slower than writing, I would expect these two at approximately the same speed. Is this normal? Why? If not, what steps should I take to find the cause?
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SPI port on Arria10 SoC Development Board

November 14, 2016, 2:47 pm
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Hi All,

We are trying to determine where we can monitor the SPI port signals on the board (10AS066 Dev Kit).

Could anyone point me to the right direction ?


Thanks,
Kruttika.
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MicroSD daughter card - Arria 10 dev board

November 14, 2016, 2:56 pm
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Hi all, I have an Arria 10 dev board (10ASXSoC000165) with a bad MicroSd daughter card (E204460). Anybody knows how/where to get a replacement ?
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FPGA Remote Upgrade

November 14, 2016, 7:05 pm
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Hi All,

I am stuck with this FPGA upgrade problem. I started doing the upgrade in which the factory image has the Remote update and ASMI IP blocks and the application image has the Serial Flash loader IP block. I switch from the factory to the application image and programmed the flash externally using a .rbf file and the fpga gets upgraded.


The problem i am facing is that, after doing the upgrade, if I power cycle the fpga it loses the upgraded image and goes back to the factory image. Is this how it will happen ? If this is a problem can you guide me to a solution for this problem.

Thanks,
Sid
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Build Megawizard/QSYS Systems from command-line (for build environment)

November 15, 2016, 12:21 am
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Hi.

I want to build my Quartus projects (huge Arria II GX and Arria V setups) automatically on a remote build server.

But there's one major problem: My project contains multiple Megawizard and QSYS Components.
Currently, I only store .qip and .vhd files in our CVS system. This works great if you open the Quartus GUI, double-click the Component and click generate to create the underlying compents like altgx_reconfig, altgx_pll, etc.

But when using the command-line, the command
quartus_sh --ip_upgrade -variation_files %path_to%\altgx_transceiver.qip %project%
simply does nothing. The command line states a successful execution, but no files are created.

Is it possible to fully create PCIE Compiler IPs, Transceiver Setups, etc. from pure .vhd/.qsys files?
Do I have to somehow parse the qip settings file to create new components? Can anybody sent an example how to do this?

Best regards,
_X_
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Local Reset Conditions - Sync or Async

November 15, 2016, 2:56 am
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Just pondering a question, and wondering what other people would do.
We all know that Altera recommends async asserted, sync de-asserted asynchronous resets, and real sync resets have to be emulated. So would it then follow, that if I have some signal that is reset by some other signal, and the global reset, to OR them together to reset the flop asynchronously:

Code:
process(clk, rst, local_rst)
begin
  if rising_edge(clk) then
    op <= ip;
  end if;

  if rst or local_rst then
    op <= '0';
  end if;
end process;
Traditionally, I would always treat "local_rst" as a synchronous reset and take the setup timing hit, but would the above be worse from a recovery POV compared to the "traditional" code below:

Code:
process(clk, rst)
begin
  if rising_edge(clk) then
    op <= ip;
 
    if local_rst = '1' then
      op <= '0';
    end if;
  end if;

  if rst = '1' then
    op <= '0';
  end if;
end process;
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Startup Delay

November 15, 2016, 3:22 am
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Hi everyone,

I am using Altera MAX 10 CPLD in my design. I would like to know what is the startup delay associated with the device (the time elapsed between power on and the device starts working).

Thanks in advance :)
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still problems with timequest

November 15, 2016, 6:24 am
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Studying the AN 477 to page 15 I read:
At the FPGA (Receive) Side

Example 4.
# Create a 125MHz clock
# virtual_source: an ideal clock in the sourcing device
# RX_CLK: input clock port of the interface; 90 deg phase shifted
create_clock -name virtual_source -period 8
create_clock -name RX_CLK -period 8 -waveform { 2 6 } [get_ports {RX_CLK}]
# Set input delay based on the requirements mentioned previously
# RX_CLK is 90 deg phase shifted
# Input delay is relative to the rising and falling edges of the clock
set_input_delay -max 0.8 -clock [get_clocks virtual_source] -add_delay [get_ports RXD*]
set_input_delay -min -0.8 -clock [get_clocks virtual_source] -add_delay [get_ports RXD*]
set_input_delay -max 0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay \
[get_ports RXD*]
set_input_delay -min -0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay \
[get_ports RXD*]
set_input_delay -max 0.8 -clock [get_clocks virtual_source] -add_delay [get_ports \
{RX_CTL}]
set_input_delay -min -0.8 -clock [get_clocks virtual_source] -add_delay [get_ports \
{RX_CTL}]
set_input_delay -max 0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay \
[get_ports {RX_CTL}]
set_input_delay -min -0.8 -clock_fall -clock [get_clocks virtual_source] -add_delay \
[get_ports {RX_CTL}]
# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks virtual_source] -rise_to [get_clocks {RX_CLK}] \
-setup
set_false_path -rise_from [get_clocks virtual_source] -fall_to [get_clocks {RX_CLK}] \
-setup
set_false_path -fall_from [get_clocks virtual_source] -fall_to [get_clocks {RX_CLK}] \
-hold
set_false_path -rise_from [get_clocks virtual_source] -rise_to [get_clocks {RX_CLK}] \
-hold


I use cyclonev dev board with marvell ethernet PHY.
I use the phy delay option for center align the rx data to rx clock (from phy to fpga).
I replaced the value 0.8 with the value 1.2 (see image).

But timequest analis fails hold slack.
where am I wrong?
Attached Images
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Altera Cyclone V Sockit - Internal Oscillator Clock Source?

November 15, 2016, 7:21 am
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Internal Oscillator for the Initialization Clock

I have a Altera Cyclone V Sockit Development board and are using the Internal Oscillator as the initialization clock source for all my FPGA images.

I was just wondering where this internal oscillator is sourced and what are the requirements of this initialization process?

Is it generated internally?
Is it part of the architecture of EPCQ Flash on the FPGA side?
Do I need any clocks on the FPGA running for this initialization clock to work correctly?

Thanks

Kyle
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Conditional assignment statement vs selected assignment statement

November 15, 2016, 8:21 am
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Hello,

I have some experience with VHDL, but now I am trying to understand the details and not just using the code.

What is the difference between the conditional assignment statement and the selected assignment statement? Additionally why in the example below can't be assign when r(3) = '1', but we have to consider all possibilities?

Considering the following example of a priority encoder where r is a 4 bit input binary sequence to be encoded.

with r select
code <= "11" when "1000"|"1001"|"1010"|"1011"| "1100"|"1101"|"1110"|"1111",
"10" when "0100"|"0101"|"0110"|"0111",
"01" when "0010"|"0011",
"00" when others;

refers to page 22 in the document linked below

code <= "11" when (r(3)=’1’) else
"10" when (r(2)=’1’) else
"01" when (r(1)=’1’) else
"00";

refers to page 10 in the docment linked below

Thanks! :)

http://ece-research.unm.edu/jimp/vhd...rent_stmts.pdf
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Unable to program Arria 10 FPGA from Linux

November 15, 2016, 10:44 am
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I've asked this question on the rocketboards forum, but thought I'd repeat it
here. The rocketboards post is here
https://forum.rocketboards.org/t/una...ps-linux/693/3.


I'm trying to program the FPGA on an Arria 10 SoC Development Kit
(DK-SOC-10AS066S-A). However I'm not able to access the /dev/fpga0 device.


I am able to boot into linux on the board and ssh in as root.


I've flashed the SD card with sdimage.img from
linux-socfpga-gsrd-16.0-a10-bin.tar.gz (revision B as I have the ES2 kit). I've
also tried with linux-socfpga-sgmiird-16.0-a10-bin.tar.gz with identical
results.


I've transferred the hello world program to the board as "hello.rbf".


Code:
dd if=hello.rbf of=/dev/fpga0
fails with
Code:
dd: can't open '/dev/fpga0': Operation not permitted.

Code:
cat /sys/class/fpga/fpga0/status
outputs
Code:
user mode

There are no bridges enabled,
Code:
ls /sys/class/fpga-bridge
shows nothing.


The switch and jumper configuration on the board:


Code:
SW1: OFF OFF ON ON
SW2: All OFF
SW3: OFF OFF ON ON ON OFF OFF OFF
SW4: All OFF

Code:
Jumpers J16 and J17 are shorted.
Jumper J30 is shorted.
Jumper J32 is shorted across 9 and 10.
Jumper J42 is shorted across 9 and 10.

The instructions here
https://rocketboards.org/foswiki/vie...ion_from_Linux
suggest stopping the boot at UBoot to prevent UBoot from flashing the fpga.


I've attempted to stop the boot there, but the "press any key" prompt happens
after it flashes socfpga.rbf to the FPGA. Removing socfpga.rbf from the disk
causes UBoot to loop with this output:


Code:
U-Boot 2014.10 (May 03 2016 - 09:43:56)


CPU  : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
DRAM:  WARNING: Caches not enabled
SOCFPGA DWMMC: 0
Error - socfpga.rbf not found within SDMMC
cff_from_mmc_fat: error reading rbf header
INFO  : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe2db10
data abort
pc : [<ffe00b1a>]          lr : [<ffe01d4d>]
sp : ffe3bf00  ip : 0000001c    fp : 00000001
r10: ffd02078  r9 : ffe3bf60    r8 : ffe00054
r7 : ffe20b60  r6 : ffe3c000    r5 : 00000000  r4 : ffffd000
r3 : ffcfb000  r2 : 00000002    r1 : 00000001  r0 : 00000001
Flags: nzcv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

Replacing socfpga.rbf with my hello world file does what I expect it to
(displays a binary counter on the LEDS), however u-boot does not proceed beyond
flashing the FPGA.


I am able to use the example programs (blink, syschk) in /home/root/altera
without problems.


Please let me know if there is any more useful information I can provide.
↧

CPLD Hard Reset

November 15, 2016, 11:53 am
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0
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Hi all,

I am using a Max 10: 10M02SCM153C8G . I am facing a problem with reprogramming it. After programming the CPLD, now the JTAG is not able to identify the CPLD at all . This is the first time I am encountering such a problem. I want to know if there is a way of doing a hard reset on the CPLD to bring it back to its original state. Kindly let me know the procedure on how to do a Hard Reset on the CPLD.


Thanks,
Sid
↧
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