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newbie to SOCkit

November 15, 2016, 12:43 pm
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Hello
I'm working on system identification and signal processing. I'm gonna work with SOCKit+High Speed AD/DA Card. I've learned pure VHDL.
My time is limited I'm very concerned about the future of my project!
I have three questions:
1-can I write my codes in pure HDL? (only for FPGA not for Cortex-A9) for example consider I can not work with Cortex-A9 so I'll postpone working with Cortex-A9 to next year!
2-is it necessary to learn Verilog? (the timing is so important for me this is why I've chosen VHDL) if so please introduce a good tutorial for Verilog.
3-is it necessary to install Linux on SOCKit to use Cortex-A9 or I can work with Cortex-A9 in IAR? maybe I want to process some data on Cortex-A9. actually my sampled signal size is huge. only for 1 sec the data size is 2x65MHzx16Bit! I'm very concerned about the processing on sampled signals due to limited ram capacity.

Regards
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MegaCore Function Generation Error

November 15, 2016, 1:12 pm
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Hi,
I got an error using the example file "topfft.mdl" in HIL tutorial offered by Altera.

When I open the"fft_stream" FFT control window and click on "Step 2: Generate" to update the FFT megacore function, error prompts out as follows:
"MegaCore FUnction Generation Error"
"IP Functional Simulation Model Creation Failed. Code==3".

My running enviroment is "DSP builder 16.1" and "Matlabe2015b"
How can I solve this problem?

Hou
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Programming the EPM7128AEFC100-10 via JTAG

November 15, 2016, 1:42 pm
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We still produce a boards that contains a EPM7128AEFC10-100. The logic sheet refers to it as an EPLD. Our production line was using an IC tester to program this device, but that tester has died and we need to program this device on several boards. I'm assuming I can use the JATG port and probably an Altera Byte Blaster, but I can't find any information on what I need here.

Advice?

Kelly Small
Pr. Test Engineer
Honeywell
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problems simulating Full adder

November 15, 2016, 3:07 pm
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Module Declaration Question for Transceiver Design

November 15, 2016, 3:50 pm
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Hi, I was hoping someone could answer a fairly simple question. Here is my module declaration code for a transceiver design:

module xcvr_prbs (

//inputs
input wire phy_mgmt_clk,
input wire pll_ref_clk,
input wire reset_reset,
input wire reconfig_reset,
input wire rx_serial_data,
input wire rx_seriallpbken,


input wire xgmii_tx_clk,
input wire rx_serial_data_0,
input wire xgmii_tx_dc_0[71:0],




output wire xgmii_rx_clk,
output wire rx_data_ready,
output wire xgmii_rx_dc_0[71:0],
output wire tx_serial_data_0,


//ouputs
output wire errorFlag,
output wire [100:0] errorCount,
output wire tx_serial_data,
output wire tx_ready,
output wire rx_ready,
output wire [63:0] prbs_data_rx_top
);

My question is, how do I know whether to put input/output wires and registers inside the module parenthesis, or outside the parenthesis? I have been following some example transceiver designs and in those examples, some wires are declared inside and some outside. I am assuming the ones declared inside the module also need pin assignments. Is that correct?

Thanks in advance!
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Nios II UDP Offload Example author

November 15, 2016, 6:33 pm
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Does anyone know who the Nios II UDP Offload Example author is? The link is below:

http://www.alterawiki.com/wiki/Nios_...ffload_Example

I'm working on my master's degree and want to properly give attribution to the great work. It had been really helpful these past few months in understanding channels, packets, streaming concepts, use of data and channel FIFOs, and more. It would be great to be able to put a name to it rather than just "Altera Wiki"
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Using Qsys SRAM and SDRAM controllers without a Nios II

November 16, 2016, 1:07 am
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I need to communicate with the SRAM in the DE2-115 board using purely VHDL code. No Nios II. Later I may have to use the SDRAM instead if bigge memory is required.

I understand that a controller is required. Is it only found inside Qsys? If I decide to use the Qsys controller, how do I make use of it without any Nios II i.e link the Qsys memory controller to a state machine written in VHDL which is not part of the Qsys system. If you have better ideas then please let me know.
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How to use framebuffer when implementing line drawing algorithm in FPGA

November 16, 2016, 1:38 am
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I need to implement the Bresenham's integer line drawing algorithm onto the DE2-115 board. The algorithm is quite simple, we give the xy coordinates from start point to end point, the algorithm then simply calculates for the given curret pixel (x,y) does the next pixel which has x coordinate x+1 have same y coordinate or y+1 or y-1.

As I calculate the results I need to store them into a memory. Provided that I am implementing this as a monochrome system and there are 8 pixels stored per byte in memory, it seems difficult task to write these bits into memory. Provided that SRAM is used as frame buffer. At start of frame, I shall have to clear all bytes in the SRAM. Then, I find which byte a pixel belongs to, I read that byte from memory, AND the bit which represents the line pixel and then write it back.
I shall therefore, need a FIFO with line coordinates, these put into a FIFO, multiple pipelines take data from this FIFO and continuosly output pixel coordinate which must be "colored" since line passes through it and fill these into another FIFO. Then a dispatcher shall read these coordinates, figure out how to write them to memory, wait until memory is free and then read the memory, set the bit and write it back.
Is there a better way to fill in the frame buffer?
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Gen1x1 PIPE error during Place and Route (Fitter) due to tx_pma_div_clkout factor

November 16, 2016, 5:42 am
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Hi,

I have summarized the background about my design and Hardware setup in next two paragraphs and the issue I'm facing is in remaining paragraphs.

I'm trying to implement Gen1 PCIe (3rd Party IP) on Altera Arria 10 (10AX115S2F45I1SG) GX Board. The configuration on my controller interfacing with PIPE side is 1 lane and 32 bit operating at 62.5MHz ( this will be supplied from PHY). But since the Altera PHY PIPE doesn't support 32bit, I'm trying to generate PIPE with 16 bit at 125MHz, so that I can use some logic to convert from 16bit @125MHz to 32bit @ 62.5MHz for the controller.

I am able to generate PIPE Gen1x1 successfully using Quartus 15.1.2 by following the "Native PHY IP Parameter Settings for PIPE" suggested in the Arria 10 Transceiver manual. During configuring the PIPE in Quartus, I have enabled the option to include "tx_pma_div_clkout" port and set "tx_pma_div_clkout division factor as 2" so that I can supply 62.5MHz to my controller.

When I tried to run the Fitter, I get the following error:
Error (15653): The Fitter cannot find a legal configuration for the following atoms. Update any outdated transceiver PHY IP cores, correct any illegal pin assignments, and then recompile your design.
Error (15744): The settings must match one or more of these conditions:
Error (15744): ( ( datarate_bps > 4999999999 ) OR ( rser_clk_divtx_user_sel == DIVTX_USER_OFF ))
Error (15744): But in atom 'pipe_gen1_x1_native_ip<img src="images/smilies/tongue.png" border="0" alt="" title=":P" smilieid="5" class="inlineimg">ipe_gen1_x1|pipe_gen1_x1_native_ ip_altera_xcvr_native_a10_151_o255bgq:xcvr_native_ a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev _20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ buf.inst_twentynm_hssi_pma_tx_buf'
Error (15744): The following assignments violate the above conditions:
Error (15744): xtx_path_datarate = 2500000000
Error (15744): But in atom 'pipe_gen1_x1_native_ip<img src="images/smilies/tongue.png" border="0" alt="" title=":P" smilieid="5" class="inlineimg">ipe_gen1_x1|pipe_gen1_x1_native_ ip_altera_xcvr_native_a10_151_o255bgq:xcvr_native_ a10_0|twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev _20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ ser.inst_twentynm_hssi_pma_tx_ser'
Error (15744): The following assignments violate the above conditions:
Error (15744): ser_clk_divtx_user_sel = DIVTX_USER_2
Error (12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted.


Since my design uses 2.5Gbps rate I ignored "xtx_path_datarate = 2500000000" error. But I observed that the error is due to "ser_clk_divtx_user_sel = DIVTX_USER_2" and this is because I have set "tx_pma_div_clkout division factor" as 2 as this can give me required 62.5MHz clock for my 32bit controller interface and make the PIPE lane width as 16bit @ 125MHz. Though this setting is valid as per Native PHY settings suggested in Transceiver model, I'm unable to do run Fitter. I do not observe this error when I disable division factor.

Any suggestions to fix this issue?
Thanks in advance.

pcs
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Hold violation on source synchronous clocks

November 16, 2016, 7:08 am
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Timing is failing with Hold time negative slack of (-0.098) when going from a 20MHz to a 100MHz clock domain (both clocks are synchronous and generated from the same PLL). This is a cyclone V design which is using upwards of 80% resource usage.

I have not added any multicycle path exceptions here.

timing will occasionally pass or fail at different paths with similar hold violations.

Please see the screenshot and worst case path report attached.

What do you suggest for resolving this?
Attached Images
Attached Files
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How to Convert or Revert Qsys Pro Back to Qsys Standard

November 16, 2016, 6:03 pm
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Hi Forum Fans!

I have an IP block delivered from a customer in Qsys Prime Pro (beta) format. As Murphy's ghost requires, the rest of the design must to be in Qsys Prime Standard form to support other IP blocks from other suppliers.

Qsys Prime Pro automatically converts a standard version Qys file to Pro but it does not appear to automatically do the reverse (Pro to Standard)--so far as I can tell. I cannot open the Qsys Prime Pro file in Qsys Prime Standard.

Other than manually re-entering the design, does anybody know of a good technique to revert a Qsys Prime Pro (beta) design back to Qsys Prime (non-pro)?
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MAX10 with NIOS does not start program code

November 16, 2016, 11:55 pm
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Hi All,

I have a very peculiar issue. I have a MAX10 10M08SCE144 with a NIOS core that I am trying to get to run at reset. So I got hold of AN730 which describes how to make sure the device is loaded with the program Hex file at reset.

I have followed this guide to the letter for what they call option 2b, which is where the UFM data (hex file) and SOF are combined into a single POF.

in Qsys I have ensured that the Flash is present and connected correctly, with initialisatrion unchecked in both the flash and onchip ram settings, and that the reset vector is set to the flash.

I then go to edit my BSP and makes sure that none of the HAL linker settings are checked as per AN730. I then clean and build the projects. I generate the hex file and go through the convert programming files to turn it into a pof again, as per AN730.

But the NIOS will not startup at reset after power cycling. The code is quite obviously in the UFM, this I know because if I try to load a SOF file into the device the JTAG debugger doing a reset starts the code running, and this cannot be from the SOF itself as the SOF does not contain the NIOS code.

Any ideas why the code would be in there but not starting up at reset?

many thanks
deBoogle
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syncronize nco on different fpga

November 17, 2016, 12:47 am
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Hi,
i've to generate two sinusoidal signals (about 70Hz) with two different altera ip NCO implemented i 2 different fpga (CLK=50MHz and CLK_EN=25khz). The sinusoid is sampled @ 25khz.

The problem is that those signals should have the same phases.

There is available a sync signal for that 2 fpgas. This sync is a pulse with 100ms period and 10ns bit width. Eventually I can change the period.

How could i use this sync signal in order to correct the phase of NCOs and maintain two output signals in phase coherence?

Could you help me? Have you any idea to meet this issue?

Thanks
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SDI II IP Core - 6G

November 17, 2016, 1:27 am
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Hello,
I've got a simple question but I don't understand why it should not work...
Using SDI II IP Core for a 6G-SDI stream, the only available FPGA is Arria 10.
But Cyclone V GT has 6.144Gbps transceiver, so it should be OK...
Is there a technical reason (maybe Cyclone V logic is not fast enough)?
Or maybe we can do 6G-SDI with Cyclone V?
Thanks.
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change pin assignment after synthesis

November 17, 2016, 3:49 am
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hello,
I would like to change pin assignment after synthesis, meaning no need to synthsise the design.
is it poosible at all?
and if it is- how?
Thanks
Yotam
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Cyclone V GX Starter Kit, HDMI, SDCard and LPDDR2

November 17, 2016, 7:05 am
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Hello,

I buy this nice board. And I try create small application. I want:
1. NIOS gets picture from SDCard
2. NIOS puts pixel's information to LPDDR2
3. NIOS sets settings for ADV7213 (HDMI Transsmitter)
4. FPGA gets information from LPDDR2 and transssmit it to HDMI
5. User pushes down button and NIOS gets anouther picture from SDCard.

Now I can read from SDCard. I wrote HDMI module and I can set pixel's color (I have "X" and "Y" from screen.)

But I don't understand how I can use LPDDR2 no my HDMI module. I try start with "LPDDR2 SDRAM Controller with UniPHY v15.0"

For test I want push to LPDDR2 some information and read later. My code:

Code:

always @(posedge HDMI_TX_CLK)
begin
        if (generateImage) begin
                if (lpddr_request == 2'b10)
                        lpddr_request <= 2'b00;
                else begin
                        genX <= genX+1;
                        if (genX >= screenW)
                        begin
                                genX <= 32'b0;
                                genY <= genY + 1;
                        end


                        if (genY >= screenH)
                        begin
                                genY <= 32'b0;
                                generateImage <= 1'b0;
                                lpddr_request <= 2'b00;
                        end else begin
                       
                                lpddr_address = genY*screenW + genX;
                               
                                if (genX >= genY)
                                        lpddr_write <= 32'hFF000000;
                                else
                                        lpddr_write <= 32'h00FF0000;
                               
                                lpddr_request <= 2'b10;
                        end
                end
        end else begin
           
                        if ( ~lpddr_ready )
                        begin
                                lpddr_request = 2'b00;
                                RGB <= 24'hFFFFFF;
                        end else
                       
                        begin
                                lpddr_request = 2'b11;
                                lpddr_address = y*screenW + x;
                                RGB[23:0] = lpddr_read[31:8];
                        end
                       
        end       
end
I calculate "x" and "y" with vertical and horizontal sync.

P.S. I watched all videos on youtube with keywords:"LPDDR2 FPGA Altera and ect".
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Modelsim is exiting with code 211.

November 17, 2016, 7:09 am
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Hi,

every time I try to run a simulation with Modelsim I get:
Code:
Modelsim is exiting with code 211.
Then Modelsim closes.

Transcript says:
Code:
# vsim -gui work.test_counter
# Start time: 15:48:59 on Nov 17,2016
# Loading work.test_counter
# Loading work.counter
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ns  Iteration: 0  Instance: /test_counter File: C:/intelFPGA_lite/16.1/modelsim_ase/examples/tutorials/verilog/basicSimulation/tcounter.v
# FATAL ERROR while loading design
# Error loading design
# End time: 15:48:59 on Nov 17,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
This happens with every file I use. This one was the example so at least that one should work.

I also tried running the simulation from Quartus.

It says something similar:
Code:
# ** Fatal: (SIGSEGV) Bad handle or reference.
#    Time: 0 ps  Iteration: 0  Instance: /half_add_vhd_vec_tst File: Waveform2.vwf.vht Line: UNKNOWN
# FATAL ERROR while loading design
# Error loading design
Error loading design
I am using the ModelSim Starter Edition Intel FPGA 10.5b (Quartus Prime 16.1).
I already tried reinstalling the program, didn't help.

Best Regards
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Fast Clock of ALTLVDS_rx megafunction with external PLL

November 17, 2016, 7:24 am
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Hello, guys. I have a simple question.
I'm creating ALTLVDS_rx megafunction with external pll on Cyclone V. Which high speed clock rate (rx_inclock) should I use?
Support says that C0 (Fast Clock): Freq = data rate, C1: Freq = data rate / serialization factor.
But "LVDS SERDES Receiver IP Core User Guide", page 3, tells us that "The Cyclone series uses DDIO register as part of the SERDES interface. Because data is clocked on both the rising edge and falling edge, the clock frequency must be half the the data rate." ... so Table 3 : "Fast Clock = Data Rate / 2, Slow Clock (outclock) = Data Rate / seralzaion factor".
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how to incorporate 2 cycles of latency

November 17, 2016, 10:10 am
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hello fellow vhdl coders

I have been away from VHDL for over 2 years and I have a question which I am struggling to complete. does anyone know how to incorporate 2 cycles of latency into my vhdl module were i have muxes between 11 buses and an 8 bit output here is the code i have so far.

library IEEE;
use IEEE.STD_LOGIC_1164.all;


entity mux is
port(
clk: in std_logic;
A: in STD_LOGIC_vector(7 downto 0);
B: in STD_LOGIC_vector(7 downto 0);
C: in STD_LOGIC_vector(7 downto 0);
D: in STD_LOGIC_vector(7 downto 0);
E: in STD_LOGIC_vector(7 downto 0);
F: in STD_LOGIC_vector(7 downto 0);
G: in STD_LOGIC_vector(7 downto 0);
H: in STD_LOGIC_vector(7 downto 0);
I: in STD_LOGIC_vector(7 downto 0);
J: in STD_LOGIC_vector(7 downto 0);
K: in STD_LOGIC_vector(7 downto 0);
S0: in std_LOGIC_vector(3 downto 0);


Z: out STD_LOGIC_vector(7 downto 0)
);
end mux;
architecture func of mux is




begin
p: process(clk,A,B,C,D,E,F,G,H,I,J,K,S0)
begin
if(rising_edge(clk)) then
case s0 is

when "0001" => Z <= A;
when "0010" => Z <= B;
when "0011" => Z <= C;
when "0100" => Z <= D;
when "0101" => Z <= E;
when "0110" => Z <= F;
when "0111" => Z <= G;
when "1000" => Z <= H;
when "1001" => Z <= I;
when "1010" => Z <= J;
when "1011" => Z <= K;
when others => Z <=A;
end case;
end if;
end process;






end func;


I have tried to look through my notes when I took this class in university but i just understand how to do cycles of latency is there anyone who can help me out?
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Question about 1 port ram

November 17, 2016, 12:28 pm
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Hello, I am new to VHDL. Currently I need to use M20K memory on Stratix V chip to store some data. I have two of these kind memory, m1 and m2. Each have 128 data, each data is 32 bit. I also use comparator from IP Catalog to do the comparison and pick the smallest 128 numbers among m1 and m2. I am wondering if I can directly add process in the architecture of m1 and m2 to make it easier to do the comparison.

Many thanks for the help.
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