how to interface an ADC with 3 wire SPI (bidir SDIO) to Qsys ?

February 6, 2017, 1:59 am

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Hi,
I need to connect the SPI port of an AD9266 ADC to a Cyclone 5 SoC. This is a 3 wires SPI : clock, CS and bidirectional data (SDIO).
Can I have some hints ? I see that the QSYS SPI module supports only 4 wire SPI. Do I have to write my own vhdl module and
then interface it to QSYS ? Considering that this is probably a common problem, does someone has an example ?
Thanks
Franco

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PCI-E Avalon-ST64: how to get Bus and Device number of card?

February 6, 2017, 2:23 am

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Hello!
I have got fully working design based on Cyclone IV GX and PCI-E 1.0 x1 and using Avalon-ST 64-bit interface from my logic to IP core. All is fine (bus mastering transfers and interrupts), however I have to use BDF (Bus Device Function) as hardcoded constant. Of course, as the result, I'm getting card inoperable in different ports on different computers. I want to get BDF dynamically from PCI-E IP core.

There are tl_cfg interface which may provide me needed bus and device numbers, however this code is not working, when I remove constant (initial bdf = 16'h0200) then through Signal Tap I see bdf as 0000. What I doing wrong? Is this correct that I divide core_clk_out when passing to pld_clk? Is there any easier way to get Bus and Device number?

Code:

---

reg [3:0] cfg_clock;
wire [3:0] cfg_addr;
wire [31:0] cfg_data;
initial cfg_clock = 0;

pcie_core pcie(
// ...
.pld_clk(cfg_clock[3]),
.tl_cfg_add(cfg_addr),
.tl_cfg_ctl(cfg_data),
// ...
);

reg [15:0] bdf;
initial bdf = 16'h0200;
always @(posedge core_clk_out) begin
cfg_clock <= cfg_clock + 1;
if(cfg_addr == 4'hF) bdf <= {cfg_data[12:0], 3'b0}

---

EPCS128 Programming

February 6, 2017, 2:56 am

≫ Next: How to indicate a clk signal is differential in a MAX 10 FPGA

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i want to program epcs128 via jtag
what should i do?

How to indicate a clk signal is differential in a MAX 10 FPGA

February 6, 2017, 6:28 am

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Hello,

I am programming a MAX 10 FPGA and I would like to know how I can tell the device that the clk_in signal I defined in the top module is a differential clock. When compiling the project only one clock node is created (there's no way to know in advance that the signal is differencial, that's obvious) and I wonder if locating it to the CLK_p pin and then physically connecting the negative signal to the CLK_n would work or if I have to use some buffer or something else.
Actually I tried to use a GPIO Lite IP module defining an additional signal in the top module and assigning both as positive and negative. That made the pin planner treat my clk_in signal as differential but on the other hand, the additional signal I created was unasigned and treated as a single signal so in the end it did not work. Any better idea?

Thanks in advance!

Why the tx_serial_data is single ended in 10G BASE R IP

February 6, 2017, 7:00 am

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hi,
why the tx_serial_data/rx_serial_data of 10G base-R is single ended?
Will the quartus insert one diff buf for it if I only use this the single ended tx_serial_data/rx_serial_data as the top pins, then constrain it as lvds signal?

Displaying Binary/Hex Output on VGA

February 6, 2017, 7:50 am

≫ Next: Does Quartus supports Dynamic Array declaration?

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Hi everyone,

I'm currently trying to figure out how to display the output of a 10 bit multiplier as a number on a VGA. The multiplier is built up at component level using the block diagram method on Quartus. I think I need to use VHDL to be able to convert the binary output and display it on the VGA, but this is something I have never done before. I currently have a binary and/or hexadecimal output available. Any advice?

Thanks

Does Quartus supports Dynamic Array declaration?

February 6, 2017, 9:09 am

≫ Next: How redirect an analog signal to another pin.

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Hi,

I was wondering anyone here knows whether the Altera Quartus II supports SystemVerilog's new Dynamic Array Declaration, which allows run-time array dimension reconfigruation?

For example,

reg [7:0] array[];

array = new[4];
array = new[8](array);

which allows we dynamically change the dimension of the array at run-time. I have tried to compile the code in Quartus II 15.0 and 13.0.sp1, but get errors. Anybody can help?

Thanks,

-Roger

How redirect an analog signal to another pin.

February 6, 2017, 11:07 am

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Hello, It's possible redirect an analog input signal to another pin in FPGA (DE0 nano), or a way to implement a simple buffer DAC on VHDL ?

I'm trying to multiplex signals provided from a vga controller to make a video wall. But, as red, blue and green signals are analog, i can't redirect this signals to be displayed.

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Max 10 CRC Error Detection Register Access

February 6, 2017, 12:24 pm

≫ Next: Hardware module connection to NiosII

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The Max 10 (10M08SAE144C8G) has a built in configuration CRC checker. As part of that it has a stored CRC value that it compares against a computed value on power-up. I'd like to access both the stored and computed value from outside the FPGA. From the documentation I've read ("MAX 10 FPGA Device Architecture") it seems like this should be possible. I can't quite figure out how to access these registers from within the HDL. Is there anybody out there who has done this before and can point me in the right direction?

Hardware module connection to NiosII

February 6, 2017, 12:54 pm

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Hello,

I want to connect a hardware module implemented in Verilog with NiosII processor. The module has an output of 40 bits with an update rate of 500us. At the moment I have implemented the connection using IOs but the problem is that the processor reads the output register many times cause it runs faster and i don't know if the module has been updated or I read an older value. I really also want to avoid interrupts. I tried again by creating a counter in the module which increases by one every time the value is updated so I can discard the reading if the counter has the same value but I want something more general like a FIFO. What would be the best solution to my problem. I am thinking of ST-Avalon dual clock FIFO but I have no prior experience with that block, can anyone help me?

How to find a IP is free or requires license ?

February 6, 2017, 6:54 pm

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I'm looking to use LVDS Serdes IP and just checking about it to see its free or requires license. The user guide does not provide clear information It states a generic statement.

Incase of other vendors, there would a lock logo next to that IP in the IP catalog. Is there anything of that sort is available with altera.

Did i miss to see anything,

--
Thanks
Rajesh

Verilog ModelSim beginner Hello

February 6, 2017, 9:18 pm

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Hello im new to this forum, and i just started verilog. I was wondering if anybody knows how to work ModelSim well. I can't seem to find my files after i save them and then try to compile them...if you can tell me how to add files to a library that would be great. thank you

Cyclone-V changing off-chip signal timing using IObuf delays

February 6, 2017, 10:49 pm

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Because of routing differences in a bus system we want to experiment with input IO-buf delays of a cyclone.

The D3_delay and D1_delay options in the quartus assignment editor are available but I do not know their value range and units (sec/usec/??). Does anyone has info on this.

Performance improved when using FAST_INPUT_REGISTER assignment on the bus clock signal. Is this attribute the counterpart of D1/D3_delay or can these be combined?

Altera PLL timequest nets

February 7, 2017, 2:17 am

≫ Next: arria V FPP programing doesn't work

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Hello,

I have an Integer PLL instantiated in my Cyclone V SOC design.
In Timequest, I noticed 2 possible nets to choose from for this PLL:

1. "FRACTIONAL_PLL_O_VCOPH0"
2. "outclk_wire[0]"

Which one is correct for an Integer PLL ?

arria V FPP programing doesn't work

February 7, 2017, 2:48 am

≫ Next: MAX V 1532 file

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hi,
I have a problem trying to program my arria V using a CPLD.
I am using a compressed rbf file and the MSEL pins are set as needed "10110" for compressed file with FPP x8 bit programming scheme.
the Dclk to Data Ratio is 2 and the Dclk freq is 25MHz.
I toggle the nConfig and receive an Ack from the nStatus however the conf_done never rises and no error is reported on the nStatus (remains high).
Is there a known issue with using this configuration scheme in arria V device ?
Can someone suggests me with a debugging possibility?

thanks

It drives me crazy !!!!:cry:

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MAX V 1532 file

February 7, 2017, 3:31 am

≫ Next: UBIFS size issue

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I'm looking for the 1532 file available for the MAX 5M570ZT100. The datasheet web link is broken & searching the website shows nothing for MAX V devices. It's quite frustrating when the datasheet says it is 1532 compliant but then points to non existent pages. There also seems to be nothing within these forums. Does anyone know if this file exists or what instructions I can use in the standard bsdl file. I'm performing bscan testing & wish to incorporate 1532 concurrent programming.
Many Thanks,

UBIFS size issue

February 7, 2017, 5:30 am

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Hello,

I am working with UBIFS,

When I am giving 55MiB of vol size, by following command
ubimkvol /dev/ubi0 -N vol -s 55MiB

I could able to see only, 49 MiB of space when Kernel boot-up.
Can any one please, give me some inputs regarding same.
Thanks,
Ashwin Rase

arria10 fitter conflict for pin assignment

February 7, 2017, 5:54 am

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hi, all
I use arrio 10 with altera mac+phy ip. how ca I fix this conflict ?
project.qsf:

set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115U3F45E2SG
#Bank GXBL1F
set_location_assignment PIN_AG42 -to tx_serial_data_p[0]
set_location_assignment PIN_AF44 -to tx_serial_data_p[1]
#Bank GXBL1F
set_location_assignment PIN_AG38 -to rx_serial_data_p[0]
set_location_assignment PIN_AF40 -to rx_serial_data_p[1]

I get error log:
Info (11684): Differential I/O pin "tx_serial_data_p[1]" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "tx_serial_data_p[1](n)"
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (12677): No exact pin location assignment(s) for 103 pins of 108 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 HSSI_PMA_TX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number.
Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF, which is within Arria 10 Transceiver Native PHY low_latency_baser_altera_xcvr_native_a10_161_gvv75 qa.
Info (14596): Information about the failing component(s):
Info (175028): The HSSI_PMA_TX_BUF name(s): hft_ethernet_multichan:u_hft_ethernet_multichan|al tera_eth_10g_mac_base_r_low_latency_wrap:packet_di v_channels[1].i_u_altera_eth_10g_mac_base_r_low_latency_wrap|lo w_latency_baser:baser_inst|low_latency_baser_alter a_xcvr_native_a10_161_gvv75qa:xcvr_native_a10_0|tw entynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev _20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_tx_ buf.inst_twentynm_hssi_pma_tx_buf
Error (16234): No legal location could be found out of 96 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between the HSSI_PMA_TX_BUF and destination HSSI_RX_PCS_PMA_INTERFACE
Info (175027): Destination: HSSI_RX_PCS_PMA_INTERFACE hft_ethernet_multichan:u_hft_ethernet_multichan|al tera_eth_10g_mac_base_r_low_latency_wrap:packet_di v_channels[1].i_u_altera_eth_10g_mac_base_r_low_latency_wrap|lo w_latency_baser:baser_inst|low_latency_baser_alter a_xcvr_native_a10_161_gvv75qa:xcvr_native_a10_0|tw entynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_re v_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev _20nm5:inst_twentynm_pcs|gen_twentynm_hssi_rx_pcs_ pma_interface.inst_twentynm_hssi_rx_pcs_pma_interf ace
Error (175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements
Info (175021): The HSSI_RX_PCS_PMA_INTERFACE was placed in location HSSIRXPCSPMAINTERFACE_1F1
Info (175029): 94 locations affected
Info (175029): HSSIPMATXBUF_1C0
Info (175029): HSSIPMATXBUF_1C1
Info (175029): HSSIPMATXBUF_1C2
Info (175029): HSSIPMATXBUF_1C3
Info (175029): HSSIPMATXBUF_1C4
Info (175029): HSSIPMATXBUF_1C5
Info (175029): HSSIPMATXBUF_1D0
Info (175029): HSSIPMATXBUF_1D1
Info (175029): HSSIPMATXBUF_1D2
Info (175029): HSSIPMATXBUF_1D3
Info (175029): HSSIPMATXBUF_1D4
Info (175029): HSSIPMATXBUF_1D5
Info (175029): and 82 more locations not displayed
Error (175003): The HSSI_PMA_TX_BUF location is occupied (2 locations affected)
Info (175029): HSSIPMATXBUF_1F0. Already placed at this location: HSSI_PMA_TX_BUF tx_serial_data_p[0]~output_PMA_TX_BUF_FITTER_INSERTED
Info (175029): HSSIPMATXBUF_1F1. Already placed at this location: HSSI_PMA_TX_BUF tx_serial_data_p[1]~output_PMA_TX_BUF_FITTER_INSERTED

failing.paths.rpt

February 7, 2017, 6:35 am

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After an apparent successful compile with 0 errors reported and an aocx file created,
if one looks into the directory with log and rpt files there can be rpt files such
as top.failing_paths.rpt, and top.failing_clocks.rpt with info such listed below.

What is the significance of these rpts. Should there be a recompile with different parameters?
If so, how would one set such parameters when aoc is being used to compile the kernels?

Thanks,

Dan..


[poz@nallatech boardtest_ts_sram_sl]$ grep Worst *fail*.rpt
top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.556
top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.310
top.failing_paths.rpt:Report Timing: Found 5 hold paths (5 violated). Worst case slack is -0.019
top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.423
top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.221

top.failing_paths.rpt:Report Timing: Found 5 hold paths (5 violated). Worst case slack is -0.056


Clock domains failing timing
+--------+---------------+----------------------------------------------+-----------------------+-----------------+
; Slack ; End Point TNS ; Clock ; Operating conditions ; Timing analysis ;
+--------+---------------+----------------------------------------------+-----------------------+-----------------+
; -0.556 ; -98.123 ; board_inst|ddr3b_core_usr_clk ; Slow 900mV 100C Model ; Setup ;
; -0.423 ; -60.327 ; board_inst|ddr3b_core_usr_clk ; Slow 900mV 0C Model ; Setup ;
; -0.310 ; -63.934 ; board_inst|pcie|wys~CORE_CLK_OUT ; Slow 900mV 100C Model ; Setup ;
; -0.221 ; -23.398 ; board_inst|pcie|wys~CORE_CLK_OUT ; Slow 900mV 0C Model ; Setup ;
; -0.056 ; -10.906 ; board_inst|kernel_clk_gen|kernel_pll|outclk0 ; Slow 900mV 0C Model ; Hold ;
; -0.019 ; -0.151 ; board_inst|kernel_clk_gen|kernel_pll|outclk0 ; Slow 900mV 100C Model ; Hold ;
+--------+---------------+----------------------------------------------+-----------------------+-----------------+

dwc2 ffb40000.usb Overcurrent change detected

February 7, 2017, 7:17 am

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I get the message when writing to OTG/USB (de0-nano-soc)

dwc2 ffb40000.usb Not connected
dwc2 ffb40000.usb Overcurrent change detected
-- then my attached storage is gone till the next reboot

- while investigating i have removed the supply to the USB device & am powering externally
therefore there should be NO over current (current to external device is <100ma so should still not have an issue )

there are no devices being powered off the board - only load is the fpga & support circuitry on the board
(running both processors {linux kernel 4.4.0) , one instance of NIOSII & one of msgdma)
works fine when writing to local SDcard...

next guess is a heating issue - as it seems to function while cold but within 5-10min it fails as above .. ..

any hints ? should i be looking at heatsinks & fans (uuggh) ?