SignalTap autotriggers constantly without meeting conditions

February 7, 2017, 9:12 am

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Is there a reason SignalTap offloads acquisitions immediately after "Run Analysis" is requested, even when trigger conditions are not met? I tried removing and adding the *.SDC timing commands to meet Timequest Contraints (to no effect):

Code:

---

set_input_delay                                    \
    -clock [ get_clocks altera_reserved_tck ]    \
    10.0                                        \
    [ get_ports {                                \
        altera_reserved_tms                    \
        altera_reserved_tdi                        \
    } ]


set_output_delay                                \
    -clock [ get_clocks altera_reserved_tck ]    \
    10.0                                        \
    [ get_ports { altera_reserved_tdo } ]

---

There's not much to configure in Qsys for JTAG. The Nios II system is fed a 100Mhz clock, which I used as the trigger clock. Setting conflicting triggers (EOP and SOP both high, *all* signals to 0xFFFFF, no signals at all) seems to simply always trigger an acquisition. I'm trying a bunch of different things but to no avail. Hmmmmm....

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Max 10 Unconstrained clock in onchip_flash

February 7, 2017, 10:40 am

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I'm working on a design using MAX 10: 10M08SAE144C8G and I'm implementing and I2C RSU circuit. TimeQuest complains of an unconstrained clock as follows:
FLASH_LOADER_CORE:FLASH_LOADER|MAX10_FLASH_INTERFA CE:Max10FlashInterface|MAX10_FLASH:FlashModule|alt era_onchip_flash:onchip_flash_0|altera_onchip_flas h_avmm_data_controller:avmm_data_controller|flash_ se_neg_reg

Using the Technology Map Viewer is see that this signal is generated by the altera_onchip_flash_avmm_data_controler:avmm_data_ controller and is the output of a flip-flop. This signal is then routed into the SE input of the ufm_block.

Can anyone confirm that this is not a clock?
Perhaps I did not properly instantiate the IP?

I want to properly define the constraints for this signal.
Thanks in advance for any assistance.

java crash when opening Qsys on windows 10

February 7, 2017, 1:42 pm

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Hello there,

Im fairly new to quartus and im having an issue with Qsys. When i try to open Qsys from quartus, im getting a Java crash message. Note that i have Quartus 16.1 with update 2 installed on a windows 10 system. Could this be an issue with compatibility with windows? I have also tried to run the Qsys in windows 7 compatible mode and it still did not work. Also, i saw on a old post that it might be because of any current JRE installed in the computer, but i dont seem to have any java related software installed on my computer besides quartus itself.

Anyone might have a clue on the issue?

Thanks
Renato

BASE-R Transceivers on Stratix V FPGA

February 7, 2017, 2:29 pm

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Hi,

I am trying to use 2 BASE-R transceivers on a Stratix V FPGA to connect to two of it's SFP+ ports so that I can send/receive data between the SFP+ ports and an SPF modules (a basic external loopback for testing). I have the transceivers and reconfiguration controllers instantiated and the SFP+ port pins assigned to the appropriate pins on the Stratix V chip. My question is (being fairly new at all of this), how can I send some actual data, say a test bit, to an SFP module and record it being received at the other SFP+ port? Is there some additional Altera IP I am missing?

Thanks in advance

Mixing byte addressable and word addressable memories in a design

February 7, 2017, 2:47 pm

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I have a design with several byte addressable memories and also several word addressable memories. When I don't check the "read memory as byte addressable", I get warnings for the byte addressable memories that they have been read as word addressable and the opposite when I check it (warnings for word addressable memories read as byte addressable). Is this a problem? Is there any way to resolve this correctly?

DEO nano specifications

February 7, 2017, 5:41 pm

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I am looking at using the DEO Nano Kit to output data through the GPIO port. I see that it has Gb Ethernet. I need to get data from PC through Ethernet port and output the data to GPIO pins.
Here are my specifications, can it do it?:
Receive data from the Gb Ethernet port at 12 MB/s.
Generate a clock pulse at 6 MHz.
At every pulse cycle, do the following:
Transpose one bite of data to 8 GPIO output pins.
Use the other byte to adjust the pulse width of a nibble from the first bit.
Repeat this for 400 cycles.
Set GPIO and clock output to all low.
Wait 25 cycles.
Repeat through 2 GB of data. Total time of operation is about 200s

I could get the data from the SD card.

Can it do both of these?
Thank you

Not able to resolve "#include "

February 7, 2017, 9:00 pm

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Hi,

I am using NIOS II EDS 9.1 to generate a sample project from template.

I am able to build sample project.

Then i added below include file.

#include <stdint.h>

int main ()
{
uint32_t test;
}

I am getting below error and warnings:

error : `uint32_t' undeclared (first use in this function)

warning: stdint.h: No such file or directory

I have verified that stdint.h is present in system generated includes folder in "C:\altera\91\quartus\bin\cygwin\usr\include "

How to resolve this problem

Licensing Quartus II through remote license server

February 8, 2017, 1:26 am

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Hi all!
I have floating license for Quartus II software and I have configured license server. I was using floating license on other PCs which were connected to license server PC with LAN connection as it is explained in all ALTERA official documents. Now I want to use license from PC which is not in LAN connection with server PC, but I don't know how because I did not find any document that is talking about that case. All documents all talking about case when PCs are in "network connection", where you can easily point to license from some local PC just by typing <port_number>@<host_name>; obviously they were thinking on LAN connection because I don't see way how some PC which is not in LAN connection with license server could find license server just by host name and port number.

Of course, I have found similar thread on this forum: http://www.alteraforum.com/forum/showthread.php?t=44489

, and I have tried all mentioned suggestions but neither of them didn't work.

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Problem while running"Run functional simulation"

February 8, 2017, 2:10 am

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Hello,

when I have used 13.0 service pack 1.0(30 trial edition) at that for the same project I am not getting this error. But when I installed 13.1 QuartusII web edition I am getting this error.

Code:

---

Determining the location of the ModelSim executable...
Using: c:/altera/13.1/modelsim_ae/win32aloem/

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Multiplier -c Multiplier --vector_source=D:/DINESH/d work/Altera/Multiplier/Waveform2.vwf --testbench_file=D:/DINESH/d work/Altera/Multiplier/simulation/modelsim/Waveform2.vwf.vt

Error (23028): Unknown argument "work/Altera/Multiplier/Waveform2.vwf". Refer to --help for legal arguments.


Usage:
------


quartus_eda [-h | --help[=] | -v]
quartus_eda  []
quartus_eda -t
Error.

---

Epm570t100i5n - cpld ser

February 8, 2017, 5:15 am

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Hello everyone,


We are started using this CPLD in our new IO board. As a part of FMEA, we have calculated the FIT value based on the number of gates count.

EPM570T100I5N - IC CPLD 440MC 5.4NS 100TQFP

Based on the gates count the FIT value : 33.777476 generated from PTC windchill 11.0 tool

Now we are looking for the SER value for this CPLD. Could any one help on this.

Thanks & Regards,
Krishna M

PCIe in MAX10

February 8, 2017, 7:04 am

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I have seen on some product selection guides and in a pdf posted late 2014 that the MAX10 devices should support PCI Express.

However Quartus does not list this as available in the IP Core selections.

Anybody that knows if it is possible or not to implement in a MAX10 device?

Quartus Lite wto program the DE1-SOC development board?

February 8, 2017, 7:37 am

≫ Next: report_net_timing results values and units?

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Hi,

Can I use Quartus Lite with the Cyclone 5 devices installed to program the DE1-SOC development board? The manual says to use Quartus II but I guess it is out of date.

Is there an auto-detect feature in Quartus Lite?

Thanks
R

report_net_timing results values and units?

February 8, 2017, 7:45 am

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I've got various ring oscillator circuits that I'd like to get delay timing information for.
report_net_timing on the delays in a ring gives results in a table like the one below:


; # ; Node Name ; RR ; FR ; RF ; FF ; Destination Pin Name ; Location ;
; 1 ; "myNode2"|combout ; 0.207 ; ---- ; ---- ; 0.185 ; "myNode3"|datac ; LABCELL_X27_Y12_N36 ;
; 1 ; "myNode1"|combout ; 0.212 ; ---- ; ---- ; 0.178 ; "myNode2"|datac ; MLABCELL_X28_Y12_N36



I can't seem to find what RR, FR, RF, and FF stand for or what are the units for those values (RR,FR,RF,FF) in the table.

Any help or direction would be appreciated!

(FYI, using Arria 10)

Constraining source syncronous output

February 8, 2017, 12:02 pm

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Hi all,

I'm trying to understand the constraining of source synchronous interfaces. I am a little bit confused. Let’s say we have an interface to an external SDR SDRAM device. The latch clock for the SDRAM is phase shifted by 180° inside the fpga with respect to the launch clock of the output register. Now we want to define the max output delay. In different documents i found the following equation:

max output delay = data_trace_delay_max - clk_trace_delay_min + set_up_time

And then i heard in an online training video from altera, that the max output delay specifies the maximum amount of time available to output a signal and still meet the setup time of the external device.

But why becomes this available time bigger, when the data trace delay becomes longer? Would a bigger trace not mean that we have less time available to bring our data to the output of the fpga? Or do I have misunderstood something?

I'd appreciate if someone could resolve my confusion

thanks in advance!

Looking for a Development Kit (or Daughter Card) to test SFP+ transceiver

February 8, 2017, 1:37 pm

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Hello, I want to test out a SFP+ transceiver and am looking for a Development Kit or a Daughter card that has an SFP+ connector. If anyone knows of a board please let me know.

Thanks,
Joe

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Altclkctrl ip

February 8, 2017, 4:20 pm

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Hi,

I am using ALTCLKCTRL to mux two clock signals. One of the signal is a PLL output and the other one is an from the clock pin.
I get an error from the fitter stating that it cannot place a global clock driver between the clock pin and the clkctrl block.

I also try to drive the input pins of clkctrl by a clock buffer output (another clkctrl block ; path wold be pinà clkctrl(buffer)àclkctrl(mux)). But it seems that this is illegal.

Can someone guide me with this?

Thanks,
Vittal

DE0-Nano Problem booting into Linux using examples

February 8, 2017, 5:24 pm

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Hi,
I followed instructions in "DE0-Nano-SoC_Getting_Started_Guide" and it was fine until Chapter 5.4 Running Linux on DE0-Nano-SoC board.

I think I have followed the instructions strictly but perhaps somewhere went wrong.

Symptom:
When I opened PuTTY and started a serial session, PuTTY gave me a black console. Nothing was there except a small green block. Where it should be some booting info and wait me to type "root" to log in.

What I have noticed/tried:

1. In Section 5.2 (preparing microSD card), I found the unzipped image "DE0_Nano_SoC_Linux_Console.img" cannot be mounted by windows. I tried downloading multiple times, and it did not help.
2. In the same section, I noticed that the volume of prepared microSD card had been changed. The kit I purchased comes with a 4GB microSD and it became 817 MB after using Win32 disk imager. Same thing happened to another SD card of mine.
3. The prepared microSD contains following files/folder:

a. Temp (empty folder, probably generated by my zip software)
b. de0_nano_soc.rbf
c. socfpga.dtb
d.u-boot.scr
e.zImage

The total size of these files is merely about 6 MB. I suspect something is missing.

4. When PuTTY gave me a black screen, I detached the usb on the DE0_Nano side while leaving the usb cord connected to the laptop. And the PuTTY did not give any error.
5. When I open the port COM4 (the port for my DE0_Nano), the default speed was 9600 instead of 115200. My setting on PuTTY was 115200. I have tried both speeds but didn't help.

How can I fix this problem? Thank you.

SD Card for SOPC with Fat32

February 8, 2017, 11:05 pm

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Hello,

I have a Cylone II board with a Micro SDCardon it. I would use a Fat32 formated Card und Quarts 9.0 SP2. Are there some IP Core forte SOPC builder to save some data (no Pictures) on this Card?

Thanks for your help.

The win7 device manager detects nothing when JTag is connected to laptop

February 9, 2017, 12:22 am

≫ Next: Running a CYCLONE above its rated temperature

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I tried to use the JTag cable by connecting it to the USB port of my laptop.
By following the instruction of driver installation:
https://www.altera.com/support/suppo...ter-vista.html
After the USB port is connected with the JTag cable, the "Windows Found New Hardware dialog box" should show up, or we should see a new item in the device manager show up, then we can proceed to install the driver for it.

However, when I connect the JTag to USB port, there is nothing happening in my laptop.
"Windows Found New Hardware dialog box" doesn't show up, and there is nothing new in the device manager.
It looks like there is nothing detected in my laptop, so I can't do anything to change the driver setup for the JTag.

There is no problems about the USB ports of the laptop since I have checked them with other devices.

What should I do to solve this problem or is there any reference about it?
Thank you.

Running a CYCLONE above its rated temperature

February 9, 2017, 1:37 am

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Hi,

If I am running a T144 part which is rated for around 80 degrees C what would one expect to happen up to around 120 degrees Celsius? This will be the ambient temperature the device is running in for up to an hour max. The synthesized design will not be dense at all and relatively passive in nature, some registers and multiplexing. Running in the 1MHz range max.

I have tried the E144 parts yes but these are hard to hand solder onto custom boards due to the ground pad underneath. I was wondering if the T144 would die immediately or survive the temperatures for a while before packing it in.