February 9, 2017, 2:06 am
Hi All,
Each time I change a file (RTL, etc) outside of the Quartus-II, a window pops up asking whether I want to reload it in Quartus-II.
What settings should I do so that the file will be reloaded automatically?
Thank you!
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February 9, 2017, 7:50 am
Hello Forum Administrator,
I have a general question about the private messaging system.
Is it active on this forum / is it for a selection of people only?
If not, what are the advantages of the "friends" system. How can I get in touch with friends in a private context ?
Many thanks for a response.
Johi.
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February 9, 2017, 8:39 am
Hi everyone,
I am trying to write a vhdl program that takes a input R and a shifted version of it and adds them, then adds the result to a 2nd shifted version of R and then AND's it with a mask. (basically calculating the mod).
Here is the code i have so far but i am not sure how to append Cout to the input of my AND so that i make sure to and S+Cout AND Mask :
PORT
(
R : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
MASK : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OutRem : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END g18_lab2_RNG;
ARCHITECTURE bdf_type OF g18_lab2_RNG IS
COMPONENT g18_lab2
PORT(A : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Cin : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Cout : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL RShift1: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL RShift2: STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
RShift1 <= STD_LOGIC_VECTOR(unsigned(R)sll 1);
RShift2 <= STD_LOGIC_VECTOR(unsigned(R)sll 16);
b2v_inst : g18_lab2
PORT MAP(A => R,
B => RShift1,
Cin => '0',
S => SYNTHESIZED_WIRE_1,
Cout => SYNTHESIZED_WIRE_0);
b2v_inst2 : g18_lab2
PORT MAP(A => RShift2,
B => SYNTHESIZED_WIRE_1,
Cin => SYNTHESIZED_WIRE_0,
S => SYNTHESIZED_WIRE_2,
Cout => ;
OutRem <= SYNTHESIZED_WIRE_2 AND MASK;
END bdf_type;
EDIT: i figured out i can use & to concatenate bits so i changed my Cout to : Cout => SYNTHESIZED_WIRE_3
and then : OutRem <= SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_2 AND MASK;
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February 9, 2017, 12:51 pm
In university lab we have DE3 board (Stratix III) and we have Quartus 16.1 Somehow there is no support for Stratix III after Quartus 13.1 version. We can't use this board in Quartus and we don't want to degrade to 13.1 version because we have other DE boards etc as well. I wonder is it possible to use Stratix III device with latest Quartus version?
Best,
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February 9, 2017, 3:28 pm
Hi all,
when I try to use Quartus built in integer comparators I am experiencing some problem. I am trying to sort 64 numbers stored in a 2 port RAM. When I input the addresses and get back 2 integers, then I send these 2 integers into the built in comparator. The compare result is showing in next rising edge of the clock, but when I try to use IF statement to choose the small numbers, it seems that the comparing result detected is for last pairs. Can anyone help? Many thanks for the help.
The simulation result shows as follows:
![]()
Code:
------------- send address to m1 to get number ---------------------
if (rd_adr_a < 62) then
m1_rden_a <= '1';
m1_rden_b <= '1';
m1_wren_a <= '0';
m1_wren_b <= '0';
m1_adr_a <= std_logic_vector(to_unsigned(rd_adr_a, 7));
m1_adr_b <= std_logic_vector(to_unsigned(rd_adr_b, 7));
rd_adr_a := rd_adr_a + 2;
rd_adr_b := rd_adr_b + 2;
else
m1_rden_a <= '0';
m1_rden_b <= '0';
end if;
-------------- get m1 feedback, compare, and store to m2 ------------------
if (wr_adr_small < 62) then
if (rd_delay < 3) then -- 3 clock cycle delay to wait m1 send back data
rd_delay := rd_delay + 1;
else
cp_dataa <= m1_q_a;
cp_datab <= m1_q_b;
if (cp_delay < 1) then -- 1 cc omparator delay to wait comparator give result
cp_delay := cp_delay + 1;
else
if (cp_eq = '1') then
m2_rden_a <= '0';
m2_rden_b <= '0';
m2_wren_a <= '1';
m2_wren_b <= '1';
m2_data_a <= cp_dataa;
m2_data_b <= cp_datab;
m2_adr_a <= std_logic_vector(to_unsigned(wr_adr_small, 7));
m2_adr_b <= std_logic_vector(to_unsigned(wr_adr_big, 7));
wr_adr_small := wr_adr_small + 2;
wr_adr_big := wr_adr_big + 2;
elsif (cp_gr = '1') then -- q_a > q_b
m2_rden_a <= '0';
m2_rden_b <= '0';
m2_wren_a <= '1';
m2_wren_b <= '1';
m2_data_a <= cp_datab;
m2_data_b <= cp_dataa;
m2_adr_a <= std_logic_vector(to_unsigned(wr_adr_small, 7));
m2_adr_b <= std_logic_vector(to_unsigned(wr_adr_big, 7));
wr_adr_small := wr_adr_small + 2;
wr_adr_big := wr_adr_big + 2;
elsif (cp_ls = '1') then -- q_a < q_b
m2_rden_a <= '0';
m2_rden_b <= '0';
m2_wren_a <= '1';
m2_wren_b <= '1';
m2_data_a <= cp_dataa;
m2_data_b <= cp_datab;
m2_adr_a <= std_logic_vector(to_unsigned(wr_adr_small, 7));
m2_adr_b <= std_logic_vector(to_unsigned(wr_adr_big, 7));
wr_adr_small := wr_adr_small + 2;
wr_adr_big := wr_adr_big + 2;
else
end if;
end if; -- end delay1cc
end if; -- end delay3cc
end if;
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February 9, 2017, 3:56 pm
Hi,
I just started programming in VHDL for a computer architecture class and I was wondering if it was normal that when I type in: library IEEE; use IEEE.STD_LOGIC_1164.all; it shows up as:
library IEEE; use IEEE.STD_LOGIC_1164.all;
In the examples I have, the whole line shows up in blue. Does it mean the library isn't working?
Thanks!
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February 9, 2017, 4:54 pm
Hi,
I'm doing a Moore FSM, and the outputs are 7 bits buffers (declared as such:
sum: out STD_LOGIC_VECTOR(6 down to 0);
)
When writing the output logic, I wrote:
when S2 => sum <= '0001010';
but that gives me an error for each of these instances. What would be the correct syntax for what I'm trying to do?
Thanks!
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February 9, 2017, 7:00 pm
I use the Quartus || version13.0 (Need support MAX 3000A series) and trying to generate the JBC file(Uncompressed), from the Altera website, mentioned the quartus_jbcc.exe can generate the uncompressed jbc file(Since Quartus || version13.0 only can generate the compressed jbc file ), I tried the quartus_jbcc.exe, but the result is that it generated the same jbc file with compressed, how could I generate the uncompressed jbc file with Quartus || version13.0 ?:confused:
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February 9, 2017, 10:39 pm
Hi guys,
I'm trying to create a hash algorithm (a very simple one) for homework exercise.
I basically have taken an input from the user and hash it using:
a = 1, b =2, c = 3 ... z = 26.
So if the user input is abc, it will store 123.
My functions for creating a username and password so far:
Code:
// registering an account
void regAccount(){ cout << "Please enter your username: "; cin >> inputUsername; cout << endl; if (inputUsername == username[0] || inputUsername == username[1] || inputUsername == username[2] || inputUsername == username[3] || inputUsername == username[4] || inputUsername == username[5] || inputUsername == username[6] || inputUsername == username[7] || inputUsername == username[8] || inputUsername == username[9]) { cout << "Username already exists" << endl; } else { for (i = 0; i < 10; i++) { if (username[i] == "Empty") { username[i] = inputUsername; hashPass(); cout << "Is this account an admin? - 1 = yes / 2 = no: "; cin >> input; if (input == 1) { admin[i] = true; } else { admin[i] = false; } break; } } } }// hash the passwordvoid hashPass(){ cout << "Please enter your password: "; cin >> password[i]; cout << endl; for (int j = 0; j < password[j].length(); j++) { // possibly a switch statement checking if password[i] == a, b, c... } }
Thanks for having a look.
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February 9, 2017, 11:37 pm
HELLO,
Its PLEASURE this kind of medium TO FOR DISCUSSION OF PROBLEM REGARDING VERILOG CODE.
I am beginner of the Verilog and i am learning verilog, how to call module write testbench..etc
I REQUIRE verilog CODE THAT CAN TEST ALU USING BIST(built-in self test) METHOD (TEST PATTERN GENERATOR...> ALU......> RESPONSE ANALYZER).
ALU OPERATION FOR 4 BIT ADDITION, SUBTRACTION, MULTIPLICATION.. etc
pls help require code.
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February 9, 2017, 6:08 am
Hello,
I'm using NIOSII-Eclipse and Quartus13.1 on Windows 7. The NIOSII-Eclipse comes with gcc 4.5.3. While my c++-Project is using a large number of files, it seems that I hit the 32k limit on arguments when linking the project. This leads to a make-Error while linking my project:
nios2-elf-g++: error: CreateProcess: No such file or directory
Building process works fine. When I remove some files from Nios II Build everything is working fine, too.
I read about possible reasons and solutions for that error and it seems that using the option @FILE might be a workaround. But how can I use it when building and linking the project in the IDE?
Is there any (other) solution for that problem?
Thanks.
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February 10, 2017, 7:13 am
Hello, I am new here and i know little to nothing about using anything Quartus related.
But I have ran into an issue, I bought a developement board from ebay which has Cyclone IV, but I can't seem to find my chip in the Quartus II device list.
The chip is EP4CE6E22C8N, the program has the chip without the "N" at the end, so i was wondering if I need a new board, or is there support for this device.
Thank you.
The board I'm using:
http://www.ebay.com/itm/Altera-Cyclo...sAAOSwu4BVyLY5
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February 10, 2017, 11:25 am
Hello,
We need some way to transfer files through serial in order to program flash.
Is it possible to do that in ucos ?
Best Regards,
Ran
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February 10, 2017, 10:38 pm
Hello everyone,
Does anyone know if I can insert an s-parameter model of the FPGA power delivery network in Quartus or ModelSim functional/timing simulations? Has anyone done this already?
Thank you,
Cosmin
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February 10, 2017, 11:10 pm
Hello,
I am beginner with Micrium uc/os , so my question might be sound trivial for others, excuse me for that.
We have a requirement to be able to flash program when running uc/os.
I just wander how it generally should be done with uc/os.
As far as I read uc/cos does not have a shell (like linux/dos).
Does it mean I need to create some thread with user-menu, or a thread listening for file transfers (kermit/xmodem) ?
I tried to read some uc/os documentation, yet haven't grasped how this is generally done with uc/os.
Thank for your ideas,
Ran
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February 11, 2017, 5:04 am
Hi everyone, I am getting this error when I am trying
new-> Nios II Application and BSP from Template
Compilation is successful in Quartus. But I can not create a Project in eclipse.
I am using the version 13.0sp1.
Thanks for the answers.
INFO: Finished initializing SOPC project local software IP. Total time taken = 4 seconds
INFO: Searching for BSP components with category: driver_element
INFO: Searching for BSP components with category: software_package_element
INFO: Loading drivers from ensemble report.
INFO: Finished loading drivers from ensemble report.
SEVERE: Setting does not exist for BSP: "hal.stdın".
WARNING: Tcl script "bsp-set-defaults.tcl " error: Setting does not exist for BSP: "hal.stdın".
SEVERE: Setting does not exist for BSP: "hal.max_file_descriptors".
SEVERE: Setting does not exist for BSP: "hal.max_file_descriptors".
SEVERE: nios2-bsp-create-settings failed.
nios2-bsp: nios2-bsp-create-settings failed
nios2-bsp hal . C:/altera/13.0sp1/proj_Helloworld/proj_qsys.sopcinfo --set hal.max_file_descriptors 4 --set hal.enable_small_c_library true --set hal.sys_clk_timer none --set hal.timestamp_timer none --set hal.enable_exit false --set hal.enable_c_plus_plus false --set hal.enable_lightweight_device_driver_api true --set hal.enable_clean_exit false --set hal.enable_sim_optimize false --set hal.enable_reduced_device_drivers true --set hal.make.bsp_cflags_optimization '-Os' --cpu-name nios2_qsys_0 failed
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February 11, 2017, 5:47 am
I am using Quartus Prime 16.1 on Windows, targeting Arria 10. Although I also encountered the problem on the Linux version. For some reason when I add the "Hard IP for PCI Express" I cannot edit the widths/size of any of the BARs, neither in the initial wizard window nor in the Parameter window after it has been added to the Qsys project.
No matter what parameters I set, the BAR cannot be edited, and as a result it produces an unfixable error.
I even tried manually editing the backing *.ip file but the change is not reflected in the GUI.
Anybody encounter this? Or at least has anybody confirmed a version of the software where this ISN'T a problem?
Screenshot attached. You can see the field greyed out.
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February 11, 2017, 9:48 am
Hi.
I have bought an FPGA from ebay, like this one:
http://www.ebay.com/itm/Altera-Cyclo...sAAOSwu4BVyLY5
But the problem is, I can't seem to find a datasheet for it, so if somebody already has it, or maybe knows where to find the datasheet for it i'd greatly appreciate it.
Thank you.
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February 12, 2017, 12:54 am
I complile a project successfuly but a sof file is not generated.What could be a problem?
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February 12, 2017, 7:18 am
Hi All,
How can I include another TCL file inside of the existing *.qsf file?
The reason why I want to include another TCL file inside of the existing *.qsf file, is so that I'd like to separate Pins Assignment from the list of RTL and TestBench files, etc.
So, I'd like to keep separate definition files for each purpose (e.g. as listed above) and only include them inside of the *.qsf file.
How can I do so?
Thank you!
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