Hello, I have a DE1-SoC board connected to my computer. But, when I click to Hardware Setup there is no any hardware. How could I solve this? This is my first time to use this.
Thanks,
Thanks,
↧
Quartus II 13.1 Programmer Hardware Setup
↧
Same VHDL block RAM inferring file, different results
Hi,
I have the following VHDL file to infer a true dual port, single clock block RAM. I believe that it is according to Altera's guidelines.
I have Quartus 16.02 Build 222 07/20/2016.
When I use this file in isolation, I get a block RAM (what I want). When I use it in my design, it generates heaps of ALMs instead
and screws up timing as well.
I tried to make it into a two clocks, two enables RAM and connect to the same clock and enable both pins, but same behavior.
I also tried to make the number of locations a power of 2 and same crappy result.
I have other similar files causing identical problems.
Any clues ?
Thank you very much in advance.
I have the following VHDL file to infer a true dual port, single clock block RAM. I believe that it is according to Altera's guidelines.
I have Quartus 16.02 Build 222 07/20/2016.
When I use this file in isolation, I get a block RAM (what I want). When I use it in my design, it generates heaps of ALMs instead
and screws up timing as well.
I tried to make it into a two clocks, two enables RAM and connect to the same clock and enable both pins, but same behavior.
I also tried to make the number of locations a power of 2 and same crappy result.
I have other similar files causing identical problems.
Any clues ?
Thank you very much in advance.
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_160x32_dp is port(
-- Inputs
clk : in std_logic; -- Clock
en : in std_logic; -- Sync enable
we0, we1 : in std_logic; -- Write enables
addr0, addr1 : in std_logic_vector(7 downto 0); -- Addresess
din0, din1 : in std_logic_vector(31 downto 0); -- Data input
dout0, dout1 : out std_logic_vector(31 downto 0) -- Data output
);
end ram_160x32_dp;
architecture beh of ram_160x32_dp is
type mram is array (159 downto 0) of std_logic_vector(31 downto 0);
signal mem : mram; -- Memory array 160x32
begin
--Dual port RAM model
process(clk)
variable n : integer;
begin
if rising_edge(clk) then
-- Memory is written and read synchronoulsy
-- when enabled
if en = '1' then
n:=conv_integer(addr0);
-- Write port 0
if we0 = '1' then
mem(n) <= din0;
dout0 <= din0;
else
-- Read port 0
dout0 <= mem(n);
end if;
end if;
end if;
end process;
process(clk)
variable n : integer;
begin
if rising_edge(clk) then
-- Memory is written and read synchronoulsy
-- when enabled
if en = '1' then
n:=conv_integer(addr1);
-- Write port 1
if we1 = '1' then
mem(n) <= din1;
dout1 <= din1;
else
-- Read port 1
dout1 <= mem(n);
end if;
end if;
end if;
end process;
end beh;↧
↧
Hot-plug VCCIO changing on MAX10 (10M16SC)
Hello everyone,
I wonder if I can change a VCCIOx while running my MAX10, for instance an IO @1.2V will change for 2.5V
I didn't find any accurate information in docs, so in your opinion, is there an overshoot risk, did you ever try this on another FPGA ?
Thank you in advance :)
I wonder if I can change a VCCIOx while running my MAX10, for instance an IO @1.2V will change for 2.5V
I didn't find any accurate information in docs, so in your opinion, is there an overshoot risk, did you ever try this on another FPGA ?
Thank you in advance :)
↧
FFT Megafunction :Fatal Error in VHDL
Hello Everyone,
I am working on my project , and i got this error while simulating my code
Fatal error in Process MEMORY at C:/altera/15.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 40031
Anyone had this or similar?
Any help would be appreciated .
Thanks in advance
Best Regards,
Jesmeeshat
I am working on my project , and i got this error while simulating my code
Fatal error in Process MEMORY at C:/altera/15.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 40031
Anyone had this or similar?
Any help would be appreciated .
Thanks in advance
Best Regards,
Jesmeeshat
↧
Unable to launch Quartus II 16.1
Hello,
I have downloaded and installed Quartus II 16.1 from Altera website on Windows 7 64-bit PC. After installation, i tried to launch the tool by clicking the desktop shortcut icon but there no action. The software doesn't come up and i do not see any quartus related application running in task manager window. I tried rebooting after installation but still i see the same issue. Pls help.
The PC configuration:
Latest I7 Mother board with 16GB RAM
OS: Windows 7 64-bit.
Thanks
RPratam
I have downloaded and installed Quartus II 16.1 from Altera website on Windows 7 64-bit PC. After installation, i tried to launch the tool by clicking the desktop shortcut icon but there no action. The software doesn't come up and i do not see any quartus related application running in task manager window. I tried rebooting after installation but still i see the same issue. Pls help.
The PC configuration:
Latest I7 Mother board with 16GB RAM
OS: Windows 7 64-bit.
Thanks
RPratam
↧
↧
FPGA Master Driven Coherent Memory Transactions Using Write/Read Masters on Linux
Hi,
I'm trying to compare 3 FPGA Master driven memory transaction scenarios on Altera Cyclone V SoC:
- Connecting to SDRAM controller directly,
- Connecting to SDRAM controller using F2H bridge,
- Connecting to SCU through ACP using F2H bridge.
.. and
- I'm running Linux
- I use MSGDMA Write/Read IP's as FPGA Masters.
I allocate contiguous memory using CMA Kernel feature combined with Texas Instrument CMEM API.
Naturally MSGDMA is controlled via Linux driver.
I would appreciate help with the usage of ACP port.
Current progress. Following the documentation (9-29 in Cyclone V Device Handbook):
SCU is enabled (checked manually),
SMP bit in ACTLR is set (checked manually),
I have no access to page map configuration, but I assume allocated coherent memory is marked shareable due to the fact, that I use both ARM cores,
I target ACP in physical memory region (0x80000000 base address),
After reset ID Mapper is in dynamic state,
Write/Read Masters use Avalon interfaces not AXI, so they don't drive AxUSER and AxCACHE signals!!! These signals are generated by memory interconnect.
Here I get dizzy... In documentation it is stated, that ACP ID mapper can control overriding signals for AXI masters that cannot drive the sideband signals themselves.
BUT... it is stated that this is not true for FPGA Masters. So I conclude that I must drive these signals myself.
I went into source code and set these AxUSER and AxCACHE signals manually!! I tried setting AxCACHE[1] and AxUSER[0] to 1. There were noticeable changes in transfer speed (2x-3x), but transactions still weren't coherent.
Then I set AxUSERS signal to "11111" and AxCACHE to "1111". Again there were changes in transaction speeds.
I find this quite a challanging task and finally here is my question:Is it possible to use ACP with an FPGA master through memory-mapped interconnect. And if that's so, what am I missing here?
I'm trying to compare 3 FPGA Master driven memory transaction scenarios on Altera Cyclone V SoC:
- Connecting to SDRAM controller directly,
- Connecting to SDRAM controller using F2H bridge,
- Connecting to SCU through ACP using F2H bridge.
.. and
- I'm running Linux
- I use MSGDMA Write/Read IP's as FPGA Masters.
I allocate contiguous memory using CMA Kernel feature combined with Texas Instrument CMEM API.
Naturally MSGDMA is controlled via Linux driver.
I would appreciate help with the usage of ACP port.
Current progress. Following the documentation (9-29 in Cyclone V Device Handbook):
SCU is enabled (checked manually),
SMP bit in ACTLR is set (checked manually),
I have no access to page map configuration, but I assume allocated coherent memory is marked shareable due to the fact, that I use both ARM cores,
I target ACP in physical memory region (0x80000000 base address),
After reset ID Mapper is in dynamic state,
Write/Read Masters use Avalon interfaces not AXI, so they don't drive AxUSER and AxCACHE signals!!! These signals are generated by memory interconnect.
Here I get dizzy... In documentation it is stated, that ACP ID mapper can control overriding signals for AXI masters that cannot drive the sideband signals themselves.
BUT... it is stated that this is not true for FPGA Masters. So I conclude that I must drive these signals myself.
I went into source code and set these AxUSER and AxCACHE signals manually!! I tried setting AxCACHE[1] and AxUSER[0] to 1. There were noticeable changes in transfer speed (2x-3x), but transactions still weren't coherent.
Then I set AxUSERS signal to "11111" and AxCACHE to "1111". Again there were changes in transaction speeds.
I find this quite a challanging task and finally here is my question:Is it possible to use ACP with an FPGA master through memory-mapped interconnect. And if that's so, what am I missing here?
↧
UART RECEIVE interrupt in nios int status = 0; status = IORD_ALTERA_AVALON_UART_STAT
Hello,
I need to read the uart data on interrupt bases ,means whenever there is something on rx pin of uart interrupt should get generated and in ISR should read it.
I have tried by using bellow code but didn't get any success ...
char data;
volatile int edge_capture;
void uart_isr()
{
int status = 0; status = IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE);
if(status & 0x80)
data = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE);
interrupt_count = interrupt_count +1;
}
void uart()
{
void* edge_capture_ptr = (void*) &edge_capture;
alt_ic_isr_register(UART_0_IRQ_INTERRUPT_CONTROLLE R_ID,
UART_0_IRQ, uartR, edge_capture_ptr, 0x0);
alt_ic_irq_enable(UART_0_IRQ_INTERRUPT_CONTROLLER_ ID,UART_0_IRQ);
IOWR_ALTERA_AVALON_UART_CONTROL(UART_0_BASE,ALTERA _AVALON_UART_CONTROL_RRDY_MSK);
}
sometime ISR just gets called once and sometime it will be keep getting even if there is nothing on uart RX bus..
M i doing something wrong here ..plz suggest me.
If anyone has example code for uart interrupt receive plz share .
Thanks and Regards
Ankur
I need to read the uart data on interrupt bases ,means whenever there is something on rx pin of uart interrupt should get generated and in ISR should read it.
I have tried by using bellow code but didn't get any success ...
char data;
volatile int edge_capture;
void uart_isr()
{
int status = 0; status = IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE);
if(status & 0x80)
data = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE);
interrupt_count = interrupt_count +1;
}
void uart()
{
void* edge_capture_ptr = (void*) &edge_capture;
alt_ic_isr_register(UART_0_IRQ_INTERRUPT_CONTROLLE R_ID,
UART_0_IRQ, uartR, edge_capture_ptr, 0x0);
alt_ic_irq_enable(UART_0_IRQ_INTERRUPT_CONTROLLER_ ID,UART_0_IRQ);
IOWR_ALTERA_AVALON_UART_CONTROL(UART_0_BASE,ALTERA _AVALON_UART_CONTROL_RRDY_MSK);
}
sometime ISR just gets called once and sometime it will be keep getting even if there is nothing on uart RX bus..
M i doing something wrong here ..plz suggest me.
If anyone has example code for uart interrupt receive plz share .
Thanks and Regards
Ankur
↧
multiport Ethernet reference design
I can't find a reference design to show me how to connect a shared fifo to the triple speed Ethernet IP if i set it in multiport mode. Does anyone have a build that uses the multiport configuration with the shared fifo?
Also may I know if I can connect two sgmii signals from 2 FPGAs together( FPGA1_rx to FPGA2_tx and vice versa) without a phy inbetween? Any special requirements for these to work? I presume you could have loopbacked on the SGMII interface before so could work but not sure.
Also may I know if I can connect two sgmii signals from 2 FPGAs together( FPGA1_rx to FPGA2_tx and vice versa) without a phy inbetween? Any special requirements for these to work? I presume you could have loopbacked on the SGMII interface before so could work but not sure.
↧
EQFP144 footprint for Allegro
Hello,
I need an EQFP144 footprint for Allegro. I have downloaded the official Altera library (from here: https://www.altera.com/support/suppo...b-cadence.html) and the package I need is not included.
The FPGA I am programming is a MAX10 (10M02SCE144C8G) and I do not have much experience in drawing footprints. Does anyone know if that footprint is included in any other library or where I could get it? Maybe from an Allegro standard library... I don't know... :huh:
Thank you!!
I need an EQFP144 footprint for Allegro. I have downloaded the official Altera library (from here: https://www.altera.com/support/suppo...b-cadence.html) and the package I need is not included.
The FPGA I am programming is a MAX10 (10M02SCE144C8G) and I do not have much experience in drawing footprints. Does anyone know if that footprint is included in any other library or where I could get it? Maybe from an Allegro standard library... I don't know... :huh:
Thank you!!
↧
↧
mmu initlization
Hello,
Where does u/cos initialize mmu ?
Can't find it in source code.
Thanks,
Ran
Where does u/cos initialize mmu ?
Can't find it in source code.
Thanks,
Ran
↧
SignalTap II issue
Hello,
Here is debounce state machine:
And here is SignalTap simulation
![]()
After 2st firing of the input sw the "state machine" frozes definitely in "00" state.
Moreover, after 1st sw firing, the "state machine" value is displayed in symbolic interpretation in SignalTap II, i.e. zero, wait0, one, wait1.
After 2nd sw firing this symbolic interpretation disappears ... leaving place to numeric interpretation, i.e. 0 (as shown on the above image).
So I have 2 questions:
Thanks in advance
Here is debounce state machine:
Code:
module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration
localparam [1:0]
zero = 2'b00,
wait0 = 2'b10,
one = 2'b11,
wait1 = 2'b01;
// number of counter bits (2'N * 20ns = 40ms)
localparam N = 21;
//localparam N = 15;
// signal declaration
reg [1:0] state_reg, state_next;
reg [N-1:0] q_reg;
wire [N-1:0] q_next;
wire q_zero;
reg q_load, q_dec;
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset)
begin
state_reg <= zero;
q_reg <= 0;
end
else
begin
state_reg <= state_next;
q_reg <= q_next;
end
// FSMD data path (counter) nextstate logic
assign q_next = (q_load) ? {N{1'b1}} : ((q_dec) ? q_reg - 1 : q_reg);
// status signal
assign q_zero = (q_next == 0);
// FSMD control path nextstate logic
always @*
begin
state_next = state_reg; // default state: the same
q_load = 1'b0; // default output: 0
q_dec = 1'b0; // default output: 0
db_tick = 1'b0; // default output: 0
case (state_reg)
zero:
begin
db_level = 1'b0;
if (sw)
begin
state_next = wait1;
q_load = 1'b1;
end
end
wait1:
begin
db_level = 1'b0;
if (sw)
begin
q_dec = 1'b1;
if (q_zero)
begin
state_next = one;
db_tick = 1'b1;
end
end
else // sw==0
state_next = zero;
end
one:
begin
db_level = 1'b1;
if (~sw)
begin
state_next = wait0;
q_load = 1'b1;
end
end
wait0:
begin
db_level = 1'b1;
if (~sw)
begin
q_dec = 1'b1;
if (q_zero) state_next = zero;
end
else // sw==l
state_next = one;
end
default: state_next = zero;
endcase
end
endmoduleAfter 2st firing of the input sw the "state machine" frozes definitely in "00" state.
Moreover, after 1st sw firing, the "state machine" value is displayed in symbolic interpretation in SignalTap II, i.e. zero, wait0, one, wait1.
After 2nd sw firing this symbolic interpretation disappears ... leaving place to numeric interpretation, i.e. 0 (as shown on the above image).
So I have 2 questions:
- why symbolic interpretation disappears
- is it possible to put into SignalTap the signals that present in the source code in order to debug "system machine" misbehavior. Actually only few signals are available for SignalTap.
Thanks in advance
↧
error : Cyclone V XCVR Illegal constraint of Channel PLL
Hi All,
As you can see the attachement "xcvr_pin_planner", I'm using 4 transceivers in the cyclcone V ST FPGA.
I use only one "Transceiver reconfiguration controller" configured for 8 reconfiguration interfaces (grouping option = 2,2,2,2).
With this configuration i have this error (with quartus 14.1 and 15.1) :
If i remove CH1 (see attachement), I no longer have this problem
As you can see the attachement "xcvr_pin_planner", I'm using 4 transceivers in the cyclcone V ST FPGA.
I use only one "Transceiver reconfiguration controller" configured for 8 reconfiguration interfaces (grouping option = 2,2,2,2).
With this configuration i have this error (with quartus 14.1 and 15.1) :
Code:
Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 Channel PLL(s))
Error (175020): Illegal constraint of Channel PLL that is part of Cyclone V Transceiver Native PHY altera_xcvr_native_av to the region (0, 40) to (0, 42): no valid locations in region
Info (175028): The Channel PLL name(s): sFPDP_CONTROLLER:inst_sfpdp_controller4|sFPDP_XCVR:CMP_sFPDP_XCVR|sFPDP_PHY:CMP_sFPDP_PHY|altera_xcvr_native_av:sfpdp_phy_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_cdr
Info (175015): The I/O pad iSFPDP_XCVR_RX3 is constrained to the location PIN_L2 due to: User Location Constraints (PIN_L2)
Info (14709): The constrained I/O pad is contained within a pin, which is contained within a Receiver channel, which contains this Channel PLL
Error (178014): Partition assignments may be preventing transceiver placement - transceivers optimizations across partitions are not supported in this version of the Quartus II software. For more information, refer to the Release Notes.↧
Proble with NCO core at frequency higher than 200MHz
Hi All
I am using Arria V FPGA. I am using NCO ipcore for waveform generation as well as carrier. The problem I am facing is with NCO core. At higher frequency , lets say 240 MHz, if I am generating 30 MHz, which is integral multiple of 240Mhz, spectrum is clean. If I move to 31 MHz,spectum becomes noisy. Any solution.
I am using Arria V FPGA. I am using NCO ipcore for waveform generation as well as carrier. The problem I am facing is with NCO core. At higher frequency , lets say 240 MHz, if I am generating 30 MHz, which is integral multiple of 240Mhz, spectrum is clean. If I move to 31 MHz,spectum becomes noisy. Any solution.
↧
↧
FFT Megafunction :Modelsim
Hello Everyone,
I am working on my project , and i got this error while simulating my code
Fatal error in Process MEMORY at C:/altera/15.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 40031
Anyone had this or similar?
Any help would be appreciated .
Thanks in advance
Best Regards,
Jesmeeshat
I am working on my project , and i got this error while simulating my code
Fatal error in Process MEMORY at C:/altera/15.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 40031
Anyone had this or similar?
Any help would be appreciated .
Thanks in advance
Best Regards,
Jesmeeshat
↧
[Qsys] LPDDR2 Controller (UniPHY): HDL generation fails.
From the TerasIC Cyclone V GX Starter Kit (C5G) System CD v.1.2.2., I use Qsys (16.1 under Windows 10 64-bits) to re-generate the HDL from
Unfortunately, I receive the following error:
I suspect the error to originate from the scripts called to generate the LPDDR2 SDRAM Controller with UniPHY IP component but have too limited knowledge to track down the error.
I also found the solution to a somewhat similar error message but this didn't solve the issue (or I did it wrong).
Finally, I don't believe the error could come from the project as I didn't modify it and it seems to have been generated correctly by TerasIC engineers under 13.1.
Thanks.
[...]\C5G_v.1.2.2_SystemCD\Demonstrations\C5G_LPDDR2_Ni os_Test\C5G_QSYS.qsys.
Unfortunately, I receive the following error:
Code:
Error: s0: Error during execution of "{C:/intelfpga_lite/16.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/intelfpga_lite/16.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: ]2;Altera Nios II EDS 16.1 [gcc4]C:/intelfpga_lite/16.1/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../C5G_QSYS_mem_if_lpddr2_emif_s0_AC_ROM.hex -inst_rom ../C5G_QSYS_mem_if_lpddr2_emif_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR1_CALIB=01100011000000010000 -DAC_ROM_MR1=01100011000000010000 -DAC_ROM_MR2=00000101000000100000 -DAC_ROM_MR3=00000010000000110000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=10 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 2016 Intel Corporation. All rights reserved.
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../C5G_QSYS_mem_if_lpddr2_emif_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../C5G_QSYS_mem_if_lpddr2_emif_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: C:/intelfpga_lite/16.1/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: Error: 0x80070057
Error: s0:
Error: s0:
Error: s0:
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if {[file exists $seq_file] == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf""
invoked from within
"set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequencer" "sequencer.elf"]]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size [alt_mem_if::util::seq_mem_size::get_max_memory_usage [file join "sequenc..."
(procedure "generate_qsys_sequencer_sw" line 924)
invoked from within
"generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name $ac_rom_init_file_name ..."
invoked from within
"set seq_mem_size_list [generate_qsys_sequencer_sw $prepend_str $protocol $pre_compile_dir $fileset $inhdl_dir $rdimm $lrdimm 0 0 $nios_hex_file_name ..."
("if" else script line 2)
invoked from within
"if {[::alt_mem_if::util::qini::qini_value alt_mem_if_seq_size_request 0] > 0} {
set seq_mem_size [::alt_mem_if::util::qini::qini_value alt_mem_if_se..."
(procedure "alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer" line 238)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}"
invoked from within
"set qsys_sequencer_files_list [alt_mem_if::gen::uniphy_gen::generate_qsys_sequencer "${name}" $protocol $tmpdir $fileset {}]"
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file [alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "LPDDR2" $tmpdir QUARTUS_SYNTH] {
set file_name [file tail $gene..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth C5G_QSYS_mem_if_lpddr2_emif_s0"I also found the solution to a somewhat similar error message but this didn't solve the issue (or I did it wrong).
Finally, I don't believe the error could come from the project as I didn't modify it and it seems to have been generated correctly by TerasIC engineers under 13.1.
Thanks.
↧
FPGA re-flashing and running application from parallel flash
Hi,
I am new to altera fpga, i am working on interfacing parallel flash with cyclone V board. After copying the binary/application from PC to parallel flash i need to run this application on fpga, what will be the best solution? how i can copy the binary/application to fpga and run it. please suggest the Command/APIs or any sequence etc.
Thanks,
I am new to altera fpga, i am working on interfacing parallel flash with cyclone V board. After copying the binary/application from PC to parallel flash i need to run this application on fpga, what will be the best solution? how i can copy the binary/application to fpga and run it. please suggest the Command/APIs or any sequence etc.
Thanks,
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Where to find List of FPGA OpenCL libraries available/implemented
Hi everyone,
I am totally new to OpenCL and Altera, and apologize if this is a very basic question.
I plan to buy an Altera FPGA and want to take on a project with OpenCL as a learning side project (with school). I'm curious as to if there is a list of libraries available that tells me which all libraries have been implemented and are available for me to use on my FPGA board (most likely the Zynq or Snickerdoodle).
I've googled libraries available, and see that there is a website with a list that is maintained, but as I am new to all of this, I can't seem to understand if all of these libraries can be used with Altera FPGA, or if some are just CPU/GPU/DSP related and not related to FPGA. (Please excuse me if this is also a very simple dumb question).
Link of the List:
http://www.iwocl.org/resources/openc...-and-toolkits/
I'm interested in projects related to incorporating Linux and FPGA.
Type of project trying to understand
http://elinux.org/images/5/54/ELC200...and_profit.pdf
Hoping people can guide me to a list of libraries I can use, and maybe some advice on OpenCL and FPGA with Arm Cortex. I highly appreciate all of your time!
I am totally new to OpenCL and Altera, and apologize if this is a very basic question.
I plan to buy an Altera FPGA and want to take on a project with OpenCL as a learning side project (with school). I'm curious as to if there is a list of libraries available that tells me which all libraries have been implemented and are available for me to use on my FPGA board (most likely the Zynq or Snickerdoodle).
I've googled libraries available, and see that there is a website with a list that is maintained, but as I am new to all of this, I can't seem to understand if all of these libraries can be used with Altera FPGA, or if some are just CPU/GPU/DSP related and not related to FPGA. (Please excuse me if this is also a very simple dumb question).
Link of the List:
http://www.iwocl.org/resources/openc...-and-toolkits/
I'm interested in projects related to incorporating Linux and FPGA.
Type of project trying to understand
http://elinux.org/images/5/54/ELC200...and_profit.pdf
Hoping people can guide me to a list of libraries I can use, and maybe some advice on OpenCL and FPGA with Arm Cortex. I highly appreciate all of your time!
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Multi-channel FIFO will not generate with Qsys (bug in Quartus Prime 16.1.2?)
I found that the Avalon Streaming Multi-Channel FIFO fails to generate for both my project and a brand new blank one. I get the same exact error message. Perhaps a bug in Qsys/Quartus 16.1.2? Or I could just be doing something wrong.
The following error is recieved when generating from Qsys using Quartus Prime 16.1.2:
Doing some searching, this problem of wrong # args seems to come up when there is a space in a name. My directory though is C:\Users\Joseph\Documents\local_repos\he_mt6d.
I've attached a copy of the error (both my project and the blank project), a snapshot of the bare-bones Qsys instantiation, and the verilog code and tcl from C:\intelFPGA\16.1\ip\altera\sopc_builder_ip\altera _avalon_multi_channel_shared_fifo.
Does anyone have any success with this module or know how to diagnose wrong # args: should be "generate output_name" problem from a system component from the IP catalog?
The following error is recieved when generating from Qsys using Quartus Prime 16.1.2:
Code:
Error: mc_fifo: wrong # args: should be "generate output_name" while executing "generate synth altera_avalon_multi_channel_shared_fifo"
Where "mc_fifo" is the qsys module name Avalon Multi-Channel Shared FIFOI've attached a copy of the error (both my project and the blank project), a snapshot of the bare-bones Qsys instantiation, and the verilog code and tcl from C:\intelFPGA\16.1\ip\altera\sopc_builder_ip\altera _avalon_multi_channel_shared_fifo.
Does anyone have any success with this module or know how to diagnose wrong # args: should be "generate output_name" problem from a system component from the IP catalog?
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Internal error sub-system SGN, version 13.1.4
I have a cyclone III project and just tried compiling it in the last Quartus II that supports it and got:
Internal Error: Sub-system: SGN, File: /quartus/synth/sgn/sgn_proc_info.h, Line: 90
lhs.size() == rhs.size()
Stack Trace:
0x4fd99: sgn_qic_helper + 0x3ed39
0x61293: sgn_qic_helper + 0x50233
0x61b91: sgn_qic_helper + 0x50b31
0x62f7b: sgn_qic_helper + 0x51f1b
0xb5f4c: sgn_clear_check_ip_functor + 0x192dc
0xb286a: sgn_clear_check_ip_functor + 0x15bfa
0xb5f4c: sgn_clear_check_ip_functor + 0x192dc
0xba0dd: sgn_clear_check_ip_functor + 0x1d46d
0x10de2: sgn_qic_full + 0x152
0x128ed: qexe_get_command_line + 0x206d
0x1573e: qexe_process_cmdline_arguments + 0x59e
0x15851: qexe_standard_main + 0xa1
0xa7f8: msg_exe_fini + 0x58
0xaf3c: msg_exe_fini + 0x79c
0x1f04: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194
0xb8bf: msg_exe_main + 0x8f
0x8363: BaseThreadInitThunk + 0x13
0x670d0: RtlUserThreadStart + 0x20
End-trace
Quartus II 64-Bit Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
Are there any fixes or workarounds? This worked on version 10.0 and I tried deleting the "db" and other folders that were created.
Internal Error: Sub-system: SGN, File: /quartus/synth/sgn/sgn_proc_info.h, Line: 90
lhs.size() == rhs.size()
Stack Trace:
0x4fd99: sgn_qic_helper + 0x3ed39
0x61293: sgn_qic_helper + 0x50233
0x61b91: sgn_qic_helper + 0x50b31
0x62f7b: sgn_qic_helper + 0x51f1b
0xb5f4c: sgn_clear_check_ip_functor + 0x192dc
0xb286a: sgn_clear_check_ip_functor + 0x15bfa
0xb5f4c: sgn_clear_check_ip_functor + 0x192dc
0xba0dd: sgn_clear_check_ip_functor + 0x1d46d
0x10de2: sgn_qic_full + 0x152
0x128ed: qexe_get_command_line + 0x206d
0x1573e: qexe_process_cmdline_arguments + 0x59e
0x15851: qexe_standard_main + 0xa1
0xa7f8: msg_exe_fini + 0x58
0xaf3c: msg_exe_fini + 0x79c
0x1f04: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194
0xb8bf: msg_exe_main + 0x8f
0x8363: BaseThreadInitThunk + 0x13
0x670d0: RtlUserThreadStart + 0x20
End-trace
Quartus II 64-Bit Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
Are there any fixes or workarounds? This worked on version 10.0 and I tried deleting the "db" and other folders that were created.
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RAPIDIO for ARRIA10
Hi dear ! Can you show me example of qsys system that uses rapidio core for FPGA Arria10. Thanks so much !
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