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Issues with access to array of accesses

April 5, 2017, 10:21 am
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Hello everyone,


I am encountering issues with exotic VHDL constructs, and I would love your help...






I am trying to write procedures that will be useful to me when building testbenches.
These procedures are intended to read and write text files.


I declared 2 types:
Code:
type t_line_vector      is array (natural range <>) of line;
type t_line_vector_ptr  is access t_line_vector;
(And as a reminder, from textio,
Code:
type line is access string;
)


The t_line_vector_ptr is a data structure similar to the char ** argv from C.


Then, I wrote 2 procedures:
Code:
procedure read_file(filename : in string; line_vector_ptr : out t_line_vector_ptr);
procedure write_file(line_vector_ptr : inout t_line_vector_ptr; filename : in string);
These are intended respectively to load the content of a file into a t_line_vector_ptr, and to write the content of a t_line_vector_ptr into a file.


Then wrote a testbench that reads the content of a file and writes it to another file.


The code is attached to this post. It is pretty simple, and it compiles without warning.


Then when I simulate it, I get nasty access errors:






- with Modelsim Intel Starter Edition 10.5b:


Quote:
$ vlib work


$ vcom -work work test.vhd
Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
Start time: 18:52:31 on Apr 05,2017
vcom -work work test.vhd
-- Loading package STANDARD
-- Loading package TEXTIO
-- Compiling entity test
-- Compiling architecture rtl of test
End time: 18:52:31 on Apr 05,2017, Elapsed time: 0:00:00
Errors: 0, Warnings: 0


$ vsim work.test -batch -do "run -all"
# vsim work.test -batch -do "run -all"
# Start time: 18:52:37 on Apr 05,2017
# Loading std.standard
# Loading std.textio(body)
# Loading work.test(rtl)
#
# run -all
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
# ** Fatal: (vsim-5) ****** Memory failure. *****
# Bad pointer/access type passed to memory subsystem.
# Pointer may have been previously deallocated.
VSIM 2> # End time: 18:52:39 on Apr 05,2017, Elapsed time: 0:00:02
# Errors: 11, Warnings: 0




- I decided to try also with Vivado 2016.4, just to see, and I get:


Quote:
$ xvhdl test.vhd
INFO: [VRFC 10-163] Analyzing VHDL file "test.vhd" into library work
INFO: [VRFC 10-307] analyzing entity test


$ xelab -debug typical test -s test
Vivado Simulator 2016.4
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2016.4/bin/unwrapped/lnx64.o/xelab -debug typical test -s test
Multi-threading is on. Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling architecture rtl of entity work.test
Built simulation snapshot test


****** Webtalk v2016.4 (64-bit)
**** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.


source xsim.dir/test/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'xsim.dir/test/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Wed Apr 5 18:54:06 2017. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2016.4/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Wed Apr 5 18:54:06 2017...


$ xsim test -R


****** xsim v2016.4 (64-bit)
**** SW Build 1756540 on Mon Jan 23 19:11:19 MST 2017
**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.


source xsim.dir/test/xsim_script.tcl
# xsim {test} -autoloadwcfg -runall
Vivado Simulator 2016.4
Time resolution is 1 ps
run -all
ERROR: Attempting to dereference a dangling (deallocated) access value
Time: 0 ps Iteration: 0 Process: /test/line__78
File: test.vhd


HDL Line: test.vhd:85
exit
INFO: [Common 17-206] Exiting xsim at Wed Apr 5 18:54:27 2017...
Is there something wrong with my code?
Or is it that both tools do not support access to array of accesses correctly?


- Julien
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OpenCL with DE0-nano-SoC

April 5, 2017, 12:06 pm
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I am trying to get OpenCL going on the DE0-nano-SoC, I've found a linux image that supports OpenCL finally and I am able to run the OpenCL demos shipped with that image, however when I try to run one of my own OpenCL programs I get the following error, so far my best guess is version mismatch in the libraries.

Code:
symbol lookup error: /home/root/opencl_arm32_rte/host/arm32/lib/libalteracl.so: undefined symbol: acl_hal_get_system_definition
If I grab the libraries from the shipped image and try to re-compile my host code aginst those I get a similar error:

Code:
libalteracl.so: undefined reference to `acl_hal_get_system_definition'
Any Ideas how I can get around this or what's going on?

Similarly, I've been trying to get a custom image running using yocto, however so far I haven't been successful. I can boot and run the `init_opencl` script which successfully inserts the `aclsoc_drv`. however when I try and run my program I get an error that hangs the system requiring a restatr:

Code:
root@cyclone5:~# ./run_program
[  97.092354] Unhandled fault: imprecise external abort (0x406) at 0xbef4be34
[  97.099286] pgd = eeeec000
[  97.101980] [bef4be34] *pgd=2e7f1831, *pte=2df6c75f, *ppte=2df6cc7f
[  97.108256] Internal error: : 406 [#1] SMP ARM
[  97.112679] Modules linked in: aclsoc_drv(O)
[  97.116957] CPU: 1 PID: 808 Comm: run_program Tainted: G          O    4.3.0-altera #1
[  97.125181] Hardware name: Altera SOCFPGA
[  97.129174] task: eef18000 ti: ee7e4000 task.ti: ee7e4000
[  97.134556] PC is at aclsoc_rw+0x1f8/0x42c [aclsoc_drv]
[  97.139760] LR is at aclsoc_rw+0x1c8/0x42c [aclsoc_drv]
[  97.144964] pc : [<bf000ec4>]    lr : [<bf000e94>]    psr: 200e0013
[  97.144964] sp : ee7e5e48  ip : 00004bda  fp : ee7e5ec4
[  97.156386] r10: 00000001  r9 : 00000002  r8 : eec34000
[  97.161587] r7 : 00000008  r6 : 00000000  r5 : f020c870  r4 : f020c870
[  97.168083] r3 : 00000000  r2 : c07ca100  r1 : 00000000  r0 : ffffb0bb
[  97.174581] Flags: nzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment none
[  97.181682] Control: 10c5387d  Table: 2eeec04a  DAC: 00000051
[  97.187401] Process run_program (pid: 808, stack limit = 0xee7e4218)
[  97.193984] Stack: (0xee7e5e48 to 0xee7e6000)
[  97.198325] 5e40:                  ee7e5e7c 00000001 00000000 00000000 ee7e4000 eed8d634
[  97.206469] 5e60: 00000000 eec34000 00000000 00000008 00000008 bef4c468 eee77910 00000000
[  97.214611] 5e80: 00000002 00000000 0000c870 bef4c468 00000008 00000000 ee50e9c0 ee50e9c0
[  97.222754] 5ea0: bf0010f8 ee7e5f80 00000018 c000fe04 ee7e4000 00000000 ee7e5edc ee7e5ec8
[  97.230896] 5ec0: bf00111c bf000cd8 00000001 ee9eb5d8 ee7e5f4c ee7e5ee0 c0128bd4 bf001104
[  97.239038] 5ee0: 00000000 00000000 00000000 ee7e5ef0 eee52300 eed74d40 00000000 c0146730
[  97.247182] 5f00: 00000001 c01377f8 c07cad34 ee460000 ee50e9c0 c012942c 00000020 eeeac478
[  97.255323] 5f20: ee50e9c8 c0146a2c bef4c410 ee50e9c0 ee7e5f80 00000018 c000fe04 ee7e4000
[  97.263465] 5f40: ee7e5f7c ee7e5f50 c0129448 c0128ba4 c0139a14 c01469bc ee50e9c0 ee50e9c0
[  97.271607] 5f60: bef4c410 00000018 c000fe04 ee7e4000 ee7e5fa4 ee7e5f80 c0129d5c c01293cc
[  97.279748] 5f80: 00000000 00000000 b5916124 00020658 b619e000 00000003 00000000 ee7e5fa8
[  97.287891] 5fa0: c000fc40 c0129d14 b5916124 00020658 00000003 bef4c410 00000018 bef4c410
[  97.296035] 5fc0: b5916124 00020658 b619e000 00000003 0001ff48 b6eeacd0 0001ff88 b619e408
[  97.304176] 5fe0: 00000000 bef4c3fc b5902865 b56633a0 600e0010 00000003 00000000 00000000
[  97.312330] [<bf000ec4>] (aclsoc_rw [aclsoc_drv]) from [<bf00111c>] (aclsoc_read+0x24/0x2c [aclsoc_drv])
[  97.321778] [<bf00111c>] (aclsoc_read [aclsoc_drv]) from [<c0128bd4>] (__vfs_read+0x3c/0xe4)
[  97.330183] [<c0128bd4>] (__vfs_read) from [<c0129448>] (vfs_read+0x88/0x114)
[  97.337290] [<c0129448>] (vfs_read) from [<c0129d5c>] (SyS_read+0x54/0xb0)
[  97.344145] [<c0129d5c>] (SyS_read) from [<c000fc40>] (ret_fast_syscall+0x0/0x3c)
[  97.351598] Code: e3a06000 ea000007 e5943000 f57ff04f (e5883000)
[  97.357664] ---[ end trace 469ffa07e79f531b ]---
[  97.362823] aclsoc_close (191):
[  97.365887] aclsoc = eed8d600, pid = 808, dma_idle = 1[  97.371011]
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test

April 5, 2017, 12:58 pm
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testing the subscription email process.
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Marking reference for DE2-115

April 5, 2017, 1:25 pm
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A capacitor (I'm guessing) broke off of a DE2-115 board. It is labeled C180. It's located on the bottom of the right side of the board underneath the GPIO. Does anyone know what system the capacitor is used in or if Altera puts out references for this sort of thing?
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Quartus IP catalog On Chip Mem does not provide waitrequest

April 5, 2017, 1:28 pm
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Am I missing something? The IP Catalog for generating verilog does not provide a waitrequest signal??

In real life, on-chip mem will assert backpressure with a waitrequest. However, the IP at IP Catalog>On Chip Memory> 2-Port RAM does not allow configuration for one or generate the signals and logic. Am I missing something? I assume I'll have to build it in....I realize this small thing was what was throwing off my synthesized application.
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Please support DK-DEV-3C120N new version? All sample code about RAM is fail

April 5, 2017, 5:11 pm
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I got a new version DK-DEV-3C120N, but I found SDRAM and SRAM have been replaced with new component.
And I can’t get some more detail information about that, andall sample code about RAM can’t be run.

Can you give me some advice and help me?

The following is text above these chips:

DDRRAM X 4: 3IH22 D9LHT 6RDR
DDRRAM X 1: 3RG22 D9LQG DTFD
SRAM: 3SB47 PW755 GC9B
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MAX10/DE10-Lite clock skew issue

April 5, 2017, 5:39 pm
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As a simple demo, I wrote verilog code for an updown counter on the DE10-Lite board using buttons, LEDs and switches. KEY[1] is used as clock and KEY[0] is used as synchronous reset.

The counter has a bug when programmed into the DE10. When the three LSB are '111' the next count (up) will always be '001' instead of '000'. We've tried various changes to the updown counter code and the problem remains. It appears to be some kind of clock skew problem. It's not a debounce problem because it only happens when the LSB are '111'. Otherwise, it always counts correctly. It works correctly counting down. Is there a good way to fix this so a button can reliably be used as a clock for simple finite state machines? The problem can be fixed using the 50 MHz clock and generating an enable signal based on a rising edge of KEY[1], but I'm looking for directly clocking a FSM. Thanks.

Here is the verilog:
//================================================== =====
// This code is generated by Terasic System Builder
//================================================== =====


module updown(


//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,


//////////// KEY //////////
input [1:0] KEY,


//////////// LED //////////
output [9:0] LEDR,


//////////// SW //////////
input [0:0] SW
);


//================================================== =====
// REG/WIRE declarations
//================================================== =====
wire Clock, Reset_n, Updown;
reg [15:0] Count;
reg [15:0] next_Count;


//================================================== =====
// Structural coding
//================================================== =====
assign Clock = KEY[1];
assign Reset_n = KEY[0];
assign Updown = SW[0];
assign LEDR = Count[9:0];
assign HEX0 = 8'b11111111;
assign HEX1 = 8'b11111111;
assign HEX2 = 8'b11111111;
assign HEX3 = 8'b11111111;
assign HEX4 = 8'b11111111;
assign HEX5 = 8'b11111111;


always @(Updown, Reset_n, Count) begin
if (Reset_n == 0)
next_Count <= 0;
else if (Updown)
next_Count <= Count + 1; // if Updown, increment Count
else
next_Count <= Count - 1; // else decrement Count
end


always @(posedge Clock) // flip-flops
Count <= next_Count; // count on rising clock edge



endmodule
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FTP does not work

April 5, 2017, 9:30 pm
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Logic use of "Altera Remote Update IP Core"

April 5, 2017, 10:47 pm
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Hi

I have a design running on a Cyclone IV with a self-made FW update block. I now would like to switch to the "Altera Remote Update IP Core", since this core has the possibility to survive a power down during FW update. My problem is my FPGA is quite full (80% of logic).
Is there anywhere an example with the "Altera Remote Update IP Core" for a Cyclone IV? The example I found was with a Cyclone V and the integrated Remote Update was some kind of Altera-self-made-block instead of the normal QSYS block...

Or can somebody tell me how much logic this Remote Update will need? Then I can calculate if it makes sense to implement it.

Best regards
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How do I use the Max II internal oscillator in a schematic?

April 6, 2017, 12:39 am
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I've read the guide on using the internal oscillator, and looked at the bundled Verilog (though I don't know much about that I can just about follow what's going on). It seems to wire OSCENA to an input pin to start the thing producing a signal. I've been trying to do the equivalent in the schematic builder, but to no avail. I've attached the schematic, I know even if this worked the LED would be flashing too fast to see, but so far via simulation I've been unable to see anything but LOW on the LED output pin.

Is it possible to use the oscillator via the schematic builder? If so, can someone give me some pointers on where I'm going wrong? Very new to this stuff!
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[RAPIDIO_II] BIG PROBLEM with Rapidio II Modelsim Simulation TB

April 6, 2017, 1:10 am
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Hello,
I am trying to simulate the RapidioII core generated using the Megawizard in the Quartus 13.0.1 SJ edition by following all the steps in the User Guide. I noticed that there is no simple black box of this core that I can use directly in my testbench so I am trying to use the provided sv testbench. I have not succeeded even though I followed these steps :
1. Go into the modelsim directory where the msim_setup.tcl is, launch the msim_setup (my modelsim : Modelsim Altera Starter Edition 10.1d)
2. Set the TOP_LEVEL_NAME rapidio2.tb_rio (the IP has been created with the name rapidio2
3. ld
4. Add waves..
5. run -all.

Doing this, i can see that the reset goes high after a certain time but the rapidio2 cores, sister and the main one, are stuck at port_initialized ='0', which blocks the simulation. How do i remedy this?

Thank you.
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port a file to ecos

April 6, 2017, 3:00 am
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hi guys,

I'am working with real time operating system Ecos .I need to port a file to this Rtos and run Ecos.

so how can i add this file (from ubuntu ) to Rtos Ecos. ?


Waiting for your guidance.
thank you .

-1down votefavorite
 I am working with real time operating system Ecos
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Highspeed Datalogger (DE1-SoC + THDB ADA)

April 6, 2017, 3:59 am
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Hello everybody,

We work in a course,at our university, with the DE1-SoC Board and the Highspeed THDB-ADA
ADC Board.

The goal is to realise a high speed data sampling unit. Therefore I
worked through a lot of tutorials, because I'm a really newbie in the
FPGA world. I have also done a few research on my own, and found out that a Qsys modell for the external ADC isn't available so far.

Now my question is how can I store the measured data into a variable or into a register for further processing.
I also found out that the registers of the GPIOs of the board are (0xFF200060 - 0xFF20006F and 0xFF200070 - 0xFF20007F), but I don't know to assign the value of the AD to a register.

How could this be solved?

Thank you for your help.

Christoph
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Device Tree - Registering IRQ in Linux GIC

April 6, 2017, 6:32 am
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Hello everyone.

I've done some design using Qsys and I'm trying to get my Device Tree to work. I took the *.dtb from GHRD and changed to a *.dts (so I would be able to modify it as I wish).

Also, I generated the device tree through sopc2dts (I guess this is the command) and the *.dtb file it generates doesn't boot my board, so something is getting messed up. What I did in order to solve the problem is the following: I took the IPs that are are inside the
Code:
hps_0_bridges: bridge@c0000000
and I put the IPs that I use in my qsys design.

Code:
 
        msgdma@0x100000000 { 
              compatible = "altr,msgdma-15.0", "altr,msgdma-1.0";
                reg = <0x00000001 0x00000000 0x00000020>,
                        <0x00000001 0x00000020 0x00000010>;
                reg-names = "CSR", "Descriptor_Slave";
                interrupt-parent = <&hps_0_arm_gic_0>;
                interrupts = <0 43 4>;
                clocks = <&clk_0>;
            };


        hps_0_arm_gic_0: intc@fffed000 {
                compatible = "arm,cortex-a9-gic-15.0", "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0xfffed000 0x1000 0xfffec100 0x100>;
                reg-names = "axi_slave0", "axi_slave1";
                linux,phandle = <0x2>;
                phandle = <0x2>;
        };
The thing is I can't register the interrupt 43 onto GIC... (I only checked the proc/interrupts file)



Anyone knows what might be causing the problem? Currently I can use all my peripherals from lw and my fpga2sdram bus. This mSGDMA writes to the ARM SDRAM, and the design works well, but I can't get this IRQ thing to work.

Thanks in advance!
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Is it possible to use H2F and LWH2F at the same time in user application under Linux?

April 6, 2017, 6:58 am
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Hi, everybody!
I wonder if it's possible to use both H2F and LWH2F interfaces in an application? In my code I mmap H2F and work with it and then munmap it. After that I mmap LWH2F work with it and munmap it. The program hangs up after the start. Also I tried to open file /dev/mem then mmap H2F, munmap and close (fd). Next I open file /dev/mem again and mmap and munmap LWH2F and close (fd), but result was the same - program hung up. So, is it correct in principle to do what I want to do? I think it would make sense to use lw h2f just for control and status regs and h2f for data transactions (DMA)...
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automatic optimization by resource driven optimization,FPGA SDK

April 6, 2017, 2:39 pm
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Hi,

Correct me if i am wrong:
In Intel FPGA SDK ,for kernel program when attributes like num_compute_units() and num_simd_work_items() are not mentioned explicitly , "Resource driven optimization" is automatically enabled.

Where can i see the information about number of compute units and num of SIMD work items to which the compiler has optimized.
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quartus prime software quit unexpectedly

April 6, 2017, 4:30 pm
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I have problem with synthesis. I can't find any information about this error code.
Here is the report:
Problem Details
Error:

*** Fatal Error: Access Violation at 0X00007FFAFF18ED5E
Module: quartus_map.exe
Stack Trace:
0x1ed5d: HDBX_READER::generate_dependencies + 0x39d (db_hdbx)
0x1e3f0: HDBX_READER::generate_assignments + 0xbb0 (db_hdbx)
0x1f507: HDBX_READER::generate_hdb + 0x107 (db_hdbx)
0x22775: HDBX_READER::read_common + 0x155 (db_hdbx)
0x5068: hdbx_drl_hdbx_read + 0x88 (db_hdbx)
0x22dc4: QSYN_FRAMEWORK::write_qic_databases + 0x514 (quartus_map)
0x21f24: QSYN_FRAMEWORK::write_databases + 0x114 (quartus_map)
0x11378: qexe_do_normal + 0x2a8 (comp_qexe)
0x16142: qexe_run + 0x432 (comp_qexe)
0x16e51: qexe_standard_main + 0xc1 (comp_qexe)
0x1b06b: qsyn_main + 0x51b (quartus_map)
0x13328: msg_main_thread + 0x18 (CCL_MSG)
0x14b0e: msg_thread_wrapper + 0x6e (CCL_MSG)
0x15b00: mem_thread_wrapper + 0x70 (ccl_mem)
0x12a11: msg_exe_main + 0xa1 (CCL_MSG)
0x29862: __tmainCRTStartup + 0x10e (quartus_map)
0x8363: BaseThreadInitThunk + 0x13 (KERNEL32)
0x670d0: RtlUserThreadStart + 0x20 (ntdll)


End-trace


Executable: quartus_map
Comment:
None

System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0

Quartus Prime Information
Address bits: 64
Version: 16.1.0
Build: 196
Edition: Standard Edition
-----------------------------------------------------------------
I have found the code which causes this issue. But I don't know why the code causes the problem. Also, I don't know how to solve it. Here is the code:
initial
begin
$readmemb("../data/file1.txt", rom1);
$readmemb("../data/file2.txt", rom2);
end
It seems tha quartus doesn't allow me to initialize two ROMs in one verilog file. After I remove either one of the two $readmemb statement, quartus can synthesis successfully.
I have also tried used two seperate initial blocks, each block contains one $readmemb. This doesn't solve the problem.
I use the template provided by quartus to implement the two roms. Rom is inferred correctly.
How do I solve this problem? I need to initialize multiple roms and rams in my project.
Thank you!
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Modelsim Instantiation Error

April 6, 2017, 6:19 pm
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I am receiving this error

Instantiation of 'DFFE' failed. The design unit was not found.

Some sources are telling me to manually add the primitives library in modelsim. Others are saying that if I am using nativelink, then I should have no problems. Well I try to manually add the library in modelsim. Simulate -> Start Simulation -> Libraries -> Add -> <Quartus installation> -> EDA -> Sim Library. However after adding it the OK button is grayed out.

I am running modelsim from quartus. So I presume that is through nativelink no?

Anyone know how to fix this?

* Error: (vsim-3033) C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/Register_2_Bit_LoadVcc.v(16): Instantiation of 'DFFE' failed. The design unit was not found.
#
# Region: /Control_TB/DUT/DUT_SC/Control_State
# Searched libraries:
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/sgate
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_lnsim
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/cycloneiii
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
# ** Error: (vsim-3033) C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/Register_2_Bit_LoadVcc.v(22): Instantiation of 'DFFE' failed. The design unit was not found.
#
# Region: /Control_TB/DUT/DUT_SC/Control_State
# Searched libraries:
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/sgate
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_lnsim
# C:/altera/13.0sp1/modelsim_ase/altera/verilog/cycloneiii
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
# C:/Users/TMPHBITEU/OneDrive/Spring 17/Labs/Comp Arch/simulation/modelsim/rtl_work
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automatic optimization by resource driven optimization,FPGA SDK

April 6, 2017, 7:09 pm
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Hi,

Correct me if i am wrong:
In Intel FPGA SDK ,for kernel program when attributes like num_compute_units() and num_simd_work_items() are not mentioned explicitly , "Resource driven optimization" is automatically enabled.

Where can i see the information about number of compute units and num of SIMD work items to which the compiler has optimized.
↧

Cyclone 10

April 7, 2017, 12:52 am
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0
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I'm trying to find out pricing and availability of Cyclone 10 FPGAs, particularly the LP device 10CL055?
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