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LVDS connector/cable

April 7, 2017, 1:00 am
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Good morning.
I am starting to design a board that mounts an Altera FPGA. This board needs to communicate with another that mounts the same FPGA. The communication takes place via 10 LVDS lines, each about 600 MB/s. Now I'm looking for a connector and interconnect cable, I've seen that there are many manufacturers and many solutions, but I wanted to ask if anyone had direct experience and maybe he could recommend a connector/cable pair for ia application.
The boards are parallel to a distance of a few centimeters, I also thought a flat cable FPC / FFC, could be a solution?


Thanks in advance,
Federico.
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Implementing OpenCL in an existing SoC project

April 7, 2017, 1:15 am
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Hi

I have an existing Cyclone V project, with the HPS and custom IP-cores instantiated in QSys (board.qsys).
Additionally I have custom modules in VHDL, so I have something like:

-top.vhd
-- module 1
-----module 1.1
-----module 1.2
-- module 2
-- board.qsys

I have modified the board.qsys file using the c5soc reference platform.
As I understand I have to include this in the system.qsys, which in turn is included in the top.v file of the OpenCL project:

-top.v
--system.qsys
----board.qsys

Additionally I have to compile the board.qsys project to ensure timing and export the result to a .qpf file.
But I'm not sure where the custom VHDL modules goes:
Do they have to be part of the exported .qpf file, do I have to wrap them in an IP-core and include it in the board.qsys file or so I have to remap it in my new top.v file where system.qsys is included?

Thank you for your time, it is much appreciated!
Nikolai
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Compiler error: Could not initialize class sun.awt.X11.XToolkit

April 7, 2017, 1:37 am
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Dear all,

I'm trying to compile kernels, but sometimes the compiler gives an "Error: Qsys-script FAILED" error.

In <kernelname/kernelname.log>: there are several error messages:

Error: add_instance clk_1x altera_clock_bridge : Can't connect to X11 window server using 'localhost:11.0' as the value of the DISPLAY variable.
add_instance clk_2x altera_clock_bridge : Could not initialize class sun.awt.X11.XToolkit
... (more errors complaining about sun.awt.X11.XToolkit)
Error: save_system kernel_system.qsys: Could not initialize class sun.awt.X11.XToolkit

The compiler parameters were: aoc --fp-relaxed --fpc --report --profile <kernel.cl>

It is expected that it cannot open a window (it is running in a "screen"), but I do not want it to. How do I prevent this error? Currently my guess is to unset the display variable. As I do not know what triggers this error, and compiling takes pretty long, I do not currently know if this works.

Ideas welcome! Thanks in advance!
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integer overflow

April 7, 2017, 6:43 am
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Can anyone explain me why ModelSim Intel Starter Edition 10.5b does not complain about integer overflows, i.e. why the following code

Code:
process
    variable n : integer;
begin
    n := 0;
    report integer'image(n);
    for i in 1 to 1000 loop
        n := ((10 * n) + 3);
        report integer'image(n);
    end loop;
    wait;
end process;
generates that:


Quote:
0
3
33
333
3333
33333
333333
3333333
33333333
333333333
-961633963
-1026405035
-1674115755
438711637
92149077
921490773
624973141
1954764117
-1927195307
-2092083883
553997653
1245009237
-434809515
-53127851
-531278507
-1017817771
-1588243115
1297438037
89478485
894784853
357913941
-715827883
1431655765
1431655765
1431655765
...

Thanks,

- Julien
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Using `define constant for decoding address busses

April 7, 2017, 6:54 am
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Hi,
I am trying to make a list of addresses in my project to be use throughout all of my Verilog modules.
I have created a "addr.vh" file to put the addresses in as follows:

addr.vh

`ifndef _addr_vh_
`define _addr_vh_

`define M 'h01808;

`endif

In a module I trying to store some data when the chip select, write signal and address are true in the
follow code:

always @ (posedge fpga_clk)
begin
if (reset_low_sync == false)
begin
motor_dis_reg <= 'h0000;
end
else if ((!fpga_cs_low & !rw_low) & (addr == `M))
begin
motor_dis_reg <= data_in;
end
end

I keep getting a syntax error #10170 where I am doing the address comparison with the `M statement.
The logic works fine if put the true constant value " 'h01804" instead of the `define M. I though the `define
was a one for one substitution? Is this use of `define macro not legal??

Thank you for any reading and any help you may provide!
Larry
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Connecting HPS GPIOs to top level pins

April 7, 2017, 12:22 pm
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The Qsys defines all HPS GPIOs as bi-directional signals. I have to define the top level IO pins as bi-directional too. Otherwise, it won't allow me to connect them together. However, I got warning messages when compiling the code:
Warning (13009): TRI or OPNDRN buffers permanently enabled

and there are a bunch of warnings of 13010 indicating which HPS IO pin has problem.

Firs question: how to get rid of the warning messages?

I also got another problem here: the software cannot read the GPIO input signals at gpio_swporta_dr .
it can only read the inputs at gpio_ext_porta.

Is this because of the warning message? or reading gpio_ext_porta is the only option for input signals?

thanks for inputs!

Qs Xiang
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How to create filesystem for linux4 with nios2

April 7, 2017, 1:43 pm
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I get kernel panic likely because I don't have a filesystem. I don't know how I should enable it. I see in menuconfig there are option for the RAM filesystem and I tried setting that both to explicit files and the directory of the buildroot images. Nothing worked. Can you help me?

Code:
Linux version 4.9.0-00104-g84d4f8a-dirty (developer@1604) (gcc version 6.2.0 (Sourcery CodeBench Lite 2016.11-32) ) #48 Fri Apr 7 22:39:28 CEST 2017
bootconsole [early0] enabled
early_console initialized at 0xe8001440
On node 0 totalpages: 32768
free_area_init_node: node 0, pgdat c084e52c, node_mem_map c0883b80
  Normal zone: 256 pages used for memmap
  Normal zone: 0 pages reserved
  Normal zone: 32768 pages, LIFO batch:7
��pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
Kernel command line: debug console=ttyAL0,115200
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Sorting __ex_table...
Memory: 121196K/131072K available (2233K kernel code, 66K rwdata, 352K rodata, 5852K init, 197K bss, 9876K reserved, 0K cma-reserved)
SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS:64 nr_irqs:64 0
clocksource: nios2-clksrc: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 38225208935 ns
Console: colour dummy device 80x25
Calibrating delay loop (skipped), value calculated using timer frequency.. 100.00 BogoMIPS (lpj=50000)
pid_max: default: 32768 minimum: 301
�����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
cpu cpu0: Error -2 creating of_node link
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
random: fast init done
clocksource: Switched to clocksource nios2-clksrc
random: crng init done
futex hash table entries: 256 (order: -1, 3072 bytes)
workingset: timestamp_bits=30 max_order=15 bucket_order=0
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
8001440.serial: ttyJ0 at MMIO 0x8001440 (irq = 2, base_baud = 0) is a Altera JTAG UART
mousedev: PS/2 mouse device common for all mice
Warning: unable to open an initial console.
Failed to create /dev/root: -2
VFS: Cannot open root device "(null)" or unknown-block(0,0): error -2
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
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Mictor Connector for debugging on Cyclone V SOC Development Kit

April 8, 2017, 2:13 am
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Hi,

Can some one please provide me suitable document reference using which the debugging of CYCLONE V Soc is being done using mictor connector in SOC Development Kit

I am short of any document that gives reference to such circuit.

We want to verify this for one of our board design :-

Thanks and Regards.
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Clocking is too complex - error

April 8, 2017, 6:55 am
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Please advise me how to get rid of error from the title. It appears when I try to compile following code:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ff IS
PORT(
t : IN std_logic;
s : IN std_logic;
r : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic);
END ff;
ARCHITECTURE behavior OF ff IS
SIGNAL qs : std_logic;
BEGIN
PROCESS(r,s,t)
BEGIN
IF (r='0') THEN
    qs<='0';
ELSE
    IF (s='0') THEN
        qs<='1';
    ELSE
        IF (rising_edge(t)) THEN
            qs<=not(qs);
        END IF;
    END IF;
END IF;
END PROCESS;
q <= qs;
qi <= not(qs);
END behavior;
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operational hours for starting a process

April 8, 2017, 9:55 am
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hi there guys,

i need help with my VHDL project,

i would like to define operational hours for a process to begin.


the insertion of the hours will be entered through a GUI i'm building with WPF.

{for example, i'm entering 7:00 to 19:00 in a GUI i've built in c#, and i would like my project to check wether the current hour is whitin this range; if the answer is yes - start some process.}

how can this be achived? any helpfull references?






Thanks ahead.




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Read in external ADC values

April 8, 2017, 9:59 am
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Hello everybody,

I'm a newbie on VHDL programming, but for a course at university we have to deal with the DE1-SoC and the THDB-ADA Board.
I want to read out the values of the ADC and display them in the signal analyzer in Quartus.

So this is my source code (.vhdl):

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;

entity ADC_test is
port(

ADC_CS_N: in std_logic; --internal ADC
ADC_DIN: out std_logic;
ADC_DOUT: in std_logic;
ADC_SCLK: out std_logic;

CLOCK_50: in std_logic; --clocks
CLOCK2_50: in std_logic;
CLOCK3_50: in std_logic;
CLOCK4_50: in std_logic;

DRAM_ADDR: out std_logic_vector(12 downto 0); --SDRAM
DRAM_BA: out std_logic_vector(1 downto 0);
DRAM_CAS_N: out std_logic;
DRAM_CKE: out std_logic;
DRAM_CLK: out std_logic;
DRAM_CS_N: out std_logic;
DRAM_DQ: inout std_logic_vector(15 downto 0);
DRAM_LDQM: out std_logic;
DRAM_RAS_N:out std_logic;
DRAM_UDQM: out std_logic;
DRAM_WE_N: out std_logic;

ADC_CLK_A: out std_logic; --GPIO
ADC_CLK_B: out std_logic;
ADC_DA: in std_logic_vector(13 downto 0);
ADC_DB: in std_logic_vector(13 downto 0);
ADC_OEB_A:out std_logic;
ADC_OEB_B:out std_logic;
ADC_OTR_A:in std_logic;
ADC_OTR_B:in std_logic;
DAC_CLK_A: out std_logic;
DAC_CLK_B: out std_logic;
DAC_DA: in std_logic_vector(13 downto 0);
DAC_DB: in std_logic_vector(13 downto 0);
DAC_MODE: out std_logic;
DAC_WRT_A: out std_logic;
DAC_WRT_B: out std_logic;
OSC_SMA_ADC4: in std_logic;
POWER_ON: out std_logic;
SMA_DAC4: in std_logic


);

end ADC_test;



architecture arch_adc of ADC_test is

signal clk : std_logic;

begin

process(CLOCK_50)
begin

clk <= CLOCK_50;


end process;

end arch_adc;

Complilation succeeded but when I start the signal analyzer it displays "waiting for clock".
Do you have some ideas what I forgot to include?
Do I have to include an pll?

Thank you for your help.

Christoph :o
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Arria10 - uboot preloader hangs in 'data abort' exception

April 8, 2017, 11:31 am
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Hi,


I try to boot Linux on my custom made arria 10 board. On my board RAM is
connected to the FPGA directly, and HPS has no access to it using
default addresses (0x00000000 - 0xbfffffff). It is supposed to use RAM
using HPS to FPGA bridge (0xc0000000 - 0xfbffffff) and FPGA takes care
of initializing RAM.


msel is set so fpga is automatically programmed at the startup from
qspi. bsel is set to boot from sdcard.


I've created FPGA project for my board. First error is that when
generating handoff files, there is no emif.xml (because there is no ram,
right?), so I've stubbed this file with empty values. Uboot has built
without error and I managed to boot preloader while being connected via
jtag. I can step through code, read memory, registers and so on - a
normal session with GDB.




And here are the problems:


uboot code goes into "data abort" exception in


Code:
arch/arm/cpu/armv7/socfpga_arria10/sdram.c:124
int is_sdram_cal_success(void)
{
    return readl(&socfpga_ecc_hmc_base->ddrcalstat);
}
reading socfpga_ecc_hmc_base returns:


Code:
(gdb) p socfpga_ecc_hmc_base
$1 = (const struct socfpga_ecc_hmc * const) 0xffcfb000
So it is a valid pointer to ecc_hmc_ocp_slv_block. BUT, trying to read
this location gives error:


Code:
(gdb) x/1x 0xffcfb000
Error: data abort at 0xffcfb000, dfsr = 0x00000008
and it's the end. I can read some other registers (uart0 register)


Code:
(gdb) x/1x 0xFFC02008
0xffc02008:    0x000000c1
I cannot also read GPIO2 register nor set it to flash a diode.




Now some questions arises


1) Can Linux work when RAM is not connected to hsp MMU but to FPGA?
2) Can bsp-editor generate device tree files without emif.xml? Without
the file it rises error and refuses to go on (thus creating empty emif.xml)
3) Why can't I read some peripheral register? More, why uboot can't do
it and crashes?


I would appriace any help, any suggestions that could lead me to
solution.
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Looking for bigger, fasterFPGA with on-chip flash/imamge/code..

April 8, 2017, 2:43 pm
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Hi guys. New here. New to Altera.

I am looking for a new FPGA for a project i am working on - something with on chip flash/image/code, like possibly the Max 10 series.
I developed a project on the Spartan3AN to take advantage of on-chip flash. The chip resources are 80%+, including on-chip flash (no external storage required).
I'm hoping the Max 10 can do better.
The Max 10 looks like a good chip, and the Altera programming tools & documentation are inviting.
I'm just comparing Spartan3 devices to Max10 devices, gates vs. Logic elements, vs. CLB vs. Cells. bits vs. bytes. :p
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Altera SoC FPGA programming Environment

April 9, 2017, 3:50 am
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I am new to program SoC fpga I have a De0 nano SoC board.I am trying to program HPS ARM processor with C language. I have Qsys .info and .sof files which were generated via qsys. I tried with Altera monitor program and found that C code is not available to edit in the software, on disassembly window it shows assembly code. Is there any way to compile and check errors in C code? Is EDS software is free to use without license?
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Altera monitor program text editor not appearing

April 9, 2017, 4:52 am
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I am trying program De0 Nano Soc FPGA using Altera monitor program. I browsed code and selected when crating new project and i cannot navigate to text editor. the code is running and in Disassembly window it shows assembly instructions. i need to edit c codes in text editor which is in Altera monitor program tutorial pdf
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EP3SL150F1152C4N, it's lead free device part, but this device still contains Pb ?

April 9, 2017, 7:41 pm
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Hello,

Does solder bump of EP3SL150F1152C4N (D/C 1213) contains lead(Pb) which is under ROHS exemption 15 ?
(RoHS Exemption #15: Lead in solders to complete a viable electrical connection between the semiconductor die and the carrier within the integrated circuit flip-chip packages)

Is there anyone can advise how many Lead(Pb) are contained in this device under ROHS exemption 15 ? it will be better if you can send Altera Material Declaration for this device.

And it's very urgent, pls reply asap if you have information about that, thank you very much.
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FPGA(Opencl) code work well in emulator mode, but can't finish run on the FPGA

April 9, 2017, 7:56 pm
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Hello：
When I run my FPGA(OpenCL) code in emulator mode, the result is right; but after I create hardware configuration file and run on the FPGA, the code is blocked and can't finish.My code used channel.What is the problem?How to debug the code in this situation?Thank you very much!
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generating matrix multiplication IP core

April 9, 2017, 8:41 pm
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Hi,
when I generated the matrix multiplication IP core in Quartus 16.1, the system showed error information as follows.

Info: Starting: Create HDL design files for synthesis
Info: qsys-generate C:\intelFPGA\16.1\temp\multi.qsys --synthesis=VHDL --greybox --output-directory=C:\intelFPGA\16.1\temp\multi --family="Arria 10" --part=10AX115R3F40I2SGE2
Progress: Loading temp/multi.qsys
Progress: Reading input file
Progress: Adding fp_matrix_mult_ii_0 [altera_fp_matrix_mult_ii 16.1]
Progress: Parameterizing module fp_matrix_mult_ii_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: multi: "Transforming system: multi"
Info: multi: Running transform generation_view_transform
Info: multi: Running transform generation_view_transform took 0.000s
Info: fp_matrix_mult_ii_0: Running transform generation_view_transform
Info: fp_matrix_mult_ii_0: Running transform generation_view_transform took 0.000s
Info: multi: Running transform merlin_avalon_transform
Info: multi: Running transform merlin_avalon_transform took 0.067s
Info: multi: "Naming system components in system: multi"
Info: multi: "Processing generation queue"
Info: multi: "Generating: multi"
Info: multi: "Generating: multi_altera_fp_matrix_mult_ii_161_k7waf2q"
Info: fp_matrix_mult_ii_0: C:/intelfpga/16.1/quartus/../hls/bin/internal_matrixmult_helper --fp-relaxed -march=altera --RTL-only -o matrix_mult --device {Arria 10} --clang-arg -generate-altera-ip -I. C:/intelfpga/16.1/ip/altera/dsp/altera_fp_matrix_mult_ii/matrix_mult.cpp
Error: fp_matrix_mult_ii_0: IP geneneration failed at file discovery, please tell Altera
Error: couldn't open "C:/Users/tan/AppData/Local/Temp/alt7266_5283635077998688715.dir/0001_fp_matrix_mult_ii_0_gen//matrix_mult.prj/components/altera_fp_matrixmult/altera_fp_matrixmult_internal_hw.tcl": no such file or directory
while executing "discover_files $proxy_file_set $tmp_dir" (procedure "generate_all" line 15) invoked from within "generate_all $output_name QUARTUS_SYNTH" (procedure "generate_quartus_synth" line 2) invoked from within "generate_quartus_synth multi_altera_fp_matrix_mult_ii_161_k7waf2q"

I checked the directory C:/Users/tan/AppData/Local/Temp/alt7266_5283635077998688715.dir/0001_fp_matrix_mult_ii_0_gen, and found that it is empty.

The system environment is Windows 10 professional + Quartus 16.1, and I tried the device on Arria 10 and Stratix V. The errors were same. Could you give me some comments to solve this problem.

Thanks a lot

Tan
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CycloneV-SoC U19 variants

April 10, 2017, 12:45 am
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error of PCIE PERST_N whe running fitter!

April 10, 2017, 12:51 am
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Error (169029): Pin PERST_N is incompatible with I/O bank 3B. Pin uses I/O standard 2.5 V, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.5V.
Extra Info (169121): Device 5SGXMA3H2F35I3


how to solve this problem ?
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