How to time constrain output pin connected to input pin on the same FPGA (design) ?

April 19, 2017, 4:30 am

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Hello,

My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.

How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.

Thaks in advance
Vladimir

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MAX 10 NEEK Quartus

April 19, 2017, 5:30 am

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Hi all,

I want to monitor power on the fpga board when a video fro HDMI i/p is played on the LCD screen.
In the Design examples, there is a code for power monitor and another one for HDMI.

Any suggestions as to how should I start??
I am new to FPGA's .

Control NIOS II program from "NIOS II Console" (without HAL functions)

April 19, 2017, 7:14 am

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Hello,

I'm trying to implement control of NIOS II program from NIOS II Console.
Here is snippet of code:

Code:

---

void sw_get_command(cmd_type *cmd) {
    alt_u8 btn;
    btn = (alt_u8) btn_read(BTN_BASE) & 0xf;    // read 4 pushbuttons
    if (btn != 0) {                                // a button pressed
        if (btn & 0x01)                          // button 0 pressed
            cmd->pause = cmd->pause ^ 1;            // toggle pause bit
        if (btn & 0x02)                          // button 1 pressed
            cmd->prd = pio_read(SWITCH_BASE) & 0x03ff;  // load new interval
        if (btn & 0x04)
        {
            alt_u8 rvalid = 0;
            alt_u32 data_reg = 0;
            do{
                data_reg = IORD(JTAG_UART_BASE, JUART_DATA_REG_OFT);
                rvalid = data_reg >> 15 & 0x01;
            } while (rvalid == 0);
            printf("data = %c\n", (char)data_reg & 0xff);
            printf("ravail = %d\n", (data_reg >> 16) & 0xffff);
        }
        btn_clear(BTN_BASE);
    }
}

---

The sw_get_command is called from while(1) loop.
If button 2 is pressed (condition btn & 0x04), user is invited to type some value in NIOS II Console.
The value can have multiple symbols.
I'm faced to problem how to read all symbols. Actually when I read a symbol (in the command data_reg = IORD(JTAG_UART_BASE, JUART_DATA_REG_OFT)), it seems that read FIFO is erased.
Otherwise how to explain that after leaving the do-while loop, the value of ravail (number of characters remaining in the read FIFO) is 0 (1st image - screenshot of NIOS II console).
Another question: after some "exercises" with button 2, the communication crashes and Eclipse becomes unavailable (2nd screenshot - fragment of Windows Task Manager screenshot).

Thanks in advance.

Attached Images

• NIOSII_Console_Control.jpg (339.7 KB)

University VWF fault

April 19, 2017, 8:50 am

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Good afternoon,
I was wondering if anyone could possibly offer me some help, as a mature student going back to study EE after a 20 year break I'm finding some things a little testing, I have been asked to design a matrix multiplier, I have done this by creating a chip with 3 multis and adders, when compiled it works produces a VWF, when I put 9 chips together and compile all is good but when I try to produce a VWF all I get is this message
Top level modules: # multiplxer


# End time: 16:36:55 on Apr 19,2017, Elapsed time: 0:00:04
# Errors: 0, Warnings: 0


# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct 7 2014
# Start time: 16:36:56 on Apr 19,2017
# vlog -work work Waveform2.vwf.vt
# -- Compiling module multiplxer_vlg_sample_tst
# ** Error: Waveform2.vwf.vt(31): near "0": syntax error, unexpected INTEGER NUMBER, expecting ')'


# End time: 16:36:56 on Apr 19,2017, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0





# ** Error: C:/altera/15.0/modelsim_ae/win32aloem/vlog failed.
# Executing ONERROR command at macro ./multiplxer.do line 4


Error.

any help would be gratefully received
cheers Boots

Glitch Filtering Power Estimation

April 19, 2017, 3:07 pm

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Hello,

I'm trying to predict the power consumption of my VHDL design using PowerPlay Analizer in Quartus Prime SE. For that I'm doing the gate level simulation with Modelsim-Altera 10.5b with the option 'generate VCD file' turned on. My problem is that there is no difference in the estimated current consumption of the design when I modify the 'Enable glitch filtering' option under 'EDA Tool settings>Simulation'. Anyone knows what may be the cause for this? Fyi, the 'Perform glitch filtering on VCD files' under 'PowerPlay Power Analizer Settings' does modify the estimated current value.

Edit: I forgot to mention that the design is intended for a Cyclone V device which may be the cause of the issue, since gate-level timing simulation is no longer supported for this devices. From the 'Quartus Prime SE Handbook vol 3: Verification' document:

"Note: Gate-level timing simulation of an entire design can be slow and should be avoided. Gate-level timing simulation is supported only for the Stratix IV and Cyclone IV device families. Use TimeQuest static timing analysis rather than gate-level timing simulation."

Correct me if I'm wrong, but isn't timing simulation the way to bring up glitches? I have also found another thread that supports this conclusion (see posts #9 and #10): http://www.alteraforum.com/forum/showthread.php?t=36762

Regards,
Federico

DE1-SoC-UP: UVC Driver Re-Compilation or Install

April 19, 2017, 6:55 pm

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Hi all,

Looking to add a simple varifocal lens usb camera to my design to test out some image processing functionalities on the board. But I've come to realize that the system image provided by the University site (DE1-SoC-UP) is a Linaro variant (3.18.0) and doesn't have the UVC or V4L2 driver's I need to actually integrate the camera into my system.

I do know that UVC driver functionality can be added at kernel compilation time through menuconfig, but can't seem to find any source code for the UP image online. There's a lot of material the UP image has on it that I depend on, and I'd rather not have to recompile everything from a "from scratch" version of the source code for fear that I might miss or leave something out (relatively inexperienced at the moment in regards to custom linux compilations and u-boot creation for the DE1-SoC board Architecture). But in order to do anything with the webcamera's I have, I need those drivers.

Does anyone know of either an easy way to install UVC drivers onto the Kernel that Altera has provided without recompilation, or if not, where I can find the source code and required information necessary to recompile without losing anything I already have on the system?

Any help on this end would be very much appreciated.

Thanks,

-Sky

C and C++

April 19, 2017, 10:43 pm

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What is the difference between C n C++............................................... ..

implementing distance sensor in my code

April 19, 2017, 11:43 pm

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Hello all,
I really need your help, i'm kind of in the dark here

i want to implement 'Sharp's' Distance sensor {DataSheet attached} in my project
and i honestly don't know where to begin coding.

If to look at the great picture - i want to be able to know when the object is 20 CM from the sensor and then perform an action( turning LED or anything else).

can anyone please guide me? or giving me something to read? any video i can watch?
it will be highly appriciated!

i'm using DE2-115, BTW.

Attached Files

• distance_sensor.pdf (364.8 KB)

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MAX10 flash memory address mapping

April 20, 2017, 12:58 am

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Hi,


I have instantiated an Altera on chip flash memory in a code to perform field upgrade in a 10M08 device.
1. Please clarify the starting address to be used, to write an application image to CFM1 & CFM2.
2. Why is the address line width is [16:0] (in fig.2), and not [17:0] even though it require 18-bits to represent the address space of CFM1 & CFM2.





fig.1 - Address Mapping in Dual Compressed Image configuration mode




fig.2 - On Chip Flash IP


Thanks in advance ,
SSK

USB Blaster II shows as Cypress FX2LP No EEprom

April 20, 2017, 1:52 am

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Hello,

i have the Cyclone V Soc Dev. Board with the integrated USB Blaster II.

When I powered the Board this morning the USB Blaster didn't show up in the device manager. Instead a unkown device has popped up.
After doing a little research I found out that the device is the Cypress FX2. I attached an Image from the UBS Device Viewer.

I'm a little confused because didn't change a jumper or anything else on the Board.
Can anyone tell me how I get the USB Blaster back? :confused:

Best Regards,
ruebe

Attached Images

• Cypress.jpg (247.5 KB)

about error "instantiates undefined entity "dspba_delay_ver"

April 20, 2017, 2:33 am

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1.build a mdl file project in simulink use altera dsp builder advanced blockset.
2.run in the modelsim ,result is ok.
3.add the qip file to my project in quartus II 15.0 .
4.when i compile the design ,there are errors like this:Error (12006): Node instance "redist273" instantiates undefined entity "dspba_delay_ver"
is anyone can help me ,thanks?

passing data from Linux to preloader

April 20, 2017, 3:45 am

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I would like to pass data (1 byte is enough) from Linux to preloader. Is there any general purpose register or a safe memory address I can write to and then reboot Linux?

Is the initswstate or the handoff registers for this purpose a bad idea?

MAX10 Discrete I2C implementation of RSU issue

April 20, 2017, 4:37 am

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Greetings,
I'm using Quartus 16.1 and trying to implement remote system upgrade over I2C using a discrete implementation on a MAX 10 (10M08SAE144C8G). After viewing the training videos it is clear that there is a requirement to use dual compressed image in QSYS. When this is done and the design is compiled, the error "14740 Configuration mode on atom ...|ufm_block does not match the project setting" is produced. If I change the QSYS setting to single uncompressed image the compilation completes without error. I don't know if the design works with this setting yet but it seems inconsistent. Am I missing some setting in the Quartus project that must be set to use dual configuration?

Any suggestions for resolving this issue would be much appreciated.

FPGA-to-HPS SDRAM Interface Problem

April 20, 2017, 5:31 am

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Hello!

I have system where I want to transfer data to HPS memory using custom IP in FPGA during the boot process (before U-Boot stage). Does the Preloader (U-Boot SPL) initialize the FPGA-to-HPS SDRAM Interface? In Signaltap the f2h_sdram0/avm_waitrequest signal is always high. Do I have to modify the SPL-code to enable the FPGA-to-HPS SDRAM Interface?

regards,
Joonas

DE2i-150

April 20, 2017, 5:50 am

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How to write code for atom processor in DE2i-150 and how to dump it on this kit? Please reply to the earliest.

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how to link the file to the SDRAM in qsys tools

April 20, 2017, 6:40 am

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hi everyone..can you help me? i try to connect the file to the SDRAM in qsys..and according to the journal that i found,i need to add the system and SDRAM clock for DE-series board through the university program library component..but unfortunately in my qsys, the university program library component didn't exist !!! :confused::confused:...what should i do now..hmmmm

NIOS II linker cannot find function that is referenced in the main source file

April 20, 2017, 7:36 am

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Hello,

Quite strange error appears while building project:

undefined reference to `function1(unsigned long, unsigned long)

function1 is located in one of the project source files and corresponding #include directive does present in the source file where function1 is referenced.

Did someone experience such issues ?

Thanks

JTAG Programming successfull but no effect at the ouput

April 21, 2017, 12:11 am

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I am using a Cyclone III EP3C120F484 device for my custom board. When I connect the USB Blaster and run the JTAG programmer in Quartus, the programming is done with no error. The code is just written to on/off the two LEDs. I have no PLLs or clocks involved yet to keep things simple. However, after the programming is done, I see no output on the pins. Everything is tied to 3.3V regardless of the configured program.

I have three voltage supplies for my FPGA: 1.2V for the core, which is okay, 2.5V for the JTAG and PLL, which are okay, and 3.3V for outputs on all banks, which look okay. I also checked the JTAG chain in Quartus which seemed okay.

I have checked the Conf_Done pin. This pin is high before programming and goes low after programming is done.Monitor the TDI and TDO pins. But i didn't reach the problem.


Can anyone help me with what could potentially be the problem?

DE0-NANO Board SDC file and PLL

April 21, 2017, 3:14 am

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Hallo

I have a DE0-NANO board. There is a on board 50 MHz oscillator on the board which works as the clock to the FPGA. Now suppose i want to run my design at 30 MHz. So i write a SDC file like the following, would this work? I mean would this already create a pll which will run my design at 33 MHz when i download it on the FPGA?

# Constrain clock port clk with a 30-ns requirement


create_clock -period 33 [get_ports clk]


# Automatically apply a generate clock on the output of phase-locked loops (PLLs)
# This command can be safely left in the SDC even if no PLLs exist in the design


derive_pll_clocks


derive_clock_uncertainty


# Constrain the input I/O path


set_input_delay -clock clk -max 0.5 [all_inputs]


set_input_delay -clock clk -min 0.1 [all_inputs]


# Constrain the output I/O path


set_output_delay -clock clk -max 0.5 [all_outputs]


set_output_delay -clock clk -min 0.1 [all_outputs]

quartus_jli device verify failure on USB 3.0

April 21, 2017, 1:14 pm

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Hi all,

## Description

I'm having a verify failure when programming Cyclone IV with quartus_jli only when running on USB 3.0.

When I use the same computer with its USB 2.0 I don't have this issue.

Output:

```
Info: Command: quartus_jli -c 1 -a program ./firmware/BrainsightNIRS.jam
Inconsistency detected by ld.so: dl-close.c: 811: _dl_close: Assertion `map->l_init_called' failed!
Device #1 is EPCS64
erasing ASC device(s) in sector mode...
programming ASC device(s) in sector mode...
CRC verify ASC device(s) in sector mode...
Device verify failure
Exit code = 11... Device verify failure
Error: Quartus Prime Jam Tools was unsuccessful. 0 errors, 0 warnings
Error: Peak virtual memory: 189 megabytes
Error: Processing ended: Fri Apr 21 11:39:21 2017
Error: Elapsed time: 00:01:35
Error: Total CPU time (on all processors): 00:00:19


```

## Environment

* Ubuntu 16.04
* Quartus Altera Lite 16.0
* USB 3.0 (Computer) Connected to FX2 USB chip connected to FPGA Cylone IV

Had anyone had a similar problem?