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Error (10481): VHDL Use Clause error at fir_compiler_v13_0_ast.vhd(33)

April 20, 2017, 6:44 pm
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I exported a series of HDL files with DSP Builder 13.0,and setup a new quartus ii project,but when I started compilation,some errors occured,the error information is :
Error (10481): VHDL Use Clause error at fir_compiler_v13_0_ast.vhd(33): design library "auk_dspip_lib" does not contain primary unit "auk_dspip_lib_pkg_fir_130"


Error (10800): VHDL error at fir_compiler_v13_0_ast.vhd(33): selected name in use clause is not an expanded name


then I found the file auk_dspip_lib_pkg_fir_130.vhd，added it into my project，and I also tried to add the lib file into my project,but the error still existed.
quartus ii help information is :
CAUSE: In a Use Clause at the specified location in a VHDL Design File (.vhd), you tried to access the specified primary unit of the specified design library. However, the design library does not contain the primary unit, or the primary unit has not been successfully compiled. For example, the Use Clause in the following code attempts to access the primary unit example, but the ieee design library does not contain the primary unit example:
LIBRARY ieee;
USE ieee.example;
ACTION: Access only primary units that exist in a design library and have been successfully compiled.

but I don't understand the ACTION.
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Downloading ELF failed

April 22, 2017, 1:20 am
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What do I do if I have the error "Downloading ELF failed" in Nios II SBT?

I built a system in Qsys that had 0 errors, it compiled and I could load it to the board.

What is then the error in Nios II SBT when I can't load the ELF file?

I tried different run configuration but none of them works.

The processor doesn't seem to respond:
Code:
$ nios2-download -g system.elf Using cable "USB-Blaster [2-2]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused
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Supress Eclipse command "gdb-set auto-solib-add"

April 22, 2017, 4:15 am
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I have a remote connection to a target running a nios2 processor with uClinux distribution over TCP/IP under the control of Eclipse-CDT. nios2-linux-uclibc-gdb debugger doesn't support set auto-solib-add command. So when I start the application Eclipse (among other commands) sends: gdb-set auto-solib-add on command to the debugger and it responds with an error,msg="No symbol \"auto\" in current context." That causes launch to fail.
I tryed to reset "Load shared library automatically" flag under Run->Debug Configurations...->C/C++ Remote Application->Debugger->Shared libraries. But it sends the same command with gdb-set auto-solib-add off and runs into the same error.

The same question were posted Stackoverflow.com (-> http://stackoverflow.com/questions/13646357/eclipse-cdt-how-to-suppress-some-gdb-commands) and it suggests that it comes from the final launch sequence of Eclipse, so the command sequence cannot be supressed easily. The post on stackflow doesn't help me. Any idea how to influence Eclipse.

Eclipse-CDT: Kepler
Quartus 16.1
debugger: nios2-linux-libc-gdb

Many thanks
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mutliple VHDL designs maneuvering

April 22, 2017, 4:37 am
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Hello all,
i have 4 VHDL files i wrote (4 different modes to my project).
and i've built a c# program that allows the user to choose which mode to operate.

i think i did it wrong when i created 4 different projects for each mode
how can i combine all of the code files to be under one project and evantually burn them all to the board.?

cheers,
kobi
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monitor program, Does it support c ++?

April 22, 2017, 8:22 am
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During the process of putting the makefile on the sd card, ds-5 says it needs a license. So first I try to compile using a free monitor program.
The 14.0 monitor program states that the c program / assemble language can be compiled into the system. If so, does c program also support c ++? Or do you only support c? I look forward to your reply. I would appreciate your reply.
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simulation error while implementing md5

April 22, 2017, 10:10 am
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hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values
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Error:Port "cg" does not exist in macro function "ADD0"

April 22, 2017, 1:53 pm
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So i got 8 error while compiling this 4 bit Carry-lookahead adder. I got the above error for ports cg and cp in macro functions ADD0-ADD3. For my code check the attachments. Edit: Here i've copied the code in:

Quote:
library IEEE;
use IEEE.std_logic_1164.all;
entity cla4 is -- 4-bit CLA structural model: top entity
port( a, b: in std_logic_vector(3 downto 0);
carryin: in std_logic;
sum, ch, cq: out std_logic_vector(3 downto 0);
cgout, cpout, overflow: out std_logic);
end cla4;
architecture arch of cla4 is
component fagp -- component declaration
port( a, b, cin: in std_logic;
sum, cg, cp: out std_logic);
end component;
component cla_logic -- component declaration CLA-generator
port( g, p: in std_logic_vector(3 downto 0);
cin: in std_logic;
c: out std_logic_vector(2 downto 0);
cgout, cpout: out std_logic);
end component;
signal carry: std_logic_vector(3 downto 0); --local signals
signal cg, cp: std_logic_vector(3 downto 0);
signal cout: std_logic;
begin
carry(0) <= carryin;
ADD0:
fagp
port map (a(0), b(0), carry(0), sum(0), cg(0), cp(0));
ADD1:
fagp
port map (a(1), b(1), carry(1), sum(1), cg(1), cp(1));
ADD2:
fagp
port map (a(2), b(2), carry(2), sum(2), cg(2), cp(2));
ADD3:
fagp
port map (a(3), b(3), carry(3), sum(3), cg(3), cp(3));
--generate carries from
--propagate and generate values
--from full_adder_g_p_g_p
CLA:
cla_logic
port map(cg, cp, carryin, carry(3 downto 1), cout, cpout);
cgout <= cout;
overflow <= carry(3) xor cout;
end arch;

Quote:
library IEEE;
use IEEE.std_logic_1164.all;
entity cla_logic is
port(
G, P: in std_logic_vector(3 downto 0);
CIN: in std_logic;
C: out std_logic_vector(2 downto 0); -- “internal” carry
CGOUT, CPOUT: out std_logic);
end cla_logic;
architecture arch of cla_logic is
begin
C(0) <= G(0) or (P(0) and CIN);
C(1) <= G(1) or (G(0) and P(1)) or (CIN and P(0) and P(1));
C(2) <= G(2) or (G(1) and P(2)) or (G(0) and P(1) and P(2)) or (CIN and P(0) and P(1) and P(2));
CGOUT<= G(3) or (G(2) and P(3)) or (G(0) and P(2) and P(3)) or (G(0) and P(1) and P(2) and P(3)) or (CIN and P(0) and P(1) and P(2) and P(3));
CPOUT<= (P(3) and P(2) and P(1) and P(0));
end arch;
Quote:
library IEEE;
use IEEE.std_logic_1164.all;
entity fagp is
port( a, b, cin: in std_logic;
sum, g, p: out std_logic);
end fagp;
architecture arch of fagp is
begin
sum <= a xor b xor cin;
p <= a and b; --complete this
g <= a or b; --complete this
end arch;

Any Ideas??
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variable initialization help

April 22, 2017, 2:41 pm
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Hi all,

For a process, the variable only take the initial value at the first time the process is running, then it will take the last value of that variable. I am wondering how can I initial the variable every time the process is executed?

For example, if I want to do something like following

Code:

ENTITY example IS
PORT (
  ......
  InitVal : IN INTEGER;  -- initial value
  ......
);

ARCHITECTURE rt OF example IS
......
  PROCESS (...)
  VARIABLE v1 : INTEGER := InitVal;
  BEGIN
      if (v1 < 100) then
        v1 := v1 + 1;
      end if;
  ......
  END PROCESS;
END ENTITY;
InitVal is the integer input from upper level module, I want the variable v1 has the value of InitVal every time the process is executed. What can I do in this case?

Many thanks for the help.
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Cannot run stimulus module using Quartus Prime?

April 22, 2017, 2:58 pm
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Attempting to learn Verilog right now. I am currently running through Verilog HDL by Palanatkir and am using Quartus Prime Lite as my current EDA. I am very new at this but just wondering, the book has us code a stimulus block as one of our very first exercises. I cannot figure out how to get Quartus to compile with it, as Quartus just states that the top level block has no logic.

Here is my code:

Code:
        module stimulus;
        reg clk;
        reg reset;
        wire [3:0] q;
       
        R_CC rcc0(q, clk, reset);
       
        initial
            clk = 1'b0; // set clk to 0
        always
            #5 clk = ~clk; // toggle clk every 5 tu
           
        initial
        begin
            reset = 1'b1;
            #15 reset = 1'b0;
            #180 reset = 1'b1;
            #10 reset = 1'b0;
            #20 $finish; // terminate sim
        end
       
        initial
            $monitor($time, " Output q = %d", q);
           
    endmodule

    // module - basic building block of Verilog
    // Ripple Carry Counter
    module R_CC(q, clk, reset);
        output [3:0] q; // io signal and vector decl
        input clk, reset;
       
        T_FF tff0(q[0], clk, reset);
        T_FF tff1(q[1], q[0], reset);
        T_FF tff2(q[2], q[1], reset);
        T_FF tff3(q[3], q[2], reset);
       
    endmodule

    module T_FF (q, clk, reset);
        output q;
        input clk, reset;
        wire d;
       
        D_FF dff0(q, d, clk, reset);
        not nl(d, q); // not is a Verilog primative
       
    endmodule

    module D_FF(q, d, clk, reset);
        output q;
        input d, clk, reset;
        reg q; // wtf
       
        always @(posedge reset or negedge clk)
        if (reset)
            q <= 1'b0;
        else
            q <= d;
           
    endmodule
Maybe I am using the wrong tool? Should I be using ModelSim or something similar?
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Verilog Coding

April 22, 2017, 10:59 pm
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The following Verilog code is used to realize the SVPWM technique.The code has 5 modules.The module "sect_det" when run shows the output "sd" same for all clock cycles though it has inputs that vary with every clock cycle. I am unable to identify the bug.Please help me with the same. Also, the code needs to be optimized. Suggestions are welcomed.
Verilog Code is attached.

Attached Files
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IP upgarde required

April 23, 2017, 2:56 am
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Hi,

I have installed Quartus Prime and using DE0 nano development board. When I add the LPM_MUX from the IP catalogue I have a red message "IP UPGRADE REQUIRED".
Pressing the button brings up a dialog button to launch the IP Upgrade tool. Please see attached screenshot.

I have used the 'upgrade in editor' and 'generate simulator script for IP' buttons. The regeneration status was successful, but I still have the red message "IP UPGRADE REQUIRED".

If I hover my mouse over the error it states "Compilation of IP is not supported in current software version". I have the latest version of quartus prime downloaded yesterday...

I'm wondering if someone else has seen this problem and has an idea what I need to do?

Many thanks for your time.

Best Regards
Peter Mayhew

PhD Research Student
University of the West of England
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Audio Core IP with ST interface: Clock setting

April 23, 2017, 8:41 am
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Hello everybody, this is my first Problem Report in this FORUM :D

So...
I'm trying to use the WOLFSON Audio CODEC on DE2 board to output an audio stream (96kSamples/sec) generated by Custom Hardware to the line-out port.
As suggested by various University Program IP user guide Im using all the IPs needed:

1) Clock Signals for DE-series Board Peripherals IP : with Audio clock exported to be connected to the audio chip (12.288Mhz- as suggested by datasheet)
2) Audio and Video Configuration IP : set with (Auto-Initializa Device = 1; Audio_out = 1; Data_format = Left Justified ; Bit Lenght = 16; Sampling_Rate = 96kHz)
3) Audio Core IP : set up with ST-interface , 16 bit-wide, and audio_out = 1;

What should be the clock connection within this components? (Im sure that the fist IP need 2 clock inputs: 50Mhz and 27Mhz, but I've no idea about the Audio Core IP . The suggested datasheet is not clear about this point)

Does the Audio and Video configuration IP set the CODEC in Master or Slave MODE?
Does the Audio Core IP and the Audio CODEC use the same clock source?

(i'm clearly configuring all the system on Qsys)

I'm a bit confused about this point, the official documentation seems to have a lack on this aspect of interconnecting the audio University program IP.

Best regards


Thank you
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[DE1-SOC] How to handle interrupt of msgDMA in a linux application

April 23, 2017, 11:33 am
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I'm using DE1-SOC and I have a system which streaming data from a fifo in FPGA to SDRAM by msgDMA.
I have controlled msgDMA to write the descriptor and read data from SDRAM successfully but I don't know how to register and handle the interrupt of event completing a transfer in linux application.
In my qsys design, the csr_iq of msgDMA is connected with f2h_irq0 of HPS, is it correct?

Is there a way to interrupt the program without writing a kernel module? I have no knowledge about writing a kernel driver.
Currently, I'm trying a stupid way as below:

Code:
  write_descriptor_to_base_address();
  csr_ret = read_csr_status();
  while(1) {
    if ( (csr_ret >> 8) & 0x1) == 1) {  // read the bit 9th where IRQ_ID was set
            handle_event_transfer_complete();
            break;
    }
  }
Could anyone here give me some advice to solve the problem?
Thank you,
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[DE1-SOC] How to handle interrupt of msgDMA in a linux application

April 23, 2017, 6:45 pm
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I'm using DE1-SOC and I have a system which streaming data from a fifo in FPGA to SDRAM by msgDMA.
I have controlled msgDMA to write the descriptor and read data from SDRAM successfully but I don't know how to register and handle the interrupt of event completing a transfer in linux application.
In my qsys design, the csr_iq of msgDMA is connected with f2h_irq0 of HPS, is it correct?

Is there a way to interrupt the program without writing a kernel module? I have no knowledge about writing a kernel driver.
Currently, I'm trying a stupid way as below:

Code:
  write_descriptor_to_base_address();
  csr_ret = read_csr_status();
  while(1) {
    if ( (csr_ret >> 8) & 0x1) == 1) {  // read the bit 9th where IRQ_ID was set
            handle_event_transfer_complete();
            break;
    }
  }
Could anyone here give me some advice to solve the problem?
Thank you,
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Question about nios ii interrupt registration

April 23, 2017, 11:17 pm
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Hi everyone

My hardware system model is nios2 based system with some peripheral and that of software is uClinux

i`m try to develop interrupt handle method in my software running in uClinux.

My goal is that some peripheral give interrupt sign and then nios2 processor handles this interrupt.

First of all, i tries to make BSP using SBT and use APIs(e.g alt_irq_register) in compiling of my software.

Here is my first question.

I can`t make BSP using SBT due to my nios2 uses MMU option.

So to make BSP, i temporary turns off MMU option during making BSP.

After i got BSP, again turns on MMU option and remake system.

In this case, is there any problem in using BSP?

The other question is about using APIs.

In compiling process of alt_irq_register.c, i see the error "undefined reference to 'alt_irq' & 'alt_irq_active'.

I sees inside of alt_irq_register.c and finds that there is no declaration of "alt_irq" and just use this variable.

I finds that alt_irq is defined at "alt_irq_handler.c", but i can`t find where alt_irq_handler() is called.

Is there anyone who have a experience of using BSP`s APIs in cross-compiling environments?

Please share your experience.

Thank you!
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got this error when using eclipse

April 24, 2017, 4:06 am
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hi everyone..can u tell me why i got this error in my eclipse?


make: *** [proj_Trafflight.elf] Error 1 proj_Trafflight C/C++ Problem

i already try to solved this error...but it's still same
really for your repsonse..tq :)
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FFT IP Core and Modelsim

April 24, 2017, 4:45 am
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Hello!
I'm trying to run the RTL simulation of a project which contains Altera FFT module. In Modelsim (spawned with the NativeLink), after pointing all libraries I still have an error:

Error: (vsim-3033) d:/workdir/@fpga/test/s2n_ram_eth_fourier_16_4/db/ip/fft1/submodules/fft1_fft_ii_0.sv(59): Instantiation of 'asj_fft_si_se_so_b' failed. The design unit was not found.

There are two versions of the missing 'asj_fft_si_se_so_b' file within the project, both encrypted and plain .vhd. For some reasons Modelsim still does not find it. Any help, please.

Regards!
Nick
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ARRAY with a dynamic range

April 24, 2017, 6:34 am
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Hi All,

I am tying to create an ARRAY dynamic size with range of 1-64 (XXX).
(I will use it for creating a dynamic data delay that can be configured)

Modelsim compile it with no errors , but i don't see a change in the array size in the wave window.

Can you help?

ENTITY a2d IS
PORT (
reset_n :in std_logic;
clk :in std_logic;
REG_CAN_DATA_A_DLY :in std_logic_vector (7 downto 0) --:="0000000000000001"; --:integer := 50;
);
END;



signal XXX :integer range 1 to 64;

type delay_array is array(1 to XXX) of std_logic_vector(15 downto 0);
signal data_delay_array : delay_array;

begin

XXX <= to_integer(unsigned(REG_CAN_DATA_A_DLY));


process ( reset_n,clk)
begin
if ( reset_n = '0') then

elsif (clk'event and clk = '1') then

data_delay_array <= data_in & data_delay_array( 1 to delay_array'high-1) ; data_in_delay <= data_delay_array(data_delay_array'high);




end if; end process;
END a2d;
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lpm_pack use for MAX10

April 24, 2017, 8:24 am
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Hi,

I am scoping out a project and before I get too far I was wondering will I have issues in synthesis using the lpm_pack.vhd library? Most of these are now missing from the IP catalog. Is this a software settings problem? I would like to use some of these modules to simplify my design.

Does anyone know what will be the case here?

Thanks,

D
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Cyclone V Reconfigurable PLL

April 24, 2017, 6:05 am
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I am attempting to use a reconfigurable PLL in a Cyclone V. I am using two routes – ModelSim Starter as provided with Intel FPGA toolset(Ver 16.1) and a full blown version of Modelsim (10.5a). I am having issues with both routes at the moment:

1. ModelSim Starter 10.5b

# Loading rtl_lib.cpu_pll_0002
# ** Fatal: Bad library format, library not compiled with Intel FPGA Edition compiler.
# Time: 0 ps Iteration: 0 Instance: /sys_clk_gen_tb/uut/cpu_pll_inst/cpu_pll_inst File: D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Altera_IP/CPU_PLL/cpu_pll/cpu_pll_0002.v
# FATAL ERROR while loading design
# Error loading design

This error occurs despite deleting the library and recompiling to give me a clean build.

2. ModelSim 10.5a

# Loading C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/altera_lnsim.altera_cyclonev_pll
# ** Error: (vsim-3033) C:/intelFPGA/16.1/quartus/eda/sim_lib/altera_lnsim.sv(27862): Instantiation of 'cyclonev_ffpll_reconfig' failed. The design unit was not found.
# Time: 0 ns Iteration: 0 Instance: /sys_clk_gen_tb/uut/sys_pll_inst/system_pll_inst/altera_pll_i/genblk2/genblk2/cyclonev_pll File: C:/intelFPGA/16.1/quartus/eda/sim_lib/altera_lnsim.sv
# Searched libraries:
# C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/altera_lnsim
# C:/intelFPGA/16.1/quartus/eda/sim_lib/verilog/cyclonev_ver
# D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Modules/sys_clk_gen/V1.0/Implementation/sim/modelsim/rtl_lib
# D:/Sandbox/Projects/TJ6394/Firmware/V1.0/Modules/sys_clk_gen/V1.0/Implementation/sim/modelsim/rtl_lib
# Loading work.altera_pll_reconfig_core
# Loading work.altera_std_synchronizer
# Loading work.dyn_phase_shift
# Loading work.generic_lcell_comb
# Loading work.self_reset
# Loading work.dprio_mux
# Loading work.fpll_dprio_init
# Error loading design

I assume I am missing a library but I am not sure which one- I have manually compiled all the cyclone v libraries but I cannot see any reference to the missing design unit in any of these libraries.

Anyone got any suggestions.....
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