Analyzing routing delay added for hold timing

May 1, 2017, 10:58 am

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Hi everyone,

I've got a design which has what I think is an excessive amount of routing delay added to meet holding timing, ~23us or 3.7% of our AVGZ routing resources. When I disable Optimize Hold Timing under Advanced Fitter Settings, the resulting compile has a Design-wide TNS of -72.503ns for Hold as reported in the Multicorner Timing Analysis Summary.

Analyzing the hold violations, the worst offenders are on register to register paths at the boundaries between Spine Clock Regions. I would expect this since these transitions are where the clock skew would differ the most.

I'm curious if there's a way to dig deeper into why these numbers are so different. My issue is that the device is full enough and is running fast enough that I believe this additional routing is pushing the design to where it's impossible to meet setup requirements. I consistently get no setup warnings when Optimize Hold Timing is disabled. The fastest clock domain is 300 MHz and is fairly close to meeting hold requirements with no hold optimization (-2.057ns TNS) but has 12us added with Optimize Hold Timing enabled and then fails setup.

If it helps, I'm using Quartus 16.1.0 Build 196

Thanks!
Scott

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automatic load code, compile, program from external code

May 1, 2017, 11:36 am

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Hi,

I am using Quartus II and a Cyclone III device.
I would like to be able to automatically load and compile a Verilog code, and then program the board without my intervention. I would like to control this process from an external software, so that after each time I program the board and before the next programing of it, I will have the external software run some tests on it.
My goal is to repeat the process many times, each time loading a different Verilog code and then testing it.

Is that possible? How do I do this?
Could this be done from C, Python, Matlab?

Thanks,
Itamar.

HSMC ports of Cyclone V GT FPGA Development Board

May 1, 2017, 1:10 pm

≫ Next: Interrupt handling problem using linux with DE1_SoC cyclone V

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Hi guys!!

I've got questions about HSMC port of Cyclone V GT FPGA Development Board.
I need to use that port to SPI communication and I/O.


I've read its datasheet and I've notice I can use it like I/O port (?)


My questions are:


1.- Can I use HSMC port to SPI communication of 50MHz?? If I can do it, Do I need another board, conector or anything?


2.-I've noticed that HSMC ports has 172 pins (120 are signals), I need to know if I can use that 120 pins like I/O.
Can I use it like I/O? If that is true, Do I need another board, conector or anything?


I need to used 100 I/O or SPI comunication and I don't know if that port lets me use it like I/O or SPI.


I've never used that port, therefore I'm asking here.


Thank for reply!!

Interrupt handling problem using linux with DE1_SoC cyclone V

April 28, 2017, 5:51 pm

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Hi


We are using cyclon V on DE1_SoC board to write a interrupt handling module. We used the demo from Cornell's web site (http://people.ece.cornell.edu/land/c...als/index.html), where they provide a SD card image named DE1-SoC-UP-Linux.img. The demo works well but we met problems as follows:
(1)We compiled this demo with Altera's latest linux kernel, and the resulted interrupt module can be inserted into linux kernel, but it can NOT receive any interrupt. The result is shown as:

Code:

---

    root@socfpga:~/interrupt# cat /proc/interrupts
              CPU0      CPU1     
    16:          0          0    GIC-0 199 Level    timer
    17:      5221      5137    GIC-0  29 Level    twd
    22:          0          0    GIC-0 136 Level    ffe01000.dma
    23:          0          0    GIC-0 207 Level    ff706000.fpgamgr
    24:        208          0    GIC-0 194 Level    serial
    32:          0          0    GIC-0 190 Level    ffc04000.i2c
    33:          0          0    GIC-0 191 Level    ffc05000.i2c
    36:      5777          0    GIC-0 171 Level    dw-mci
    37:        45          0    GIC-0 160 Level    ffb40000.usb, ffb40000.usb, dwc2_hsotg:usb1
    38:        11          0    GIC-0 152 Level    eth0
    73:          0          0  gpio-dwapb  3 Edge      pb_handler
    IPI0:        0          0  CPU wakeup interrupts
    IPI1:        0          0  Timer broadcast interrupts
    IPI2:        572      1145  Rescheduling interrupts
    IPI3:          2        1  Function call interrupts
    IPI4:          0        0  CPU stop interrupts
    IPI5:          0        0  IRQ work interrupts
    IPI6:          0        0  completion interrupts
    Err:          0

---

And with the demo SD card, the result is

Code:

---

              CPU0      CPU1     
    16:          0          0    GIC-0 199 Level    timer
    17:      53664      52132    GIC-0  29 Level    twd
    22:          0          0    GIC-0 136 Level    ffe01000.dma
    23:          0          0    GIC-0 207 Level    ff706000.fpgamgr
    24:      1022          0    GIC-0 194 Level    serial
    32:          0          0    GIC-0 190 Level    ffc04000.i2c
    33:          0          0    GIC-0 191 Level    ffc05000.i2c
    36:      25382          0    GIC-0 171 Level    dw-mci
    37:        45          0    GIC-0 160 Level    ffb40000.usb, ffb40000.usb, dwc2_hsotg:usb1
    38:        302          0    GIC-0 152 Level    eth0
    73:          0          0  gpio-dwapb  3 Edge      pb_handler
    IPI0:          0          0  CPU wakeup interrupts
    IPI1:          0          0  Timer broadcast interrupts
    IPI2:        395      27078  Rescheduling interrupts
    IPI3:          1          3  Function call interrupts
    IPI4:          0          0  CPU stop interrupts
    IPI5:          0          0  IRQ work interrupts
    IPI6:          0          0  completion interrupts

---

It can be found that the interrupt controller is different, and a controller named "gpio-dwapb" is used in my project.


Is it the reason it not work? And how to fix this problem? How to assign the correct interrupt controller, for example the GIC.


(2)I have repalced the .dtb and .rbf files in the demo SD card with mine, it still works well.
The kernel file in this demo SD card is uImage, I transform my zImage to uImage with command
mkimage -A arm -O Linux -T kernel -C none -a 0x00008000 -e 0x00008000 -n "Linux kernel Image by embedclub" -d zImage uImage
After replacing with my uImage, the system can' not boot up, why?


Thanks.

Minimal Cyclone V SE Testsystem on DE0-NANO-SOC: Uboot dies right after FPGA config

April 29, 2017, 5:55 am

≫ Next: Time on Ecos (or Qemu )

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Hi,

I made a minimum System in Quartus 15.1. The Qsys Systems consist only of an AvalonMM UART and a 8 bit PIO for the LEDs. The only bridge used is the lightweight HPS4FPGA one (in32bit mode). I got rid of all the complex FPGA2SDRAM bridge, and all the bells and whistles from the GHRD, because I will not need it in my application and want to start from a clean simple design. I enable I2C1 and HPS UART1 on top because I will need a secondary I2C bus layed out on the LTC connector of the board. I tested the settings for these in the original GHRD refernence design and that worked ok there.

I copied all the memory and Qsys settings using screenshots from the GHRD settings by hand to my "lightweight" design and built the system. I also created a preloader and Uboot for it. Preloader and U-Boot comes up fine, recognizes the 1GB DDR3, can read from SDCARD etc.

If I load the .rbf file in U-Boot and configure the FPGA, it configures the FPGA fine (the config done LED lits up), but exactly in that moment the U-Boot crashes and just does not take any input any more via the console.
I do not remap the HPS0 UART to a different location, I just enable the second HPS UART and the I2C1 in the QSYS (I think this remapping of the UARTs and I2Cs would have happened anyhow in the preloader already, so if there would be a setting wrong I shouldn't have ended up in Uboot right?)

Anyone has an idea where to start looking?

Markus

Time on Ecos (or Qemu )

April 29, 2017, 7:03 am

≫ Next: Ubuntu 14.04: Not able to build new rootfs for yocto

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I'm working with real time operating system Ecos. I run this code on ubuntu :

Code:

---

    #include <stdio.h>
    #include <sys/time.h>
    #include <unistd.h>
   
    static int tv_diff(struct timeval *t1, struct timeval *t2)
    {
        return
            (t1->tv_sec - t2->tv_sec) * 1000 +
            (t1->tv_usec - t2->tv_usec) / 1000;
    }
   
    int main(void)
    {
    struct timespec ts;
    struct timeval tv1, tv2;
   
    printf("Hello, eCos !\n");
   
    clock_gettime(1, &ts);
    tv1.tv_sec = ts.tv_sec;
    tv1.tv_usec = ts.tv_nsec / 1000;
    printf("Time: %ld \n", tv1.tv_sec);
    sleep(10);
    clock_gettime(1, &ts);
    tv2.tv_sec = ts.tv_sec;
    tv2.tv_usec = ts.tv_nsec / 1000;
   
    printf("Time: %ld \n", tv2.tv_sec);
   
    printf("diff Time: %d \n", tv_diff(&tv2, &tv1));
   
        return 0;
    }

---

and it worked properly :


root@ubuntu:/home/feres/Bureau# ./amin
Hello, eCos !
Time: 45417
Time: 45427
diff Time: 10000


But when i run it on Ecos ( wich it work on Qemu ) it give me this results:


Hello, eCos !
Time: 0
Time: 0
diff Time: 0


Is there any missing package on Ecos (or Qemu) or is there any specific commande to get time on Ecos (or Qemu)?

Ubuntu 14.04: Not able to build new rootfs for yocto

May 2, 2017, 2:55 am

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Hi all,

I am using Cyclone V SOC kit and try to enable CAN by following this thread:
http://www.alteraforum.com/forum/showthread.php?t=42747

However I stuck in building rootfs for yocto, although I followed the instructions here:
http://rocketboards.org/foswiki/Docu...ngStartedYocto

It always failed ubuntu 14.04 with error shown below.
I read somewhere that Ubuntu 12.04 should be use, but version 12.04 seem to be too old for my workstation where the network not working.
Is there anyway to build rootfs for yocto with Ubuntu 14.04 or newer version?

Code:

---

sys_isgpsv@pgisglab028:~/yocto/build$ bitbake altera-gsrd-image
Pseudo is not present but is required, building this first before the main build
WARNING: Host distribution "Ubuntu 14.04.3 LTS" has not been validated with this version of the build system; you may possibly experience unexpected failures. It is recommended that you use a tested distribution.
Loading cache: 100% |##############################################| ETA:  00:00:00
Loaded 1174 entries from dependency cache.
Parsing recipes: 100% |############################################| Time: 00:00:00
Parsing of 882 .bb files complete (857 cached, 25 parsed). 1208 targets, 111 skipped, 0 masked, 0 errors.


Build Configuration:
BB_VERSION        = "1.16.0"
TARGET_ARCH      = "arm"
TARGET_OS        = "linux-gnueabi"
MACHINE          = "socfpga_cyclone5"
DISTRO            = "poky"
DISTRO_VERSION    = "1.3"
TUNE_FEATURES    = "armv7a vfp neon callconvention-hard cortexa9"
TARGET_FPU        = "vfp-neon"
meta
meta-yocto
meta-yocto-bsp
meta-yocto-bsp
meta-altera
meta-linaro      = "<unknown>:<unknown>"


NOTE: Resolving any missing task queue dependencies
NOTE: Preparing runqueue
NOTE: Executing SetScene Tasks
NOTE: Executing RunQueue Tasks
ERROR: Function failed: sysroot_stage_all (see /home/sys_isgpsv/yocto/build/tmp/work/x86_64-linux/quilt-native-0.60-r0/temp/log.do_populate_sysroot.4652 for further information)
ERROR: Logfile of failure stored in: /home/sys_isgpsv/yocto/build/tmp/work/x86_64-linux/quilt-native-0.60-r0/temp/log.do_populate_sysroot.4652
Log data follows:
| DEBUG: Executing python function sstate_task_prefunc
| DEBUG: Python function sstate_task_prefunc finished
| DEBUG: Executing python function do_populate_sysroot
| DEBUG: Executing shell function sysroot_stage_all
| tar: --same-order option cannot be used with -c
| Try 'tar --help' or 'tar --usage' for more information.
| tar: This does not look like a tar archive
| tar: Exiting with failure status due to previous errors
| DEBUG: Python function do_populate_sysroot finished
| ERROR: Function failed: sysroot_stage_all (see /home/sys_isgpsv/yocto/build/tmp/work/x86_64-linux/quilt-native-0.60-r0/temp/log.do_populate_sysroot.4652 for further information)
ERROR: Task 10 (/home/sys_isgpsv/yocto/meta/recipes-devtools/quilt/quilt-native_0.60.bb, do_populate_sysroot) failed with exit code '1'
NOTE: Tasks Summary: Attempted 23 tasks of which 22 didn't need to be rerun and 1 failed.
No currently running tasks (7 of 63)


Summary: 1 task failed:
  /home/sys_isgpsv/yocto/meta/recipes-devtools/quilt/quilt-native_0.60.bb, do_populate_sysroot
Summary: There was 1 WARNING message shown.
Summary: There was 1 ERROR message shown, returning a non-zero exit code.

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MAX 10 Flash programming

May 2, 2017, 3:44 am

≫ Next: Regenerate a new FPGA bin file with different .mif files - from .sof file ?

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Hi,

In MAX 10 FPGA, when the CFM will program ? What are the signals are related to flash ? CONFIG_SEL pin is used to select the CFM0 and CFM1 but, how the process will work ? Please explain if anyone knows.

Thanks in advance.

Regards,
KVL

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Regenerate a new FPGA bin file with different .mif files - from .sof file ?

May 2, 2017, 7:20 am

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Hello,

I have a design (on Stratix3) that contains several .mif files to initialize internal memories .
With a small script I am able to rebuild a new FPGA bin file without doing the full P&R process , see below the commands I use :

> quartus_cdb --update_mif ...
> quartus_asm --read_settings_files=off --write_settings_files=off ....
> quartus_cpf .......

The issue I have is that I have not saved the whole repertory (db and incremental_db) of Quartus for each P&R .. I only saved the project.sof file .
with the above script I understood that the input files used to regenerate the new design file with updated memory content are the ones located in db and incremental_db memories and not the .sof file..

So I was wondering if it was possible to regenerate a design with .mif files modified from the .sof file ?

Thank you for your feedback.

Altera DE0 Board not detected by Windows

May 2, 2017, 11:30 am

≫ Next: How to control the DATA input of a LUT

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Hello everyone.

I am having a problem with my Altera DE0 board and I couldn't find anything to help me out.

My board was functioning normally. Some days ago it completely stopped working with Windows.
Windows does not detect my board when I plug the USB blaster cable in my notebook. The "usb device connected" sound does not happen.
But, if I plug the USB blaster cable to the USB and the FPGA, without using the power source cord, my board powers up normally. The usb cable works like a power source.

The problem is, since this happened, I cannot program anything. Windows does not recognize my board.

Softwares and board I use:
Windows 10 x64
Quartus II 9.1sp2
Altera DE0 board (not the nano)

What I have tried so far:
Plugging the board to another computer: no "usb device connected" sound;
USBdeview: nothing related to the board appears;
Removing the Altera USB-Blaster from device manager: I uninstalled the driver from device manager. Now, windows doesn't detect my board and there is no "installing new driver" when I plug the board to usb.

What I think might have happened:
One day I accidentally turned the board on only using the USB-blaster cable, with no power cord from the source. After this day, my notebook stopped recognizing the board.

Anyone knows any solution to this?

Thanks.



(edit: )
Now I also tested:
->New cable: no response;
->Installed ubuntu 17.04: used "lsusb" and "lsusb|grep Altera" commands, getting no response from the board;
("lsusb" lists all usb devices connected to PC and "lsusb|grep Altera" lists devices with Altera name on it)
-> Reinstalling quartus II 9.1sp2 and still nothing.

How to control the DATA input of a LUT

May 2, 2017, 8:21 pm

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Hi all,

i am using lut_input/lut_output primitives to define a LUT function, and i want to control which DATAx input of LUT is used.
For example, i want to use DATAC input of LUT, but it seems that QII fitter randomly choose a DATA input like DATAD as input port(EP4CE115 with QII14.0).

How can i control the DATA input of a LUT?
The thread (http://www.alteraforum.com/forum/sho...=48731） has the same requirement as me, it seems revising .rcf file may help.
so i generated rcf file and revised 'route_port' in the file correspondingly, please see the following code.

//verilog code
wire ia;
(* keep *)wire combo;
lut_input t1(cnt_rx[0],ia);
lut_output o1(ia,combo);


//original rcf file
branch_point = Label_LOCAL_INTERCONNECT:X76Y23S0I12;
dest = ( combo, DATAA ), route_port = DATAD;

//revised rcf file
branch_point = Label_LOCAL_INTERCONNECT:X76Y23S0I12;
dest = ( combo, DATAA ), route_port = DATAC;



--------------------
QII14.0 gives following info:
Info (170085): Cannot route signal "cnt_rx[0]" to atom "combo"
Info (170097): Routing for this connection is constrained
Info (170098): Error on line number 6752 in Routing Constraints File
Info (170119): To finish routing, the Quartus II software will remove the routing constraints for this fan-out and will make another attempt at routing this fan-out after all other fan-outs of this signal are routed

when i change route_port from DATAD to DATAA, it seems ok and QII choose DATAA as LUT input port as i set, however, when i change route_port from DATAD to DATAB or DATAC, QII will give the messages as above shows.

so do i miss something? or when i change from DATAD to DATAB or DATAC, need i change something else at the same time?

Please help.



ingdxdy

help regarding implementation of md5

May 2, 2017, 11:21 pm

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can someone help me with my md5 code in verilog.

The quartus often doesn't have any response during creating a new project.

May 2, 2017, 11:22 pm

≫ Next: Enabling distributed compilation for Quartus Pro ?

≪ Previous: help regarding implementation of md5

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The operating system I used now is Windows 10 1607 build.

Attached Images

• WeChat Image_20170503142023.jpg (500.0 KB)

Enabling distributed compilation for Quartus Pro ?

May 2, 2017, 11:27 pm

≫ Next: Fitter can't place 1 fractional PLL

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Hi all,

Recently I came across this 'Distributed Compilation' in parellel over multiple machines for Quartus Pro - from one of altera spectra-q marketing document. ( https://www.altera.com/content/dam/a...ckgrounder.pdf, page 3) .

I guess it should need some sort of setup to specific the machine nodes to distribute to ( or izzit not?! ). But I am not where near to get the right info about quartus-pro-userguide.

Anyone know how to enable this ? Or some useful link to read ?

Thanks,
OT

Fitter can't place 1 fractional PLL

May 3, 2017, 12:37 am

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Hi,

we have a Cyclone V SX design that fails to compile because the fitter can't place 1 fractional PLL. I have compiled the design succesfully previously, but after I added two 2-lane HiSPi (LVDS) inputs to design the fitter fails. It seems that the LVDS I/O-banks (5A, 5B ) doesn't have enough PLLs since two PLLs are needed for the LVDS_RX-blocks. Has anybody any ideas how to solve this issue?

Any help appreciated.
Joonas

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A problem with ModelSim.

May 3, 2017, 1:00 am

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Some strange problem with ModelSim.
I open a new project and the next step it should pop up a window for including files in the project. However nothing pops up. Right click -> Add to Project -> Existing File - doesn't work also.

Clear on read register

May 3, 2017, 1:52 am

≫ Next: New on all this! and with and with a Sockit board as heritage!

≪ Previous: A problem with ModelSim.

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hello,

I want to implement a code to handle an external interrupt and in it I want to use a clear on read register.
But, I couldn't find the logic for it.
So, anyone can help me please???

New on all this! and with and with a Sockit board as heritage!

May 3, 2017, 4:45 am

≫ Next: Booting Nios from EPCQ-L does not work with Arria 10

≪ Previous: Clear on read register

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Hello!

I must start by saying that I'm an absolute beginner in all this. Nevertheless, I inherited a Sockit board from an abandoned project that I intend to use to process data from a continuous process.

I tried to start by running some tests to see if the board works. I went over the Getting Started guide but to be honest I'm utterly confused with all the software packages Quartus, Nios II and I find that the examples are not very helpful, for example the 5.4 Running Linux on SoCKit board, seems incomplete, once I access to Linux what answer should I expect from the system?

Could anybody please help me understand what tests can I run to see if the board works?

I really appreciate your help. Regards!

Prietoy

Booting Nios from EPCQ-L does not work with Arria 10

May 3, 2017, 4:53 am

≫ Next: $$$ for your spare BeMicro Max 10 FPGA kits

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Hi,

our hardware is equipped with an EPCQ-L 256 connected to an Arria 10AX048 device (AS x4 mode). For storing the FPGA configuration data and the Nios2 firmware in the EPCQ-L I will use the Quartus programmer and a .jic file. The generation was done with the "Convert file" utility according AN736
(Nios II Processor Booting From Altera Serial Flash). This procedure I have used successfully in Cyclone 5/ EPCQ projects.
But in case of Arria 10 after power cycling the board just the .sof is loaded from EPCQ-L, Nios will not boot. I can run the firmware with the Debugger from Eclipse without problems. Are there any differences between the FPGA families or between EPCQ and EPCQ-L?
Does anyone have used the Serial Flash Controller to boot Nios from EPCQ-L in Arria 10?

regards
Jens

$$$ for your spare BeMicro Max 10 FPGA kits

May 3, 2017, 10:30 am

≫ Next: Connecting the Stratix V FPGA on a Intel based motherboard with windows 8.1

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Aloha all,

I'm part of a start up in Los Angeles, CA, and we are in desperate need of the BeMicro Max 10 FPGA kits, which were recently discontinued.

We are willing to purchase them from you, or even replace them with a newer model if you prefer.

Thank you so much for your help!
Sly