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Connecting the Stratix V FPGA on a Intel based motherboard with windows 8.1

May 3, 2017, 5:59 pm
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Hi,



I am trying to connect the Stratix V GXEAN-01 board to a Motherboard using PCIe on x16 slot. The PC runs windows 8.1. I have already setup Quartus standard edition with license and have visual studio with Open CL support. Do you have a FPGA build ( a hello world program) which is a simple program to test if the FPGA setup works OK or not ? If I connected the FPGA out of the box should the windows enumerate the device on device manager atleast as unknown device?
I do not see any new (unknown or any) device enumerated on the host PC. I can see that some LEDs light up when I turn on the PC and the heat sink on FPGA is running.

Thanks and Best Regards,
Fasi
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Can I use USB-Blaster to debug the Cyclone IV device?

May 3, 2017, 8:49 pm
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Can I use USB-Blaster to debug the Cyclone IV device?
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Access is denied when I save the file.

May 3, 2017, 11:48 pm
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Why do these other designs not fit?

May 4, 2017, 12:48 am
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Dear all,

I've got another question about why designs do not fit on our Arria 10 board . This time, the designs do not overly use resources. I've used --high-effort.

The first kernel has the following top.fit.summary:

Code:
Fitter Status : Failed - Wed May  3 23:08:26 2017
Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Pro Edition
Revision Name : top
Top-level Entity Name : top
Family : Arria 10
Device : 10AX115N3F40E2SG
Timing Models : Final
Logic utilization (in ALMs) : 122,273 / 427,200 ( 29 % )
Total registers : 263614
Total pins : 288 / 826 ( 35 % )
Total virtual pins : 0
Total block memory bits : 4,057,294 / 55,562,240 ( 7 % )
Total RAM Blocks : 501 / 2,713 ( 18 % )
Total DSP Blocks : 770 / 1,518 ( 51 % )
Total HSSI RX channels : 8 / 48 ( 17 % )
Total HSSI TX channels : 8 / 48 ( 17 % )
Total PLLs : 18 / 112 ( 16 % )
The second one has an even smaller footprint, but also does not route:

Code:
Fitter Status : Failed - Thu May  4 00:26:07 2017
Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Pro Edition
Revision Name : top
Top-level Entity Name : top
Family : Arria 10
Device : 10AX115N3F40E2SG
Timing Models : Final
Logic utilization (in ALMs) : 154,248 / 427,200 ( 36 % )
Total registers : 241333
Total pins : 288 / 826 ( 35 % )
Total virtual pins : 0
Total block memory bits : 2,692,686 / 55,562,240 ( 5 % )
Total RAM Blocks : 296 / 2,713 ( 11 % )
Total DSP Blocks : 128 / 1,518 ( 8 % )
Total HSSI RX channels : 8 / 48 ( 17 % )
Total HSSI TX channels : 8 / 48 ( 17 % )
Total PLLs : 18 / 112 ( 16 % )
Why do these designs not fit while they do not use that many resources?

The quartus_sh_compile for both is attached. Can I make these designs route somehow?

Any suggestions welcome!
Thanks in advance!
Attached Files
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Does Seriallite III for Arria10 have programmable pre-emphasis & equalizer settings?

May 4, 2017, 2:11 am
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Hello!
I have looking for a high speed serial communication between multiple FPGAs, and Seriallite fits the bill. I am using an Arria10 development board. Now, the main page for Seriallite III https://www.altera.com/products/inte...riallite3.html says that it has tunable pre-emphasis and equalization settings. I have explored the IP core in QSYS and I am unable to find any options to set the values. I actually don't see any parameters by that name. Even if I click the check boxes with respect to the Transceiver options, no new menu items appear.

In contrast, if I open the Seriallite II IP core (targeting StratixIV), I see the option for setting the pre-emphasis and equalization parameters under Transceiver tab.

It is fine even if Altera fixes the values automatically. I would just like to know if the user can set the values and to ensure that I didn't miss any options.

Thanks,
Divya
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Documentation is confusing about calls and synchronization

May 4, 2017, 2:44 am
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Hello,
I am reading the OpenCL documentation, and I found two major confusing concepts:

1. It is mentionned in page 28 of the Programming Guide that: "for a given kernel, you can only assign one call site per channel ID" (the same for pipes), and then they used many times multiple calls to the same channel and in the same kernel, and even used in loops (page 31 and 33).
Can anyone clarify this detail to me?

2. In the synchronization of pipes (example page 56), why when we use blocking attribute the calls are not ordered, and we need to add fences (mem_fence()), how can the calls be blocking and not ordered in the same time ?
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altera_dma driver for PCIe

May 4, 2017, 6:01 am
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Hi everyone, i'm using an Arria V starter kit for PCIe application and i used the reference design posted in altera wiki. The application software reported success in one PC but not in other with different features. The driver code is installed in two with success but in one, user application reported timeout for read, write and simultaneous RW. Had anyone has the same problem? Have anyone some suggestion about what can i do to try solve this problem?
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VIdeo Color Space Converter IP core

May 4, 2017, 8:03 am
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Hi,

I plan to use Clocked Video Input II + Color Space Converter II + Clocked Video Output II.
I generated these IP cores from Qsys with the associated testbenches.
I tried to simulate the design with modelsim and I noticed that data_out stream of the CVO-II is always XXXXX. Did someone simulate the CVO-II please?

Best regards,

Alexandre
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Continuous signal tap capture?

May 4, 2017, 8:42 am
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Hi,

I am wondering if there is a way to continuously get data from probes in signal tap.

I have explored the mex matlab signal tap functionality in a loop but I lose samples.
I have briefly tried tcp/ip tcl server and signal probes functionality and I lose samples.

Are there double buffering schemes in signal tap?
Do I need to implement my own system (double buffered memory) to not lose samples?
The signal I am hoping to capture continuously is a 16 bit word updating at 56khz.

Thanks!
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Working with MAX3000 family

May 4, 2017, 11:18 am
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Hi!

I need to program some EPM3032 CPLDs.
The bdf file was generated by Quartus version 13, free download. According the warning after compilation, this version doesn´t generate programming files like *.pof and *.jam. I've tried also Quartus 13 web version, unsuccessfully.
The question is:
What can i do to generate programming files?

Best Regards

Joel
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MII TSE Deisgn

May 4, 2017, 12:30 pm
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Hello,

i have a few problems with my TSE design. I want to use MII between the MAC and PHY (DP83848C), which is supported by the IP-Core.
I have successfully set up a communication over RGMII on the DE2-115 board from Terasic with the help of a guide from Altera, "Using Triple-Speed Ethernet on DE2-115 Boards". Now I want to port the system to a DE0-Nano with an external PHY.
I choose GMII/MII in the TSE configuration, I use my code from the DE2-115 board with a few changes for 100MBit mode, the LEDs on the external board are blinking, but I cant receive anything. I think there is something wrong with my PHY initialization, but I don't know what. Is someone here who has a full working setup with the DP83848C over MII? I'm working with Quartus 16.1 and don't use Iniche or something, I want to use the plain C interface like in de guideline from Altera.
If there is something more you want to know, don't be afraid to ask.

Hope for a reply,
Donni
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BSP Editor - Operating System Section only display generic preloader

May 4, 2017, 1:17 pm
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Hello everyone,


I currently have Quartus II and SoC EDS (version 15.0) installed on both windows 7 and Ubuntu 16.04. I noticed when I tried to create a New BSP using the BSP editor under Linux, the Software section under Operating System only displays "Preloader", while on my windows system it shows both "U-Boot SPL Preloader Cyclone V/..." and "U-Boot Bootloader (Arria 10 HP)."

Is there a way to have both the windows options (U-Boot SPL Preloader Cyclone V/... and "U-Boot Bootloader (Arria 10 HP))appear under my linux version of BSP editor?


Thanks for taking the time to read through my question. Any help is appreciated.
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Strange comparator behavior

May 4, 2017, 1:25 pm
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I have a simple comparator project which compares two 2-bit words. I wrote a code, but time diagrams show some strange behavior:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity cmp is
port ( x0, x1, y0, y1, L, E, G : in std_logic;
Lo,Eo,Go : out std_logic);
end cmp;
architecture behav of cmp is
signal LEG: std_logic_vector(0 to 2);
begin
process (x0,x1,y0,y1,L,E,G)
begin
    if x1>y1 then LEG<="001";
    elsif x1<y1 then LEG<="100";
    else
        if x0>y0 then LEG<="001";
        elsif x0<y0 then LEG<="100";
        else
            if G='1' then LEG<="001";
            elsif L='1' then LEG<="100";
            else LEG<="010";
            end if;
        end if;
    end if;
end process;
Lo<=LEG(0); Eo<=LEG(1); Go<=LEG(2);
end behav;

I looked through my code but didn't find a mistake which makes for example "Go" output to fall and rise near the 50th ns. Is it my mistake or maybe Max+Plus II (v.10.0) bug?
Attached Images
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A problem with ModelSim.

May 3, 2017, 1:00 am
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Some strange problem with ModelSim.
I open a new project and the next step it should pop up a window for including files in the project. However nothing pops up. Right click -> Add to Project -> Existing File - doesn't work also.
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Clear on read register

May 3, 2017, 1:52 am
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hello,

I want to implement a code to handle an external interrupt and in it I want to use a clear on read register.
But, I couldn't find the logic for it.
So, anyone can help me please???
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New on all this! and with and with a Sockit board as heritage!

May 3, 2017, 4:45 am
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Hello!

I must start by saying that I'm an absolute beginner in all this. Nevertheless, I inherited a Sockit board from an abandoned project that I intend to use to process data from a continuous process.

I tried to start by running some tests to see if the board works. I went over the Getting Started guide but to be honest I'm utterly confused with all the software packages Quartus, Nios II and I find that the examples are not very helpful, for example the 5.4 Running Linux on SoCKit board, seems incomplete, once I access to Linux what answer should I expect from the system?

Could anybody please help me understand what tests can I run to see if the board works?

I really appreciate your help. Regards!

Prietoy
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Booting Nios from EPCQ-L does not work with Arria 10

May 3, 2017, 4:53 am
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Hi,

our hardware is equipped with an EPCQ-L 256 connected to an Arria 10AX048 device (AS x4 mode). For storing the FPGA configuration data and the Nios2 firmware in the EPCQ-L I will use the Quartus programmer and a .jic file. The generation was done with the "Convert file" utility according AN736
(Nios II Processor Booting From Altera Serial Flash). This procedure I have used successfully in Cyclone 5/ EPCQ projects.
But in case of Arria 10 after power cycling the board just the .sof is loaded from EPCQ-L, Nios will not boot. I can run the firmware with the Debugger from Eclipse without problems. Are there any differences between the FPGA families or between EPCQ and EPCQ-L?
Does anyone have used the Serial Flash Controller to boot Nios from EPCQ-L in Arria 10?

regards
Jens
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$$$ for your spare BeMicro Max 10 FPGA kits

May 3, 2017, 10:30 am
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Aloha all,

I'm part of a start up in Los Angeles, CA, and we are in desperate need of the BeMicro Max 10 FPGA kits, which were recently discontinued.

We are willing to purchase them from you, or even replace them with a newer model if you prefer.

Thank you so much for your help!
Sly
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Connecting the Stratix V FPGA on a Intel based motherboard with windows 8.1

May 3, 2017, 5:59 pm
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0
0
Hi,



I am trying to connect the Stratix V GXEAN-01 board to a Motherboard using PCIe on x16 slot. The PC runs windows 8.1. I have already setup Quartus standard edition with license and have visual studio with Open CL support. Do you have a FPGA build ( a hello world program) which is a simple program to test if the FPGA setup works OK or not ? If I connected the FPGA out of the box should the windows enumerate the device on device manager atleast as unknown device?
I do not see any new (unknown or any) device enumerated on the host PC. I can see that some LEDs light up when I turn on the PC and the heat sink on FPGA is running.

Thanks and Best Regards,
Fasi
↧

Can I use USB-Blaster to debug the Cyclone IV device?

May 3, 2017, 8:49 pm
$
0
0
Can I use USB-Blaster to debug the Cyclone IV device?
↧
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