Question ablout TimeQuest Timing Analyzer

May 8, 2017, 12:51 am

≫ Next: NIOS2 gcc compiler pragma for structure alignment

≪ Previous: Why OpenCL haver specific boards?

Hi, I have a question about the TimeQuest Timing Analyzer. I use Quartus Prime Version 16.1.0. I couldn't find that "TimeQuest Timing Analyzer Wizard" under "Tools" menu. Is there a new way to open it or something else? Does anyone know? Thanks.

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NIOS2 gcc compiler pragma for structure alignment

May 8, 2017, 1:49 am

≫ Next: Help! My Kernal is Panic and He Is Trying to Kill Someone!!

≪ Previous: Question ablout TimeQuest Timing Analyzer

I've tried several variations of #pragma pack(push,1) but the compiler chokes on all of them.

Does anyone know the correct syntax? Or can this only be done with variable attributes?

↧

Help! My Kernal is Panic and He Is Trying to Kill Someone!!

May 8, 2017, 2:19 am

≫ Next: about MAX V open drain output maximum voltage

≪ Previous: NIOS2 gcc compiler pragma for structure alignment

Hi,

It boots fine on DE1 Dev Kit, but not on our PCB, why?

Thanks in advance ,,

Quote:

U-Boot 2013.01.01 (Oct 24 2013 - 17:40:22)

CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
DRAM: 512 MiB
MMC: ALTERA DWMMC: 0
In: serial
Out: serial
Err: serial
Net: mii0
Warning: failed to set MAC address

Hit any key to stop autoboot: 0
reading u-boot.scr
** Unable to read file u-boot.scr **
Optional boot script not found. Continuing to boot normally
reading zImage
3809104 bytes read in 1284 ms (2.8 MiB/s)
reading socfpga.dtb
17119 bytes read in 14 ms (1.2 MiB/s)
fpgaintf
ffd08028: 00000000 ....
fpga2sdram
ffc25080: 00000000 ....
axibridge
ffd0501c: 00000000 ....
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x00000100
Loading Device Tree to 03ff8000, end 03fff2de ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Initializing cgroup subsys cpuset
Linux version 3.12.0-00307-g507abb4-dirty (root@matthew) (gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-57) ) #2 SMP Mon Jan 6 19:54:56 CST 2014
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Altera SOCFPGA, model: Altera SOCFPGA Cyclone V
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 8 pages/cpu @80bcf000 s11328 r8192 d13248 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048
Kernel command line: console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 511692K/524288K available (5637K kernel code, 253K rwdata, 1424K rodata, 343K init, 256K bss, 12596K reserved)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xa0800000 - 0xff000000 (1512 MB)
lowmem : 0x80000000 - 0xa0000000 ( 512 MB)
modules : 0x7f000000 - 0x80000000 ( 16 MB)
.text : 0x80008000 - 0x806ed828 (7063 kB)
.init : 0x806ee000 - 0x80743c40 ( 344 kB)
.data : 0x80744000 - 0x807834f0 ( 254 kB)
.bss : 0x807834f0 - 0x807c355c ( 257 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
Hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 42949ms
Console: colour dummy device 80x30
Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
ftrace: allocating 17704 entries in 52 pages
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x8051f018 - 0x8051f070
CPU1: failed to come online
Brought up 1 CPUs
SMP: Total of 1 processors activated.
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
NET: Registered protocol family 16
fpga bridge driver
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410030c9, AUX_CTRL 0x32460000, Cache size: 512 kB
syscon fffef000.l2-cache: regmap [mem 0xfffef000-0xfffeffff] registered
syscon ffd05000.rstmgr: regmap [mem 0xffd05000-0xffd05fff] registered
syscon ffc25000.sdrctl: regmap [mem 0xffc25000-0xffc25fff] registered
syscon ff800000.l3regs: regmap [mem 0xff800000-0xff800fff] registered
syscon ffd08000.sysmgr: regmap [mem 0xffd08000-0xffd0bfff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
altera_hps2fpga_bridge fpgabridge.2: fpga bridge [hps2fpga] registered as device hps2fpga
altera_hps2fpga_bridge fpgabridge.2: init-val not specified
altera_hps2fpga_bridge fpgabridge.3: fpga bridge [lshps2fpga] registered as device lwhps2fpga
altera_hps2fpga_bridge fpgabridge.3: init-val not specified
altera_hps2fpga_bridge fpgabridge.4: fpga bridge [fpga2hps] registered as device fpga2hps
altera_hps2fpga_bridge fpgabridge.4: init-val not specified
bio: create slab <bio-0> at 0
FPGA Mangager framework driver
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Switched to clocksource timer1
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with ARMv7 Cortex-A9 PMU driver, 7 counters available
arm-pmu arm-pmu: PMU:CTI successfully enabled
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/W].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
msgmni has been set to 999
io scheduler noop registered (default)
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
ffc02000.serial0: ttyS0 at MMIO 0xffc02000 (irq = 194, base_baud = 6250000) is a 16550A
console [ttyS0] enabled
altera_fpga_manager ff706000.fpgamgr: fpga manager [Altera FPGA Manager] registered as minor 0
brd: module loaded
cadence-qspi ff705000.spi: DMA NOT enabled
cadence-qspi ff705000.spi: master is unqueued, this is deprecated
m25p80 spi2.0: unrecognized JEDEC id ffffff
cadence-qspi ff705000.spi: Cadence QSPI controller driver
dw_spi_mmio fff01000.spi: master is unqueued, this is deprecated
CAN device driver interface
c_can_platform ffc00000.d_can: invalid resource
c_can_platform ffc00000.d_can: control memory is not used for raminit
c_can_platform ffc00000.d_can: c_can_platform device registered (regs=a08e4000,
stmmac - user ID: 0x10, Synopsys ID: 0x37
Ring mode enabled
DMA HW capability register supported
Enhanced/Alternate descriptors
Enabled extended descriptors
RX Checksum Offload Engine supported (type 2)
TX Checksum insertion supported
Enable RX Mitigation via HW Watchdog Timer
libphy: stmmac: probed
eth0: PHY ID 00221611 at 4 IRQ 0 (stmmac-0:04) active
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
Synopsys Designware Multimedia Card Interface Driver
dwmmc_socfpga ff704000.dwmmc0: Using internal DMA controller.
dwmmc_socfpga ff704000.dwmmc0: Version ID is 240a
dwmmc_socfpga ff704000.dwmmc0: DW MMC controller at irq 171, 32 bit host data wi
mmc_host mmc0: Bus speed (slot 0) = 12500000Hz (slot req 400000Hz, actual 390625
dwmmc_socfpga ff704000.dwmmc0: 1 slots initialized
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
dwmmc_socfpga ff704000.dwmmc0: data FIFO error (status=00000800)
mmc0: problem reading SD Status register.
mmc_host mmc0: Bus speed (slot 0) = 12500000Hz (slot req 12500000Hz, actual 1250
mmc0: new high speed SDHC card at address aaaa
mmcblk0: mmc0:aaaa SS08G 7.40 GiB
mmcblk0: p1 p2 p3
dwc2 ffb40000.usb: DWC OTG Controller
dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1
dwc2 ffb40000.usb: irq 160, io mem 0x00000000
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: DWC OTG Controller
usb usb1: Manufacturer: Linux 3.12.0-00307-g507abb4-dirty dwc2_hsotg
usb usb1: SerialNumber: ffb40000.usb
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
oprofile: using arm/armv7-ca9
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
8021q: 802.1Q VLAN Support v1.8
Key type dns_resolver registered
ThumbEE CPU extension supported.
Registering SWP/SWPB emulation handler
kjournald starting. Commit interval 5 seconds
EXT3-fs (mmcblk0p2): using internal journal
EXT3-fs (mmcblk0p2): recovery complete
EXT3-fs (mmcblk0p2): mounted filesystem with ordered data mode
VFS: Mounted root (ext3 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 340K (806ee000 - 80743000)
Unhandled fault: imprecise external abort (0x1406) at 0x76f9a87c
Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007

CPU: 0 PID: 1 Comm: init Not tainted 3.12.0-00307-g507abb4-dirty #2
[<80017e0c>] (unwind_backtrace+0x0/0x104) from [<80013604>] (show_stack+0x20/0x2
[<80013604>] (show_stack+0x20/0x24) from [<8051a3b4>] (dump_stack+0x78/0x90)
[<8051a3b4>] (dump_stack+0x78/0x90) from [<80517358>] (panic+0xac/0x204)
[<80517358>] (panic+0xac/0x204) from [<80027a38>] (do_exit+0x8a8/0x968)
[<80027a38>] (do_exit+0x8a8/0x968) from [<80027c4c>] (do_group_exit+0x4c/0xd4)
[<80027c4c>] (do_group_exit+0x4c/0xd4) from [<80036710>] (get_signal_to_deliver+
[<80036710>] (get_signal_to_deliver+0x26c/0x67c) from [<800127a8>] (do_signal+0x
[<800127a8>] (do_signal+0x88/0x3ac) from [<80012e38>] (do_work_pending+0x74/0xbc
[<80012e38>] (do_work_pending+0x74/0xbc) from [<8000ee40>] (work_pending+0xc/0x2

↧

about MAX V open drain output maximum voltage

May 8, 2017, 3:53 am

≫ Next: communication using rs232 to pc

≪ Previous: Help! My Kernal is Panic and He Is Trying to Kill Someone!!

Hi,

Where can I find info about MAX V open drain output max. voltage value?
Can I drive directy LED ( 3,2V drop voltage at 10 mA) from MAX V open drain output if the LED Anode connected to the +5V power supplier via 150 Ohm resistor ( I assume the output transistor sauraion votage's 0,4V as datasheet says).?
During LED off state 5V will be applied to the output transistor drain. Is it OK?

BR

↧

communication using rs232 to pc

May 5, 2017, 4:35 am

≫ Next: rs232 uart ip :: user guide

≪ Previous: about MAX V open drain output maximum voltage

hi,

i am using an cyclone 5 soc development kit. i programmed fpga and design is running fine. my result is storing in an 45 bit register in fpga @ of 200 hz. i need to transfer these values to my pc. ( i am using quartus)

so i decided to use an rs232 uart from quartus & embedded command shell as software in pc. but problem is there is no user manual for this rs 232 ip.so can anybody please help me on this, how to use this rs-2332 ip (any document or demo program )?
any help is really appriciated :)

Code:

// unnamed.v



// Generated using ACDS version 16.0 211





`timescale 1 ps / 1 ps

module unnamed (

        input  wire        address,    // avalon_rs232_slave.address

        input  wire        chipselect, //                   .chipselect

        input  wire [3:0]  byteenable, //                   .byteenable

        input  wire        read,       //                   .read

        input  wire        write,      //                   .write

        input  wire [31:0] writedata,  //                   .writedata

        output wire [31:0] readdata,   //                   .readdata

        input  wire        clk,        //                clk.clk

        input  wire        UART_RXD,   // external_interface.RXD

        output wire        UART_TXD,   //                   .TXD

        output wire        irq,        //          interrupt.irq

        input  wire        reset       //              reset.reset

    );





    unnamed_rs232_0 rs232_0 (

        .clk        (clk),        //                clk.clk

        .reset      (reset),      //              reset.reset

        .address    (address),    // avalon_rs232_slave.address

        .chipselect (chipselect), //                   .chipselect

        .byteenable (byteenable), //                   .byteenable

        .read       (read),       //                   .read

        .write      (write),      //                   .write

        .writedata  (writedata),  //                   .writedata

        .readdata   (readdata),   //                   .readdata

        .irq        (irq),        //          interrupt.irq

        .UART_RXD   (UART_RXD),   // external_interface.export

        .UART_TXD   (UART_TXD)    //                   .export

    );





endmodule

above one is the uart ip module, in this they didnt provide any information regarding all signals lke chipselect,byteenable,read,write....

one more doubt is :: is this the correct way of doing this?

inside my fpga there is arm processor. anybody here knows how to do this please share some information about it :)

thanks and regards

↧

rs232 uart ip :: user guide

May 8, 2017, 6:05 am

≫ Next: Quartus Prime Standard 15.1 - Missing Arria 10 compatible IP in Catalog

≪ Previous: communication using rs232 to pc

hi,

Code:

// unnamed.v



// Generated using ACDS version 16.0 211





`timescale 1 ps / 1 ps

module unnamed (

                input  wire        address,    // avalon_rs232_slave.address

                input  wire        chipselect, //                   .chipselect

                input  wire [3:0]  byteenable, //                   .byteenable

                input  wire        read,       //                   .read

                input  wire        write,      //                   .write

                input  wire [31:0] writedata,  //                   .writedata

                output wire [31:0] readdata,   //                   .readdata

                input  wire        clk,        //                clk.clk

                input  wire        UART_RXD,   // external_interface.RXD

                output wire        UART_TXD,   //                   .TXD

                output wire        irq,        //          interrupt.irq

                input  wire        reset       //              reset.reset

        );





        unnamed_rs232_0 rs232_0 (

                .clk        (clk),        //                clk.clk

                .reset      (reset),      //              reset.reset

                .address    (address),    // avalon_rs232_slave.address

                .chipselect (chipselect), //                   .chipselect

                .byteenable (byteenable), //                   .byteenable

                .read       (read),       //                   .read

                .write      (write),      //                   .write

                .writedata  (writedata),  //                   .writedata

                .readdata   (readdata),   //                   .readdata

                .irq        (irq),        //          interrupt.irq

                .UART_RXD   (UART_RXD),   // external_interface.export

                .UART_TXD   (UART_TXD)    //                   .export

        );





endmodule

doccument::ftp://66.35.227.3/up/pub/Altera_Mate...ions/RS232.pdf

above one is an rs_232 uart ip provided by quartus(generated by qusy).but i am not able to find an user manual for it..so i dont know how can i assign value to 32 bit input register. actual value is only 8 bits what should i do with rest of the bits??
i also dont know chipselect, address & byteenale values ?
can anybody help me on this? anyhere please tell me how to use it.
any help is really appriciated

thanks and regards

↧

Quartus Prime Standard 15.1 - Missing Arria 10 compatible IP in Catalog

May 8, 2017, 6:56 am

≫ Next: Export bsf to jpg

≪ Previous: rs232 uart ip :: user guide

Hi all,

I have just installed Quartus prime standard 15.1 and am starting a project using an Arria 10 board. I need to use the IP catalog (for PLLs specifically) but there is no IP compatible with the Arria 10 for some reason. The project was previously based on a Cyclone V FPGA on the lite edition but I have changed the device settings. All the other IP for other devices are available. Any ideas as to what's wrong??

Dáire.

↧

Export bsf to jpg

May 8, 2017, 10:01 am

≫ Next: Quartus runs but the GUI doesn't open or show

≪ Previous: Quartus Prime Standard 15.1 - Missing Arria 10 compatible IP in Catalog

When I Export schematic or bsf file to a .jpg or .bmp file the left side of the jpg or bmp is always cut off so that the left side 1 inch is always missing.
I'm using the export to jpg/bmp because File Print Preview only seems to utilize about 1/4 of the available paper - there seems to be no way to
print the extents of the schematic/bsf file i.e. to utilize all the paper size available. I'd like to be able to print to a tabloid sheet which I can do
however, the printed image is way smaller then it should be.
Currently using Quartus Lite, version 15.1

↧

Quartus runs but the GUI doesn't open or show

May 8, 2017, 3:32 pm

≫ Next: Transceiver data passthrough without jitter (Cyclone IV)

≪ Previous: Export bsf to jpg

I freshly downloaded Quartus Lite 17.0 and have installed it on my laptop with Windows 10. Previous versions of Quartus seem to have ran fine but this version doesn't. When I try and open Quartus, the process runs and consumes massive amount of computer resources (maxing out a core and using a ton of RAM) but the GUI never seems to show. I've tried opening after a fresh restart (first program to be ran) along with leaving it running for a few hours but with no successful results. Any reasons for why this could be?

Thanks
Edit: For reasons completely unknown to me, after I opened the Quartus Programmer, Quartus decided to open! I'm unsure to the reasoning for this but this solves my problem. Sorry to waste your time!

↧

Transceiver data passthrough without jitter (Cyclone IV)

May 9, 2017, 12:46 am

≫ Next: Read/Write data to SDRAM on DE0 nano using NIOS ii

≪ Previous: Quartus runs but the GUI doesn't open or show

Hello,
I need to transfer data through some number of FPGAs (Cyclone IV, 2.5GHz, 16-bit words at 125MHz) without jitter at 125 MHz in order to have 1 clock domain in the fpgas connected together in line. Is there are any possible ways to use RX recovered clock from the receiver as TX clock for transievers? The compiler does not allow to do it (I cannot connect RX clock to the inclk). I cannot use cross clock domains inside FPGA (FIFOs, etc.) as the overall jitter becomes very big by the end point in he net.

↧

Read/Write data to SDRAM on DE0 nano using NIOS ii

May 9, 2017, 1:11 am

≫ Next: device_handler_thread_main: Assertion `args && args->func_name' failed

≪ Previous: Transceiver data passthrough without jitter (Cyclone IV)

I'm trying to access(read/write) the SDRAM on DE0 nano board using NIOS ii system.
What I have done so far is,
1. I build a NIOS processor with an onchip memory.
2. Build an SDRAM controller using Qsys and connected that with the NIOS system.
3. wrote a program to read/write data to corresponding data/address lines in SDRAM controller.

I'm having an issue that, I write data to a some given address when I read back that write data is present in every address. I think memory addressing is wrong.

How can I fix this?
Is there any another approach to Read/Write data from SDRAM??

What I want is read/write data to SDRAM using NIOS, I don't want to use SDRAM in NIOS system instead of onchip.

my top module bdf file (as an image) attached with this.

Attached Files

SDRAMTEST_2_TopModule.bdf.pdf (1.83 MB)

↧

device_handler_thread_main: Assertion `args && args->func_name' failed

May 9, 2017, 1:11 am

≫ Next: Migrating Xilinx Project to Arria 10

≪ Previous: Read/Write data to SDRAM on DE0 nano using NIOS ii

I use mutilthread in my opencl code. When run in emulator mode, code run successfully. But when run in FPGA, and excute to "clWaitForEvents()" function, it abort and show:

"cnn: acl_hal_mmd.c:218: device_handler_thread_main: Assertion `args && args->func_name' failed" .

Anybody know why? Thank you!

↧

Migrating Xilinx Project to Arria 10

May 9, 2017, 5:26 am

≫ Next: On-Chip Memory instruction corruption

≪ Previous: device_handler_thread_main: Assertion `args && args->func_name' failed

I am currently moving a large virtex 6 based project over to an Arria 10 board, which includes Xilinx specific IO module instances such as IBUFG, OBUFDS, IOBUF, and ODDR, and am new to Quartus environment. Is there an Altera / Quartus Equivalent of these IO cells and how do I instantiate them ??

↧

On-Chip Memory instruction corruption

May 9, 2017, 7:12 am

≫ Next: not random at each execution

≪ Previous: Migrating Xilinx Project to Arria 10

We have a design which uses a NIOS CPU whose instruction code is stored in On-Chip Memory. Most of the time everything works however there are times when the code is changed slightly and either the firmware consistently jumps to the beginning of the code or the code appears to freeze. This happens even when we add code that has no functional application to the system (e.g. adding debug lines to the code). We have checked the size of the memory and the size of the code and there is more the ample space for the stack. Also we have compared the contents of the Flash in which the code is stored to the code that is copied into the On Chip Memory and they are identical.

Does anyone have any ideas where we should start our debug ?

↧

not random at each execution

May 9, 2017, 7:16 am

≫ Next: University Program VWF does not work

≪ Previous: On-Chip Memory instruction corruption

Hi all,

I have a problem with generating a random from the uniform function, it is always the same with each execution of the process.

I have attached a piece of code to the testbench.
If someone gets to see where it's wrong. Thank you

Attached Images

test.jpg (20.8 KB)

↧

University Program VWF does not work

May 9, 2017, 9:16 am

≫ Next: USB Blaster II will program but not verify, but USB Blaster will....

≪ Previous: not random at each execution

. Prime Lite Edition as well as the licensed versions that we are currently using in the labs the University Program VWF do not work it gives an error that reads as follows:
**** Running the ModelSim simulation ****
c:/intelfpga_lite/16.1/modelsim_ae/win32aloem//vsim -c -do trishelle.do
Unable to checkout a license. Vsim is closing.
** Fatal: Invalid license environment. Application closing.
Unable to checkout a license. Make sure your license file environment variables are set correctly and then run 'lmutil lmdiag' to diagnose the problem.
Modelsim - Intel FPGA Edition uses the following environment variables to check the licenses (listed in the order of preference)
1. MGLS_LICENSE_FILE
2. LM_LICENSE_FILE.

Error.

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USB Blaster II will program but not verify, but USB Blaster will....

May 9, 2017, 12:14 pm

≫ Next: Downloading images through System Console

≪ Previous: University Program VWF does not work

I have both the USB Blaster and USB Blaster II. We've been using the Blaster II due to the faster programming speeds. But for some reason I cannot get multiple different and similar boards to program/verify with the USB Blaster II anymore. I've changed the clock speeds using the jtagconfig --setparam 1 JtagClock 6M command however it doesn't work. I've tried the following clock speeds 500k, 1M, 6M and 16M.

I can program and it will work. "Programmer Operation was Successful"

However, when I program/verify, I get "Verification Failed for Device number 1"

Any thoughts?

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Downloading images through System Console

May 9, 2017, 12:54 pm

≫ Next: sharing of local_memory between Work Items on SoC FPGA (Cyclone V)

≪ Previous: USB Blaster II will program but not verify, but USB Blaster will....

I have a design that works with the Arria 10 GX eval board. I use a dashboard in the System Console to interact with my design. Within the dashboard I have a combo box and a button that allow me to select a sof image and to download it to the board. The following is the code attached to the download button:

proc btnDownloadClick { } {
global dash
global my_device

set filename [file join output_files [dashboard_get_property $dash cboImage selectedItem]]

foreach possible_device [ get_service_paths device ] {
if { [ regexp 10AT115 $possible_device ] } {
set my_device $possible_device
}
}
puts "Download: device=$my_device filename=$filename"
device_download_sof $my_device $filename
}

When I first launch System Console and load my script I am able to download an image with no problems and then to interact with the design through other elements in the dashboard. However, when I attempt to load a new image I get the following error and I have to restart System Console before I can download a new image.

May 09, 2017 2:53:28 PM com.altera.debug.core
SEVERE: device_download_sof: This device does not have a JTAG connection

May 09, 2017 2:53:28 PM com.altera.debug.core
SEVERE: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
java.util.concurrent.ExecutionException: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
at com.altera.systemconsole.internal.core.SimpleFutur e$Sync.innerGet(SimpleFuture.java:208)
at com.altera.systemconsole.internal.core.SimpleFutur e.getInternal(SimpleFuture.java:88)
at com.altera.systemconsole.internal.core.SimpleFutur e.get(SimpleFuture.java:61)
at com.altera.systemconsole.dashboard.internal.System ConsoleDashboard$TCLDashboard$1$1.run(SystemConsol eDashboard.java:70)
at com.altera.systemconsole.internal.core.SystemExecu tor$2.run(SystemExecutor.java:306)
at com.altera.systemconsole.internal.core.SystemExecu tor$4.run(SystemExecutor.java:553)
at com.altera.systemconsole.internal.core.SystemExecu tor$ComparableTask.run(SystemExecutor.java:151)
at java.util.concurrent.ThreadPoolExecutor.runWorker( Unknown Source)
at java.util.concurrent.ThreadPoolExecutor$Worker.run (Unknown Source)
at java.lang.Thread.run(Unknown Source)
Caused by: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
at com.altera.systemconsole.scripting.ScriptEngine$5. run(ScriptEngine.java:589)
at com.altera.tcl.interpreter.NativeTclWrapper.runEve nt(NativeTclWrapper.java:341)
at com.altera.tcl.interpreter.NativeTclWrapper.doOneE vent0(Native Method)
at com.altera.tcl.interpreter.NativeTclWrapper.doOneE vent(NativeTclWrapper.java:355)
at com.altera.tcl.interpreter.NativeTCLInterpreter.wa itAndDoOneEvent(NativeTCLInterpreter.java:436)
at com.altera.tcl.interpreter.InterpreterInstantiator $1.run(InterpreterInstantiator.java:59)
... 1 more

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sharing of local_memory between Work Items on SoC FPGA (Cyclone V)

May 9, 2017, 12:54 pm

≫ Next: Downloading images through System Console

≪ Previous: Downloading images through System Console

According to OpenCL ,
1. __local address space inside a __kernel function are allocated for each work-group executing the kernel.
2. variables that need to be allocated in local memory and are shared by all work-items of a work-group.

for the following kernel code for image of 512 *512 pixels

#define W 512
#define H 512
#define global_size_x 512
#define global_size_y 512
#define local_size_x 512
#define local_size_y 1

__attribute__((reqd_work_group_size(local_size_x,l ocal_size_y,1))) //dimensions

__kernel void sobel_kernel (__global unsigned char * restrict image_in,
__global unsigned char * restrict image_out)

{
__local int n;
int sum;

//Index of the pixel
__private short int row_id = get_global_id(1);
__private short int col_id = get_local_id(0);

sum = image_in[(row_id )*W + (col_id )] ; //read global to local
n=n+1; //update local value

barrier (CLK_GLOBAL_MEM_FENCE);
barrier(CLK_LOCAL_MEM_FENCE);

if((row_id <10) && (col_id <10))
printf("\n%d",n); //observe local value

//global mem write transaction
image_out[(row_id)*W + (col_id) ] = sum;
}

the above kernel when compiled on
1. emulator in linux (default s5_ref board) the output printed for n was n = 1 2 3 4 5.....
2. but when I compiled the kernel with Intel FPGA SDK and deployed .aocx file on the Cyclone V SoC FPGA the values for n were always 1 1 1 1 1...../

Can someone explain why the local variable declared doesn't have scope for all the work items in the work group.
and why emulator and FPGA may show different results.

Thanks

↧

Downloading images through System Console

May 9, 2017, 8:24 am

≫ Next: DDR3 Memory Calibration Fails for Cyclone V - EMIF Toolkit Error

≪ Previous: sharing of local_memory between Work Items on SoC FPGA (Cyclone V)

I am working with the Arria 10 GX eval board and have created a dashboard in System Console to allow me to control my design. My dashboard has a combo box to allow me to select from a list of sof files and a button to allow me to download the selected image. The following is the code attached to the button:

proc btnDownloadClick { } {
global dash
global my_device

set filename [file join output_files [dashboard_get_property $dash cboImage selectedItem]]

foreach possible_device [ get_service_paths device ] {
if { [ regexp 10AT115 $possible_device ] } {
set my_device $possible_device
}
}
device_download_sof $my_device $filename
}

When I first open System Console this code works as expected. I can then use System Console to interact with my design. If I then attempt to download a new image, I get the following error message. I have to exit and restart System Console before I can download a new image.

=== error message follows ===

May 09, 2017 10:18:39 AM com.altera.debug.core
SEVERE: device_download_sof: This device does not have a JTAG connection

May 09, 2017 10:18:39 AM com.altera.debug.core
SEVERE: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
java.util.concurrent.ExecutionException: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
at com.altera.systemconsole.internal.core.SimpleFutur e$Sync.innerGet(SimpleFuture.java:208)
at com.altera.systemconsole.internal.core.SimpleFutur e.getInternal(SimpleFuture.java:88)
at com.altera.systemconsole.internal.core.SimpleFutur e.get(SimpleFuture.java:61)
at com.altera.systemconsole.dashboard.internal.System ConsoleDashboard$TCLDashboard$1$1.run(SystemConsol eDashboard.java:70)
at com.altera.systemconsole.internal.core.SystemExecu tor$2.run(SystemExecutor.java:306)
at com.altera.systemconsole.internal.core.SystemExecu tor$4.run(SystemExecutor.java:553)
at com.altera.systemconsole.internal.core.SystemExecu tor$ComparableTask.run(SystemExecutor.java:151)
at java.util.concurrent.ThreadPoolExecutor.runWorker( Unknown Source)
at java.util.concurrent.ThreadPoolExecutor$Worker.run (Unknown Source)
at java.lang.Thread.run(Unknown Source)
Caused by: java.lang.Exception: device_download_sof: This device does not have a JTAG connection
while executing
"device_download_sof $my_device $filename"
(procedure "btnDownloadClick" line 13)
invoked from within
"btnDownloadClick"
at com.altera.systemconsole.scripting.ScriptEngine$5. run(ScriptEngine.java:589)
at com.altera.tcl.interpreter.NativeTclWrapper.runEve nt(NativeTclWrapper.java:341)
at com.altera.tcl.interpreter.NativeTclWrapper.doOneE vent0(Native Method)
at com.altera.tcl.interpreter.NativeTclWrapper.doOneE vent(NativeTclWrapper.java:355)
at com.altera.tcl.interpreter.NativeTCLInterpreter.wa itAndDoOneEvent(NativeTCLInterpreter.java:436)
at com.altera.tcl.interpreter.InterpreterInstantiator $1.run(InterpreterInstantiator.java:59)
... 1 more

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