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DDR3 Memory Calibration Fails for Cyclone V - EMIF Toolkit Error

May 9, 2017, 3:05 pm
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I'm currently using a custom board with 5CEFA9F31C7N Cyclone V E FPGA chip and Alliance AS4C512M16D3L DDR3 8GB with 1.5V on Quartus II 13.1.

After setting up my timing constraints and generated an IP through MegaWizard, I SignalTapped my local calibrations that resulted with calibrations failed.

After reading through
https://www.altera.com/content/dam/a...if_toolkit.pdf
I know that the EMIF Toolkit can be useful in determining what stage the calibration failed to narrow down the culprit. Is this available for the Cyclone V E?

Page 11 states:
"The UniPHY External Memory Interface Debug Toolkit and EMIF On-Chip Debug Toolkit do not workwith Arria V and Cyclone V SoC devices. Debugging information for Arria V and Cyclone V SoC devicesis available by enabling a debug output report, which contains similar information."

My chip is not an SoC so it would work correct?

I compiled my project (Analysis & Synthesis, ran .tcl scripts for pin assignments, map, and timing, Fitter, then Full Compile), programmed the board and proceeded to start up the toolkit, only to have it timeout on the "Initialize Connections" task. Any insight on this?

I also used the Cyclone V GT Development Kit and was able to calibrate the DDR3 memory on that device with no issues with read/write functionalities. However, Toolkit would still timeout after a few minutes on "Initialize Connections".

-Steve
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Register using component and port maps

May 9, 2017, 3:25 pm
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Hi, I am building a 32 bit register using a 8-bit register as a component. However, I am stuck at port mapping the 8-bit register correctly, any tips/help would be appreciated.

my code so far:

----BITSTORAGE----
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity bitstorage is
port(bitin: in std_logic;
enout: in std_logic;
writein: in std_logic;
bitout: out std_logic);
end entity bitstorage;
architecture memlike of bitstorage is
signal q: std_logic := '0';
begin
process(writein) is
begin
if (rising_edge(writein)) then
q <= bitin;
end if;
end process;

bitout <= q when enout = '0' else 'Z';
end architecture memlike;
--------------------------------------------------------------------------------

----8-BIT REGISTER----

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity register8 is
port(datain: in std_logic_vector(7 downto 0);
enout: in std_logic;
writein: in std_logic;
dataout: out std_logic_vector(7 downto 0));
end entity register8;
architecture memmy of register8 is
component bitstorage
port(bitin: in std_logic;
enout: in std_logic;
writein: in std_logic;
bitout: out std_logic);
end component;
begin
c0: bitstorage port map(datain(0),enout,writein,dataout(0));
c1: bitstorage port map(datain(1),enout,writein,dataout(1));
c2: bitstorage port map(datain(2),enout,writein,dataout(2));
c3: bitstorage port map(datain(3),enout,writein,dataout(3));
c4: bitstorage port map(datain(4),enout,writein,dataout(4));
c5: bitstorage port map(datain(5),enout,writein,dataout(5));
c6: bitstorage port map(datain(6),enout,writein,dataout(6));
c7: bitstorage port map(datain(7),enout,writein,dataout(7));
end architecture memmy;

--------------------------------------------------------------------------------

---32-BIT REGISTER---
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
entity register32 is
port(datain: in std_logic_vector(31 downto 0);
enout32,enout16,enout8: in std_logic;
writein32, writein16, writein8: in std_logic;
dataout: out std_logic_vector(31 downto 0));
end entity register32;
architecture biggermem of register32 is
component register8
port(datain: in std_logic_vector(7 downto 0);
enout: in std_logic;
writein: in std_logic;
dataout: out std_logic_vector(7 downto 0));
end component;
begin
Implementing port map here

end architecture biggermem;
----------------------------------------------------
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Why does one single load/store consume much RAMs?

May 9, 2017, 4:33 pm
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Hi,
when I design OpenCL and run aocl, it reports that one single load consume 13 RAMs and one single store consume 16 RAMs.

e.g
__kernel void top_kernel(__global restrict volatile int *a, __global restrict volatile int *b, __global restrict volatile int *c) {
int i;
for (i = 0; i < 10000; ++i)
c[i] = a[i] + b[i]; // it will consume 13x2 + 16 RAMs
}
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Ethernet data stream from HPS On-Chip RAM

May 9, 2017, 11:58 pm
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Hello!


Has anyone managed to send the data stream from HPS On-Chip RAM in Linux using Ethernet? Does the Altera's Ethernet driver supports this? Or does the data must be in the HPS SDRAM?


-Joonas
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altremote IP usage on cyclone IV E

May 10, 2017, 1:33 am
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Hi,

I want to use the altremote IP (Altera remote update) on a cyclone IV E system. An FPGA attached SPI flash contains a factory and an application
image (addresses 0 and 0x80000).

The factory image boots fine. The design uses a qsys component that has several IPs on the avalon bus. One of these is the altremote IP.
I can read/write all IPs just fine except the altremote core. I would expect that I can readback the bootaddress from address offset 0x10
after writing 0x80000 to this reg. But I only get back 0 on every register.

The altremote IP is configure with "Add support for writing configuration parameters" and "Add support for Avalon Interface".

What is the problem? Why is read/write to the bootaddress reg not possible?

The IP userguide mentions fmax=20Mhz for Cyclone IV. What's this fmax? Avalon clock in my case?

All IP register addresses are 32bit aligned, except the RECONFIG register (0x1d). Is this by intention? So I nee to do a byte access
to this unaligned address?

Quartus version is 16.1.

Regards,
Matthias
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OpenCL Library Design Example

May 10, 2017, 3:08 am
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In example 2,the "copyElement" file contains of several modules . I don't know the module's function respectively.Anyone can help me?
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QSYS use relative IP Search Path

May 10, 2017, 7:36 am
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I have some IP components located in my local directory structure. I can manually add a hard coded IP Search Path and everything works fine. I cannot figure out how to make this search path relative to my project file. Any help?
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SRAM DE2 - Problem

May 10, 2017, 7:53 am
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I try use SRAM on de2 board with sram controller from IP core's altera, i face the problem which read a data from location , i get the result with all HIGH (0xFFFF). Help me!
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Quartus Compile Design text immediately reverts to yellow

May 10, 2017, 9:59 am
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I am experiencing a strange problem in Quartus Prime. It has to deal with the "Compile Design" text automatically reverting back to yellow immediately after the "Compile Design" sequence has completed. This problem seems to occur whenever I have "regenerated" a QSYS block, but have not closed and reopened Quartus.

Here is an example of it not happening:
Step 1) Open Quartus Prime
Step 2) Open QSYS
Step 3) Regenerate QSYS
Step 4) Close QSYS
Step 5) Close Quartus Prime
Step 6) Reopen Quartus Prime
Step 7) "Compile Design" --> Text transitions from yellow to green as each step completes. When "Compile Design" is complete, the text stays green.

Here is an example of it happening:
Step 1) Open Quartus Prime
Step 2) Open QSYS
Step 3) Regenerate QSYS
Step 4) Close QSYS
Step 4) "Compile Design" -> Text transitions from yellow to green as each step completes. When "Compile Design" is complete, all text reverts back to yellow.

Any ideas why this is happening and how to get it to stop? We are planning on having a TCL script regenerate QSYS every time, but would also like to see green in the end.
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Configuring IO on Cyclone V after boot

May 10, 2017, 1:55 pm
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Hello Community,

I want to configure specific pins (the spim0 pins) on my Cyclone V device (SoCrates Board) without using the Preloader(!) to be inputs without pull-up,
so I can't use Qsys for this - correct me if I'm wrong.

I already found the registers for muxing the pins as GPIOs and also the registers to set the GPIO config (in/out, pull-up, etc),
i know I have to take the GPIO Controller out of reset, too - I read the chapters in the Cyclone V Device Handbook.
Writing the code for this should be easy.

What I'm concerned about is: I don't understand the IO Configuration sequence

Next to the registers I have to write to, to config the pins, there is a NOTE in the Device Handbook:
NOTE: These registers should not be modified after IO configuration.There is nosupport for dynamically changing the Pin Mux selections

So my question turns out to be: When is the right time to configure the pin mux selections and how can I make my code run at the right moment?
Currently I'm trying to do this after the device fully booted (in my case only the BootROM ran, no SPL/Preloader) by running my code directly from ARM DS 5.

Some hints in the right direction should be enough.

Thankful,
Lars from Berlin

PS: I already had a look at the Configuration Sequence in the Device Handbook, but I'm not fully understanding this.
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RTL Module Packaged into OpenCL Library

May 10, 2017, 6:17 pm
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Does anyone have integrated a RTL Module (VHDL/Verilog) in a OpenCL Kernel as a helper function ？I don't clearly about Using an OpenCL Library that Works with External Memory
(Example 2)?I don't understand the way of performing the working with External Memory.What is the meaning of helper function?
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opencl library example

May 10, 2017, 8:48 pm
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In the website "https://www.altera.com/products/design-software/embedded-software-developers/opencl/developer-zone.html#design-examples",there is an example of "opencl library". In the PDF "Intel FPGA SDK for OpenCL programing guide",2.1.7 Using an OpenCL Library that Works with Simple Functions have the commad perl make_lib.pl ,it can't find the make_lib.pl file when I run the command . Can you tell me where I can find the make_lib.pl ?
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Error (11802): Can't fit design in device. Modify your design to reduce resources,

May 10, 2017, 9:12 pm
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I have successfully run vector_add on the de0nano board example, but when i run the example of matrix_mult, I encountered the above error and view the log as follows:
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/suppo...se/search.html and search for this specific error message number.
Info (144001): Generated suppressed messages file F:/quartus16.1/hld/board/test/exm_opencl_matrix_mult_x64_windows_16.01/matrix_mult/bin/matrix_mult/top.fit.smsg
Error: Quartus Prime Fitter was unsuccessful. 2 errors, 261 warnings
Error: Peak virtual memory: 3462 megabytes
Error: Processing ended: Thu May 11 10:52:45 2017
Error: Elapsed time: 00:15:22
Error: Total CPU time (on all processors): 00:24:57
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 2196 warnings
Error: Flow compile (for project F:/quartus16.1/hld/board/test/exm_opencl_matrix_mult_x64_windows_16.01/matrix_mult/bin/matrix_mult/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.


Error (23031): Evaluation of Tcl script f:/quartus16.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 11 errors, 2196 warnings
Error: Peak virtual memory: 506 megabytes
Error: Processing ended: Thu May 11 10:52:46 2017
Error: Elapsed time: 00:37:33
Error: Total CPU time (on all processors): 00:00:12
--------------------------------------------------------------

I have the kernel file BLOCK_SIZE reduced to 8, the original is 64
__attribute ((reqd_work_group_size (BLOCK_SIZE, BLOCK_SIZE, 1))), I think the resources should not be out of it, why would this error? Does anyone know how to fix it? Thank you!


+ ------------------------------------------------- ------------------- +
; Estimated Resource Usage Summary;
+ ---------------------------------------- + -------- ------------------- +
; Resource + Usage;
+ ---------------------------------------- + -------- ------------------- +
; Logic utilization; 55%;
; ALUTs; 33%;
; Dedicated logic registers; 25%;
; Memory blocks; 37%;
; DSP blocks; 36%;
+ ---------------------------------------- + -------- -------------------;
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Cyclone V PCIe Hard IP compatibility question

May 11, 2017, 1:53 am
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Hi there

This question is probably more of a PCIe question than simply being restricted to the Cyclone V, but I would like to know if anyone has any insight or experience with the issue at hand:

I am using an NXP processor that is specified to be compatible with PCIe base specification 2.0. I want to interface it with the Cyclone V PCIe hard IP which is specified to be compatible with PCIe base specification 2.1 and PCIe base specification 3.0.

According to my understanding, PCIe is both forwards and backwards compatible and this should not be a problem at all, but I would like to find out from anyone who might have used such a setup if there are any specific design or implementation problems that might be necessary to consider.

Thanks in advance
stu84
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Can't get the proper data from custom component through IORD(from io.h file) macro.

May 11, 2017, 2:34 am
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Hello,

I have designed a MM slave component which includes 2 conduit interface and a 8 bit register and I want to read data from that register but some how I can't get the data.
The simulation is done by using ModelSim.
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New User - Licensing Error in Simulation

May 11, 2017, 7:43 am
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Hey everyone!

This is my first time using Quartus at all. I installed it on my laptop so I can do my school work at home. I was able to build a block digaram and compile it no problem but i'm getting an error for running a simulation.

Unable to checkout a license. Vsim is closing.
** Fatal: Invalid license environment. Application closing.


Unable to checkout a license. Make sure your license file environment variables are set correctly and then run 'lmutil lmdiag' to diagnose the problem.
Modelsim-Altera uses the following environment variables to check the licenses (listed in the order of preference)
1. MGLS_LICENSE_FILE
2. LM_LICENSE_FILE.


Error.

I don't know why i'm getting this error, i did some serahcing around and got the idea to request for a license? I was able to get one via email using my NIC. I added the license file to my quartus ii web edition but i'm still getting the same error.

I also found something to install these license files? called

lmgrd.exe
lmulti.exe
mgcld.exe

They open a cmd and close right away ( ran in admin as well).


Now I ran out of ideas. I'm very new so Id really appreciate it if someone gives me a solution it could be step by step processes. Thank you very much!
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Error (10349): VHDL Association List error at mult16bit.vhd(41): formal "o" does not

May 11, 2017, 7:58 am
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entity mult16bit is
generic (
DATA_WIDTH : integer := 16
);
port(
a : in std_logic_vector(DATA_WIDTH-2 downto 0);
--PARAM
b : in std_logic_vector(15 downto 0);
--PARAM
c : out std_logic_vector((3*DATA_WIDTH)-1 downto 0)
);
end mult16bit;

architecture Behavioral of mult16bit is

signal right : std_logic_vector((DATA_WIDTH)+4-3 downto 0);
signal left : std_logic_vector((DATA_WIDTH)+4-3 downto 0);
signal left_shifted : std_logic_vector((2*DATA_WIDTH)-2 downto 0);
signal new_right : std_logic_vector((2*DATA_WIDTH)-2 downto 0);
begin

MULTIPLIER_right:entity work.mult8bit
port map(

a => a(7 downto 0),
b => b,
o => right
);

MULTIPLIER_left:entity work.mult8bit
port map(

a => a(15 downto 8),
b => b,
o => left
);

left_shifted <= left & "0000000" ;
left_shifted <= std_logic_vector("sll"(unsigned(left), 8));

new_right <= "00000000" & right;


c <= unsigned(new_right) + unsigned(left_shifted) ;


end Behavioral;

this is my code and i m getting this error please help me to solve this thanks

Error (10349): VHDL Association List error at mult16bit.vhd(41): formal "o" does not exist File: /mult16bit.vhd Line: 41




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Host build for Altera OpenCL with CMake files

May 11, 2017, 10:35 am
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Hi,

I am trying to map an application called SLAMBench which has already been written in OpenCL to an FPGA. The application compiles totally fine for GPU/CPU OpenCL However It does not find the Altera OpenCL platfrom at all when I build. I know that FPGA OpenCL behaves differently from other platforms (e.g. in needs ClCreateProgramWithBinary() rather than ClCreateProgramWithSource() ) so I have already replaced all the init() function of the SLAMBench application with the Altera OpenCL init() function provided by examples in the Altera website.

The error I get when I run my program is "Unable to find Intel(R) FPGA OpenCL platform". I suspect the reason the host does not find Altera platform is because the AOCL flags are not included as part of the build ( I can successfully compile and run the "hello world" example on the same machine). Now, I tried my very best to include anything that is needed in the host build (by looking at the hello world makefile) .However, the application still fails to find Altera OpenCL. The application builds by calling 3,4 CMakes and its a fairly sophisticated build overall.

Here is the link to the application: https://github.com/pamela-project/slambench
It compiles the whole thing by "make" command.

Does anyone have any idea of what I can do? There are two files called "findOpenCLCmake" file and another "CMake" that has some OpenCL stuff in the application which I have attached. I would be grateful if someone could please let me know how to change these files to hopefully find the Altera OpenCL platform in the build?

Thanks very much!
Attached Files
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Generic One-Hot Multiplexer

May 11, 2017, 2:25 pm
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I am looking for a way to dynamic instantiate a multiplexer of N channels which has a one-hot encoded select. My current hard-coded version for a 3 channel system looks like this:

Code:
signal ChannelSelect    : unsigned(CHAN_SEL_BITS-1 downto 0);
signal EventOneHotFlag  : std_logic_vector(NUM_CHANNELS-1 downto 0);


.....

ChannelSelect <= "00" when EventOneHotFlag(0) = '1' else
                "01" when EventOneHotFlag(1) = '1' else
                "10" when EventOneHotFlag(2) = '1' else
                "00";

MuxOutputData  <= MuxInputArray(to_integer(ChannelSelect))
However, I also have up to 32 channels in some systems that result in the following:


Code:
    ChannelSelect <= '0'&x"0" when EventOneHotFlag(0) = '1' else
                    '0'&x"1" when EventOneHotFlag(1) = '1' else
                    '0'&x"2" when EventOneHotFlag(2) = '1' else
                    '0'&x"3" when EventOneHotFlag(3) = '1' else

.... Sparing you the whole list......


                    '1'&x"D" when EventOneHotFlag(29) = '1' else
                    '1'&x"E" when EventOneHotFlag(30) = '1' else
                    '1'&x"F" when EventOneHotFlag(31) = '1' else
                    '0'&x"0";



MuxOutputData  <= MuxInputArray(to_integer(ChannelSelect))
Both work correctly, but I have not found a synthesize solution to parameterize the mux to make it generic for use across system builds. I have been unsuccessful trying Generate statements or For Loops to handle the One-Hot select case.

Thanks,
Aaron
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How to do a frequency multiplier?

May 11, 2017, 8:32 pm
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Hi all,

I have a CPLD EPM3064AT44. I wonder is it possible to do a frequency multiplier, which would output 6M signal while inputting 1M?

Thanks!
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