Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Error 10500: expecting if

June 14, 2017, 11:31 pm
$
0
0
I just don't understand what the matter is that i always get the same error:

10500 VHDL Syntax error at sec_cnt.vhd(58) near text "process"; expecting "if"

(see in attached code)


Im thankful for evey helper :)
Attached Files
↧
Search

Unable to simulate MAX 10 ADC

June 15, 2017, 5:03 am
$
0
0
Hi,

I'm thoroughly stuck on simulating the MAX 10 ADC.
Tools: Quartus 17 Lite (and 16.1) + ModelSim-Altera 10.5b

Modelsim error:
# ** Error: (vsim-3033) C:/temp/ADCtest3/source/On_Chip_ADC/simulation/submodules/On_Chip_ADC_modular_adc_0.v(38): Instantiation of 'On_Chip_ADC_modular_adc_0_control_internal' failed. The design unit was not found.

Steps taken:
1. Create Max10 project with top level and testbench VHDL.
2. Use IP Catalog to create "Altera Modula ADC Core" and generate the HDL code, selecting VHDL synthesis and VHDL models.
3. Add the generated component to my VHDL
4. Add the generated .qip and .sip files to Project Navigator
5. Tools>Run Simulator Tool>RTL Simulation
6. Get several ModelSim error messages similar to the above.

I'm puzzled that I don't see 'On_Chip_ADC_modular_adc_0_control_internal' defined anywhere.

Does anyone know what causes this error?

(I'm using the IP Catalog, not Qsys, because I want to be able to wire up the ADC PLL myself. I do have the PLL.)

Thanks,
Rob
↧
↧

Cyclone V Clock Not Toggling

June 15, 2017, 6:44 am
$
0
0
Device: 5CGTFD9E5F35C7
Quartus Version 14.1

I am currently having problems with the on-board oscillator (CLK5p(U31)) not toggling when used as the clock source in Signal Tap(e.g. the 'waiting for clock' status). In my design this clock is only connected to a Qsys generated DRAM module. The outputted Avalon clock also does not toggle which is a result of the input clock not toggling. I have tried using different clocks such as the CLK10p from the X4 programmable oscillator and that did not produce the waiting for clock status from Signal Tap. But, this clock did not produce an Avalon clock that toggled. I also tapped the waitrequest_n(1 = bus can be accessed) output from the dma_module and that did not toggle. However, this is probably due to the internal clocks of the DRAM module not being generated for some reason. I have also made a simple counter and viewed the results with Signal Tap to test the clocks. I found that clocks from sourced from the programmable X4 clock work as predicted. However, the fixed oscillators such as CLK5p do not oscillate and give the 'waiting for clock' status.

I also verified that the Qsys module is configured for input clock frequency (125 MHz).

Also DRAM timing was not met for some address values. The input clock and DRAM clock output also have negative slack (-4.570 and -.470 respectively).

Any help would be greatly appreciated.
↧

difference between option 1 and option 2 in 1152-Pin FBGA package for ARRIA 10 SOC

June 15, 2017, 8:11 am
$
0
0
Hi,
I'm a new member of this forum. I'm a HW/FW designer. I'm developing a schematic based on ARRIA 10 SOC.
I choosed the 10AS048H434I3SG device (1152 pins, 35mm x 35mm). I saw there can be also 10AS048H435I3SG with the same package.
I read the package information datasheet and it talks about an opton 2 on the same package 1152-pin FBGA.
Can you please explain me the difference between option 1 an option 2?
thanks a lot!!!
Massimo
↧

Looking for specific Stratix product

June 15, 2017, 12:23 pm
$
0
0
Hi there,

I am looking to buy Stratix EPS1S10F672C6-ES but cannot seem to find the product on the website. Can someone kindly provide a webpage or a link that will be direct me to purchase the mentioned product.

Thanks alot in advance.
↧
↧

Timing for MAX 10 ADC Control Core Only interace logic

June 15, 2017, 2:06 pm
$
0
0
I'm trying to create the necessary external logic to control a MAX10 ADC Control Core Only instance. The timing in figure 8 of the UG-M10ADC User Guide does not define the relationship between command_valid, command_startpacket, command_endofpacket, or command_ready. Also, what is the reference for the term "ADC soft IP clock"? Is this the same thing as "modular_adc_pll_clock"?
↧

How to increase NIOS II Instruction Memory?

June 15, 2017, 4:13 pm
$
0
0
I have a Nios II/e system running on a Cyclone V with 64000 bytes on-chip memory. It runs with no problems until I add an additional function call to my code. It doesn't seem to matter too much what the function call is or where it is located in the code but it causes the program to freeze after download from the Nios II Eclipse IDE. I eliminated several unused variables in the code and that allowed one additional function call before encountering the problem.

I suspected that I didn't have enough on chip memory allocated. Running CheckElfSize.sh results in: text data bss dec hex filename
54464 1004 3908 59376 e7f0 ../software/09EO2.elf

I doubled the size of the on-chip memory in Qsys to 128000 bytes, reassigned base addresses, recompiled both the hdl and Nios code and still ran into the same problem. Absolutely no benefit to doubling the size of the on-chip memory. It sure seems like I'm running out of program memory but I can't figure out how to increase the size of program memory if doubling the size of the on-chip memory doesn't work. Searching through the Nios II documentation hasn't given me any easy answers yet. Thanks for any assistance anyone can give.


I'm running Qsys 16.0 Build 211
↧

Complier Error, Quartus Prime Fitter was unsuccessful

June 15, 2017, 11:21 pm
$
0
0
Hi,
I tried to compile a compution.cl file with aoc command to generate computation.aocx.
(The command line is aoc -v computation.cl -o computation.aocx)
But It failed to generate .aocx file and only .aoco file was generated.
With the -v , it showed the stage of compiling on the screen and the information is :

------Screen-------
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected default target board a10gx
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
Warning: Kernel 'fullyLayer' has unused argument 'inputDataSize'
aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware
---------------------

Then I checked computation.log in the computation floder. It showed no error occured :

-------computation.log---------
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 581 megabytes
Info: Processing ended: Fri Jun 16 09:08:55 2017
Info: Elapsed time: 00:00:34
Info: Total CPU time (on all processors): 00:00:00
----------------------------------

Then I checked top.fit.rpt for more information and the usage of resource in this file showed the resource was enough:

+--------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------------+--------------------------------------------+
; Fitter Status ; Failed - Fri Jun 16 13:32:10 2017 ;
; Quartus Prime Version ; 16.1.1 Build 200 11/30/2016 SJ Pro Edition ;
; Revision Name ; top ;
; Top-level Entity Name ; top ;
; Family ; Arria 10 ;
; Device ; 10AX066N3F40E2SG ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 30,540 / 251,680 ( 12 % ) ;
; Total registers ; 302754 ;
; Total pins ; 290 / 812 ( 36 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 22,860,776 / 43,642,880 ( 52 % ) ;
; Total RAM Blocks ; 218 / 2,131 ( 10 % ) ;
; Total DSP Blocks ; 234 / 1,687 ( 14 % ) ;
; Total HSSI RX channels ; 8 / 48 ( 17 % ) ;
; Total HSSI TX channels ; 8 / 48 ( 17 % ) ;
; Total PLLs ; 57 / 96 ( 59 % ) ;
+-----------------------------+--------------------------------------------+

But at the end of top.fit.rpt, it reported some errors :

----------top.fit.rpt----------Error (18999): Placement cannot find a legal solution.
Error (18999): Placement cannot find a legal solution.
Error (18999): Placement cannot find a legal solution.
Error (18999): Placement cannot find a legal solution.
Info (170191): Fitter placement operations beginning
Info (170192): Fitter placement operations ending: elapsed time is 00:01:11
Info (11888): Total time spent on timing analysis during Placement is 572.60 seconds.
Error: An error occurred during placement
Info (144001): Generated suppressed messages file c:/Users/xinzhou/Desktop/dnn_1.1.1.1/bin_profile/fully_layer/top.fit.smsg
Error: Quartus Prime Fitter was unsuccessful. 5 errors, 1014 warnings
Error: Peak virtual memory: 24521 megabytes
Error: Processing ended: Fri Jun 16 13:32:25 2017
Error: Elapsed time: 03:02:03
Error: Total CPU time (on all processors): 08:17:02

+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in c:/Users/...
--------------

What's more, my OS is Windows 10 Professional , Quartus version is 16.1.1, AOC version is 16.1.0, and It generated .aocx file successfully Before with other OpenCL kernel file.
Why it failed to generate .aocx file? And what should I do to shoot this trouble?
I am waiting for your reply. Thank you.
↧
Search

Avalon MM master interface

June 16, 2017, 4:36 am
$
0
0
Hello,

Can we add any custom extra signal to Avalon MM master interface of any Qsys component (Nios2 processor)?

Thanks
S.Arudchutha
↧
↧

DDR2_SDRAM Interface to Cyclone-3 device

June 16, 2017, 6:21 am
$
0
0
Hi
I have downloaded this attached code.
This code pin assignment is not matching with our board pin assignment, so I just removed the .qsf file and run again to do the pin assignment as per our board.
There is no error in : analysis & synthesis, fitter, assembler, timeQuest Timing analyser phase
But we got error in : EDA Netlist generator phase.
Error what I got also attached here.
Please guide us how to go ahead.


Error is listed here:
Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file
Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available
Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file
Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available
Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file
Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available
Error: Can't generate netlist output files because the file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is an OpenCore Plus time-limited file
Error: Can't generate netlist output files because the license for encrypted file "H:/jk_2017/VHDL_CODE_LEARNING/level_2/DDR_DOWNLOAD_CODE/CIII_DDR2_restored/auk_ddr_hp_controller.vhd" is not available
Error: Quartus II EDA Netlist Writer was unsuccessful. 8 errors, 0 warnings
Error: Peak virtual memory: 275 megabytes
Error: Processing ended: Thu Jun 15 12:50:18 2017
Error: Elapsed time: 00:01:26
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 10 errors, 139 warnings
Attached Files
↧

Lifecycle information for Cyclone III EP3C5E144C8N and EP3C16Q240C8N

June 16, 2017, 11:37 am
$
0
0
Where can I find lifecycle status for the Cyclone III EP3C16Q240C8N and EP3C5E144C8N? Searches via Google and on this forum have not turned up anything.
↧

Unexplained performance difference for same kernels

June 16, 2017, 2:08 pm
$
0
0
I have develop two identical kernels, with a single difference where the size of the for loop in one of them is higher than the other. Here are my two kernels, Kernel #1 and Kernel #2.

First Kernel:
Code:
__attribute__((num_compute_units(5)))
__attribute__((num_simd_work_items(16)))
__attribute__((reqd_work_group_size(256,1,1)))
__kernel void TestS16VfloatI1048576D32Form1MUnrol0U16(__global float *data, __global float *rands, int index, int rand_max){
    float16 temp;
    int gid = get_global_id(0);


    temp = data[gid];
    #pragma unroll 16
    for (int i = 0; i < 32; i++){
        temp = (float) rands[i] * temp;
    }
    data[gid] = temp.s0;


}
Second Kernel:
Code:
__attribute__((num_compute_units(5)))__attribute__((num_simd_work_items(16)))
__attribute__((reqd_work_group_size(256,1,1)))
__kernel void TestS16VfloatI1048576D256Form1MUnrol0U16(__global float *data, __global float *rands, int index, int rand_max){
    float16 temp;
    int gid = get_global_id(0);


    temp = data[gid];
    #pragma unroll 16
    for (int i = 0; i < 256; i++){
        temp = (float) rands[i] * temp;
    }
    data[gid] = temp.s0;


}
As it's clear in both kernel implementations, both acquire same amount of hardware resources and also both unfolding the loop with same degree. There are compiled as NDRanege and I deploy around 1 Million work items.
Now calculating the amount of floating point operations being done, I can see the first kernel can achieve 1.57 TFlops performance while the second kernel can achieve 4.37TFlops. I'm trying to come up with an explanation on how it's possible that increasing number of operation inside the kernel can increase performance, while keeping the run time the same?
↧

SRAM DS2064 into a CPLD

June 16, 2017, 10:11 pm
$
0
0
Is it a good idea to implement a SRAM DS2064 (8 bit x 8k) into a CPLD?

After a lot of internet research, I was unable to find a VDHL code for it.

I just attached the DS2064 for reference.

Thanks!
Attached Files
↧
↧

contains one or more time-limited megafuction

June 16, 2017, 10:46 pm
$
0
0
Hi everyone
i'm doing project about real time speech recognition . I was able to complie and simulate my design but when I tried to program my design in fpga, i am getting error like this.
Info: SRAM Object File C:/Users/Kaido Kid/Desktop/test1/SpeechRecog_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x0034
Info: SRAM Object File C:/Users/Kaido Kid/Desktop/test1/SpeechRecog_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2
I use quartus web edition 11.0 and board altera de 2, cyclone ii
does anyone have solution for my problem?




↧

How to speedup the compilation of Quartus II

June 17, 2017, 12:35 am
$
0
0
Hi, I have met a problem when I try to compile a big project. It cost more than 36 hours using the Quartus II 64-bit software, but it only complete 11% of the total compilation process. What can I do to speed up the compilation process? Thank you for the help. I am so worried about the problem.
↧
Search

[Q] Is there any problem with Ubuntu 17.x.x for Quartus II?

June 17, 2017, 7:42 pm
$
0
0
Hello,

I installed the free edition of Quartus on Ubuntu. But, I can't start it. The error looks like:

Code:
$./quartus
$quartus: error while loading shared libraries: libpng12.so.0: cannot open shared object file: No such file or directory
I found a topic on the web also,

https://askubuntu.com/questions/8958...-libpng12-so-0

Thanks.
↧

Hybrid Memory Cube Controller IP

June 14, 2017, 12:55 pm
$
0
0
Hello,

I synthesized the example design for the HMCC with no errors. However, I cannot generate the programming files because my license does not support this IP ( ID # 115003 on Quartus 15.1 ). However, in the Altera tutorial, it seemed that this IP suppose to be supported on any standard licences.

Please assist running this example code.

Best,
Sasha
↧
↧

DE0 Cyclone V GPIO 1-Z switching, RN series

June 14, 2017, 3:07 pm
$
0
0
Hello, I am currently working with DE0 cyclone V now.
I am trying to make a circuit that constantly switches the GPIO pins between 1-Z ( high impedance state) at a specified frequency (ex: 900 kHz).
But when I measure the voltage signals between GPIO pins and ground by an oscilloscope, it shows that even when GPIO pins are Z state, there are still some voltage.
Looking at the schematics, I can see that the GPIO pins are not directly driven by the FPGA. There are a RN series between GPIO pins and FPGA pins, as illustrated in the following photo:


I tried to look it up but I couldn't find what is that RN series, and what are they used for ?
And I also see that GPIO pins are driven by a source voltage through a pair of Schottky Diodes as as illustrated in the following photo:


I don't get why they need to drive the GPIO pins by another source of voltage. Then when the signal comes from the FPGA, how can it pull down the value of GPIO pins to 0 ?

Does anyone have the schematics of the above RN series and the Schottky Diode array ?
Thank you so much!
Attached Images
↧

Error 10500: expecting if

June 14, 2017, 11:31 pm
$
0
0
I just don't understand what the matter is that i always get the same error:

10500 VHDL Syntax error at sec_cnt.vhd(58) near text "process"; expecting "if"

(see in attached code)


Im thankful for evey helper :)
Attached Files
↧

Unable to simulate MAX 10 ADC

June 15, 2017, 5:03 am
$
0
0
Hi,

I'm thoroughly stuck on simulating the MAX 10 ADC.
Tools: Quartus 17 Lite (and 16.1) + ModelSim-Altera 10.5b

Modelsim error:
# ** Error: (vsim-3033) C:/temp/ADCtest3/source/On_Chip_ADC/simulation/submodules/On_Chip_ADC_modular_adc_0.v(38): Instantiation of 'On_Chip_ADC_modular_adc_0_control_internal' failed. The design unit was not found.

Steps taken:
1. Create Max10 project with top level and testbench VHDL.
2. Use IP Catalog to create "Altera Modula ADC Core" and generate the HDL code, selecting VHDL synthesis and VHDL models.
3. Add the generated component to my VHDL
4. Add the generated .qip and .sip files to Project Navigator
5. Tools>Run Simulator Tool>RTL Simulation
6. Get several ModelSim error messages similar to the above.

I'm puzzled that I don't see 'On_Chip_ADC_modular_adc_0_control_internal' defined anywhere.

Does anyone know what causes this error?

(I'm using the IP Catalog, not Qsys, because I want to be able to wire up the ADC PLL myself. I do have the PLL.)

Thanks,
Rob
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>