Device: 5CGTFD9E5F35C7
Quartus Version 14.1
I am currently having problems with the on-board oscillator (CLK5p(U31)) not toggling when used as the clock source in Signal Tap(e.g. the 'waiting for clock' status). In my design this clock is only connected to a Qsys generated DRAM module. The outputted Avalon clock also does not toggle which is a result of the input clock not toggling. I have tried using different clocks such as the CLK10p from the X4 programmable oscillator and that did not produce the waiting for clock status from Signal Tap. But, this clock did not produce an Avalon clock that toggled. I also tapped the waitrequest_n(1 = bus can be accessed) output from the dma_module and that did not toggle. However, this is probably due to the internal clocks of the DRAM module not being generated for some reason. I have also made a simple counter and viewed the results with Signal Tap to test the clocks. I found that clocks from sourced from the programmable X4 clock work as predicted. However, the fixed oscillators such as CLK5p do not oscillate and give the 'waiting for clock' status.
I also verified that the Qsys module is configured for input clock frequency (125 MHz).
Also DRAM timing was not met for some address values. The input clock and DRAM clock output also have negative slack (-4.570 and -.470 respectively).
Any help would be greatly appreciated.
Quartus Version 14.1
I am currently having problems with the on-board oscillator (CLK5p(U31)) not toggling when used as the clock source in Signal Tap(e.g. the 'waiting for clock' status). In my design this clock is only connected to a Qsys generated DRAM module. The outputted Avalon clock also does not toggle which is a result of the input clock not toggling. I have tried using different clocks such as the CLK10p from the X4 programmable oscillator and that did not produce the waiting for clock status from Signal Tap. But, this clock did not produce an Avalon clock that toggled. I also tapped the waitrequest_n(1 = bus can be accessed) output from the dma_module and that did not toggle. However, this is probably due to the internal clocks of the DRAM module not being generated for some reason. I have also made a simple counter and viewed the results with Signal Tap to test the clocks. I found that clocks from sourced from the programmable X4 clock work as predicted. However, the fixed oscillators such as CLK5p do not oscillate and give the 'waiting for clock' status.
I also verified that the Qsys module is configured for input clock frequency (125 MHz).
Also DRAM timing was not met for some address values. The input clock and DRAM clock output also have negative slack (-4.570 and -.470 respectively).
Any help would be greatly appreciated.