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importing pin assignments

July 30, 2017, 2:22 am
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Hi ,

I am using Quartus Prime ver 16.0 lite edition , i tried to import pin assignments for my DE2-115 board from a excel file "DE2_115_pin_assignments.csv" , compiled the project but i noticed the fitter didnt assigned and pin as per .csv file .

I tried the manual approach and from within Pin Planner clicked on the CLK pin and tried to change its assignment , but a message poped up that its read-only ??? .

This a new project creation .

How do i import and force fitter to assign pins as per .csv file ????

Regards ,

Ahmed
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OpenCL issue on Angstrom custom build for DE1-SoC

July 29, 2017, 6:09 am
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Hi, all!

Could you help me to solve the following issue.

I am trying to launch OpenCL examples on Angstrom custom build for DE1-SoC.
The version of OpenCL SDK, Quartus and other tools is 16.1
Firstly I've built vector_add example and successfully launch it on standard Angstrom image (3.12 ltsi kernel) for DE1-Soc

Then I created Angstrom 2015 with 4.2 kernel according to these instructions: https://rocketboards.org/foswiki/vie...romOnSoCFPGA_1
I copied kernel, rootfs and dts files created be Angstrom to sdcard as recommended here: https://rocketboards.org/foswiki/vie...on_the_SD_card
Angstrom Linux launched successfully.
After that I downloaded OpenCL RTE for 16.1 version and compiled OpenCL driver for new 4.2 kernel. After running opencl_init.sh driver loaded successfully.

aocl diagnostic also finished with success:

aocl diagnose: Running diagnostic from /home/root/aocl-rte-16.1.0-1.arm32/board/c5soc/arm32/bin

Verified that the kernel mode driver is installed on the host machine.

Using platform: Intel(R) FPGA SDK for OpenCL(TM)
Board vendor name: Intel(R) Corporation
Board name: de1soc_sharedonly : Cyclone V SoC Development Kit

Buffer read/write test passed.

DIAGNOSTIC_PASSED


Then I slightly change and recompile examples (change platform name from Altera to Intel).

Unfortunately for this new configuration examples hangs.

Result of launching hello_world example:

Querying platform for info:
==========================
CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM)
CL_PLATFORM_VENDOR = Altera Corporation
CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 16.1

Querying device for info:
========================
CL_DEVICE_NAME = de1soc_sharedonly : Cyclone V SoC Development Kit
CL_DEVICE_VENDOR = Intel(R) Corporation
CL_DEVICE_VENDOR_ID = 4466
CL_DEVICE_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 16.1
CL_DRIVER_VERSION = 16.1
CL_DEVICE_ADDRESS_BITS = 64
CL_DEVICE_AVAILABLE = true
CL_DEVICE_ENDIAN_LITTLE = true
CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768
CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0
CL_DEVICE_GLOBAL_MEM_SIZE = 536870912
CL_DEVICE_IMAGE_SUPPORT = true
CL_DEVICE_LOCAL_MEM_SIZE = 16384
CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000
CL_DEVICE_MAX_COMPUTE_UNITS = 1
CL_DEVICE_MAX_CONSTANT_ARGS = 8
CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 134217728
CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3
CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 8192
CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024
CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4
CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2
CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1
CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0
Command queue out of order? = false
Command queue profiling enabled? = true
Using AOCX: hello_world.aocx
Reprogramming device [0] with handle 1

Kernel initialization is complete.
Launching the kernel... (after this line program hangs)


Result of launching vector_add example:

Initializing OpenCL
Platform: Intel(R) FPGA SDK for OpenCL(TM)
Using 1 device(s)
de1soc_sharedonly : Cyclone V SoC Development Kit
Using AOCX: vectorAdd.aocx
Reprogramming device [0] with handle 1
Launching for device 0 (1000000 elements) (after this line program hangs)

I tried took top.rbf file created by OPenCL SDK for hello_world example, rename this file to opencl.rbf and exchange this file with original one on my sdcard. It is not help.

Could you help me to solve this issue or recommend the way for debugging the system?
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My_First_HPS Error

July 29, 2017, 7:26 am
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Hi, I have just started the DE10-Standard kit and run through the tutorial included in the package but I was stucked in My_First_HPS topic. I have this error below:

"make: *** No rule to make target '/intelFPGA/16.1.embedded/ip/altera/hps/altera_hps/hwlib/include/', needed by '-IC'. Stop."


Please see below for the makefile script:

#
TARGET=my_first_hps
ALT_DEVICE_FAMILY?=soc_cv_av
SOCEDS_ROOT?=$(SOCEDS_DEST_ROOT)
HWLIBS_ROOT=$(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib
CROSS_COMPILE=arm-linux-gnueabihf-
CFLAGS=-g-Wall -D$(ALT_DEVICE_FAMILY)
-I$(HWLIBS_ROOT)/include/$(ALT_DEVIVE_FAMILY)
-I$(HWLIBS_ROOT)/include/LDFLAGS= -g-Wall
CC=$(CROSS_COMPILE)gcc
ARCH=arm
build: $(TARGET)
$(TARGET):main.o
$(CC)$(LDFLAGS) $^-o$@
%.o:%.c
$(CC)$(CFLAGS)-c$<-o$@
.PHONY:clean
clean:
rm-f $(TARGET)*.a*.o*~

Please see my folder structure below:

C:\intelFPGA\16.1\embedded
C:\intelFPGA\16.1\embedded\Embedded_Command_Shell. bat
C:\intelFPGA\16.1\embedded\Embedded_Command_Shell. sh

C:\intelFPGA\16.1\embedded\drivers
C:\intelFPGA\16.1\embedded\ds-5
C:\intelFPGA\16.1\embedded\ds-5_installer
C:\intelFPGA\16.1\embedded\embeddedsw
C:\intelFPGA\16.1\embedded\examples
C:\intelFPGA\16.1\embedded\host_tools
C:\intelFPGA\16.1\embedded\ip

C:\intelFPGA\16.1\embedded\my_first_hps
C:\intelFPGA\16.1\embedded\my_first_hps\main.c
C:\intelFPGA\16.1\embedded\my_first_hps\makefile

Rgds,
jsv
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DE10-Standard My_First_HPS Error

July 29, 2017, 8:02 am
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Hi, I have just started the DE10-Standard kit and run-thru the tutorials included in the package. I was stucked in the My_First_HPS section and got the error below:

"make: *** No rule to make target '/intelFPGA/16.1/embedded/ip/altera/hps/altera_hps/hwlib/include/', needed by '-IC'. Stop."


Below is my makefile:

#
TARGET=my_first_hps
ALT_DEVICE_FAMILY?=soc_cv_av
SOCEDS_ROOT?=$(SOCEDS_DEST_ROOT)
HWLIBS_ROOT=$(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib
CROSS_COMPILE=arm-linux-gnueabihf-
CFLAGS=-g-Wall -D$(ALT_DEVICE_FAMILY)
-I$(HWLIBS_ROOT)/include/$(ALT_DEVIVE_FAMILY)
-I$(HWLIBS_ROOT)/include/LDFLAGS= -g-Wall
CC=$(CROSS_COMPILE)gcc
ARCH=arm
build: $(TARGET)
$(TARGET):main.o
$(CC)$(LDFLAGS) $^-o$@
%.o:%.c
$(CC)$(CFLAGS)-c$<-o$@
.PHONY:clean
clean:
rm-f $(TARGET)*.a*.o*~

Below is my folder structure:

C:\intelFPGA\16.1\embedded
C:\intelFPGA\16.1\embedded\Embedded_Command_Shell. bat
C:\intelFPGA\16.1\embedded\Embedded_Command_Shell. sh

C:\intelFPGA\16.1\embedded
C:\intelFPGA\16.1\embedded\drivers
C:\intelFPGA\16.1\embedded\ds-5
C:\intelFPGA\16.1\embedded\ds-5_installer
C:\intelFPGA\16.1\embedded\embeddedsw
C:\intelFPGA\16.1\embedded\examples
C:\intelFPGA\16.1\embedded\host_tools
C:\intelFPGA\16.1\embedded\ip

C:\intelFPGA\16.1\embedded\my_first_hps
C:\intelFPGA\16.1\embedded\my_first_hps\main.c
C:\intelFPGA\16.1\embedded\my_first_hps\makefile

Rgds,
Joven
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Quartus can not run Modelsim

July 30, 2017, 1:16 pm
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Hello :),
I run Quartus prime pro 17 with float license on Linux. Synthesis and bit stream generation are successfully done. But when I want to run Modelsim simulation, there is no place that I can assign Modelsim executable. Modelsim_AE and ASE exist in the Quartus folder. In tools->options there is no place for EDA tool settings!? as I see many pages in internet, there should be such setting in there. I see only general, message and text editor setting.
After making a .vwf waveform, testbench and scripts are successfully generated, but "run functional simulation" can not proceed with this error:

Unable to open /home/hamzeh/Desktop/test/simulation/qsim/myWaveform.vwf.vt
Error.

Can anybody help me on this?

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Error compiling Altera Uart 16550 IP Core Cyclone V

July 30, 2017, 1:24 pm
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Hello,

+ Quartus 17 Prime Lite edition
+ Windows 7 64 bits
+ Altera 16550 Compatible UART

I'm trying to use this module via avalon/axi bus. I added the module via qsys with no problems and I compiled a C software using the HWLIB and SoCAL libraries delivered by Altera.
When I try to compile the project I get this error:

Code:
Error (210039): File xxxxxx/de10nano_uart_16550/quartus/output_files/led_test_time_limited.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
I understand what the error means but I think there is a mistake here given that I'm using the IP Cores delivered with Quartus and no other sources, besides there is no info on the documentation[1] about this megafunction being limited or how can we buy it.

It generates a limited sof file which works OK while being connected but some implementations are not working (like FIFO).

This is the first time I get a problem using Qsys + IP cores so I guess it is a bug on Quartus ?


[1] Altera Corporation. (2017). Embedded Peripherals IP User Guide. Altera Documentation, (June), 358. Retrieved from https://www.altera.com/literature/ug
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Error compiling Altera Uart 16550 IP Core Cyclone V

July 30, 2017, 1:26 pm
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Hello,

+ Quartus 17 Prime Lite edition
+ Windows 7 64 bits
+ Altera 16550 Compatible UART

I'm trying to use this module via avalon/axi bus. I added the module via qsys with no problems and I compiled a C software using the HWLIB and SoCAL libraries delivered by Altera.
When I try to compile the project I get this error:
Code:
Error (210039): File xxxxxx/de10nano_uart_16550/quartus/output_files/led_test_time_limited.sof contains one or more time-limited megafunctions that support the OpenCore Plus feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
I understand what the error means but I think there is a mistake here given that I'm using the IP Cores delivered with Quartus and no other sources, besides there is no info on the documentation[1] about this megafunction being limited or how can we buy it.

It generates a limited sof file which works OK while being connected but some implementations are not working (like FIFO)
This is the first time I get a problem using Qsys + IP cores so I guess it is a bug on Quartus ?

[1] Altera Corporation. (2017). Embedded Peripherals IP User Guide. Altera Documentation, (June), 358.
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Error in linking SOPC buider system file with eclipse

July 30, 2017, 10:37 pm
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Hello, I have successfully generated a system in SOPC builder but when I open eclipse to program Nios II processor present in SOPC design following error prompts
"SOPC Builder system file does not contain an enabled Nios II CPU"
Moreover I get the following warning while doing compilation in quartus II

Warning: Can't generate programming files for project because design file "C:/altera/90/quartus/Proj_helloworld/Proj_helloworld/incremental_db/compiled_partitions/Proj_Qsys.root_partition.map.atm" is encrypted. It does not have license file support that allows generation of programming files.
Has this warning something to do with aforementioned error? Kindly help me resolving this error.
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How to create a TRDB D5M camera in testbench?

July 31, 2017, 1:46 am
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If one is writing cores that shall take data from the TRDB D5M and process it, it shall be of great help to have some way of instantiating it in a testbench. Is this possible? I so, how?
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does MAX10 10M50SA support CFM UFM and RSU?

July 31, 2017, 3:41 am
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hi,

I know that Max10 10M50DA support CFM, UFM and RSU, and work well. But I don't know if 10M50SA support these features too?
My colledge told me not, but the datasheet said YES. What is the face? Thanks for your reply.
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Another 10482 VHDL error

July 31, 2017, 5:13 am
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Hello folks. I am trying for the first time to ease into the Altera MegaWizard DDR3 controller and have written a small VHDL top-level module containing an instance of the DD3 controller from the MegaWizard. When I try to compile the design, Quartus returns several 10482 errors; for example, "Error (10482): VHDL error at TryOutQuartusTop.vhd(212): object "pll_ref_clk" is used but not declared." Each of the errors refers to a port on the MegaWizard - generated DDR3 controller. I have searched the VHDL forum but have not found the answer. pl_ref_clk appears in the MegaWizard - generated files, so I do not know how to solve this error. I can follow the pll_ref_clk through the hierarchy, and it is connected. Can any one help?
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Need assistance with Setting up transceiver for C5G dev board

July 31, 2017, 8:12 am
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Hello all,

I'm currently designing a basic BERT using the cyclone 5 gx dev board. The problem I'm having right now is that while I'm only getting time analysis warnings, the transmitters don't appear to be transmitting anything on my board.

I'm fairly new to the FPGA/VHDL programming scene, so I was wondering if a more experience eye could look at my work thus far and point out where I might be going wrong. I'm sure there's plenty wrong with my code right now, but I'm mainly just looking for some basic tips and any ideas why my transmitters might not be working.

My file's a bit large to put as an attachment here, so I'm putting a google drive link for anyone who wishes to assist. If there's a more preferable way, please let me know.

https://drive.google.com/open?id=0B9...WN2LXpYNkk5MnM

I'm looking forward to your responses and learning more about using Quartus/VHDL.
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MvcHome

July 31, 2017, 12:19 pm
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Still trying to get a simulation running.

This is for a Cyclone V, with an ARM and a NIOS CPU.

I am getting two basic errors when I try to run the simulation, but they might be related. The first error that pops up is:

# ** Error: (vsim-8388) Could not find the MVC shared library : MvcHome not specified. Please specify in modelsim.ini or on command line (-mvchome).


I know how to set teh MvcHome variable: In the Modelsim.ini file I can add the line MvcHome = <path>. What I don't know is what the path is.

Would this be something that was generated by Qsys and thus in a sub directory of my project?
Would it be a library that was included in the Altera installation directory?
Is it something that I need to obtain from a third party?


The next errors I get are of this nature:

** Error: (vsim-3033) Z:/Abaxis/RomuLus/FPGA_ARM_NIOS/Romulus_CPU_cores/simulation/submodules/Romulus_CPU_cores_nios2_qsys_0_cpu.vo(17862): Instantiation of 'oper_add' failed. The design unit was not found.

# ** Error: (vsim-3033) Z:/Abaxis/RomuLus/FPGA_ARM_NIOS/Romulus_CPU_cores/simulation/submodules/Romulus_CPU_cores_nios2_qsys_0_cpu.vo(18166): Instantiation of 'oper_less_than' failed. The design unit was not found.


If someone can tell me how to resolve these issues I would be greatly appreciative.

Rod
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nios with custom fpga logic

July 31, 2017, 2:46 pm
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Hello everybody. I am trying to set up a simple example where I implement a simple XOR gate in fpga logic. Then in C code written for the NIOS processor, I will pass several numbers to be XOR'd, and read back the outputs.
I am following this example: https://www.youtube.com/watch?v=mOc3ErBiuGY&t=75s.
My example would appear to be working, except I read back 0 with the IORD command every time. I write to the base address for my XOR gate (0 offset), and read back from that same address in the next line of main.cpp. Am I reading the XOR result from the correct memory address (i.e. same as write address)? Is there an error in how I pass the numbers to the 2 adder inputs?

I am attaching screenshots of:
1. main.cpp (NIOS)
2. 2 modules I use to implement a simple XOR gate.
3. screenshot of QSYS set-up.

I appreciate any ideas thoughts on this. I am puzzled. There are no error messages in the NIOS console/eclipse.

Thanks,
Matt
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Designing a SPI slave

July 31, 2017, 5:31 pm
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Hello everyone,

This is my 1st post on this forum, so I apologize if I'm doing some noob mistake, i.e. posting this question in the wrong place. I remember doing that in other forums :)

Anyways, I'm trying to add a SPI slave to my Cyclone IV VHDL design. It works, but looks like the SPI_CLK pin is very often clocking twice on a single rising edge. An ATXMEGA MCU is generating the signals as the master.

First thought was the speed of the rising slope, and so I shortened the wires on my prototype to reduce the load. It helped. The amount of double clocks reduced. But it's still happening, and the wires are pretty short already.

My question is: Should I be using a dedicated clock pin of the FPGA for the SPI_CLK? I've read that those dedicated clock pins indeed offer a lower load to the signal, but their main feature is being global and easily accessible to all flip flops.
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AN458 Alternative Nios II Boot Methods doesn't work with Quartus Lite toolsuite

August 1, 2017, 12:53 am
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Hi

I would like to share what I have experienced with AN458.
It used to work with the older Quartus versions, but since Quartus Lite it doesn't work any more.
I don't know the exact reason but make_flash_image_script.sh file must be modified: this code section must be commented:

conv -D $fake_copier ;

# check for errors
#
if [ $? -ne 0 ] ; then
echo ""
echo "ERROR: trying to convert the file $fake_copier to DOS format."
echo ""
echo "Deleting file $fake_copier, and $tmp0_outfile_elf and exiting!"
echo ""
rm -f $fake_copier;
rm -f $tmp0_outfile_elf;
exit 1;
fi

it used to transform the LF (Line Feed) into CR LF (Carriage Return + Line Feed)
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manually assigned pin number not showing up in my BDF

August 1, 2017, 5:46 am
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I have a problem, just started new project with just an input pin and output pin connected together. I assigned them pin numbers in the pin planner, but they don't show up in the BDF.
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enable differential mode on alt_iobuf??

August 1, 2017, 5:47 am
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I have a project based on and Arria 10 SoC development board which using FMC ports (LVDS IO Standard). I have a bidrectional pin which is the "io" port in an alt_iobuf instance.
The project synthesizes fully, but fails on the fitting, giving the error " can't on open-drain option for differential io pin".
I have looked up the solution and everywhere says to enable differential mode on the IO buffer, but nowhere says how to enable it?. Here is the current instance:

alt_iobuf IOBUFF_scl (
.i(1'b0),
.oe(scl_oen),
.io(scl), //bidirectional pin
.o(scl_c_normal)

);


How do you enable differential mode?

Dáire
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Profiling OpenCL kernel code

August 1, 2017, 7:40 am
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Setting up profiling for standard applications is usually fairly trivial. For example, to generate C or C++ language code coverage analysis, it's a simple matter of adding "--coverage" to the gcc command line (for both compile and link flags).

However, there is ZERO documentation about how to generate coverage information for code that gets compiled to OpenCL kernels.

There seems to be no way to get "external" profiling data, and source code must be modified to include calls to clGetEventProfilingInfo wherever profiling data is desired.

Apparently this is a failure in the OpenCL Specification, so Altera is not to blame, but, ignoring the lack of profiling support is a huge omission - I'd call it a "Schoolboy error".

When will profiling support make it into the Specification, and be supported by Altera SDKs ?
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MAX 10 fails to run JTAG loaded SOF

August 1, 2017, 7:52 am
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I have run into an odd problem with a new board that has a Max 10 10M50SA FPGA on it. (Specifically, the 10M50SAE144)

The JTAG port appears to work, I can auto-detect the FPGA correctly, and Quartus even says that it downloaded my SOF correctly. There are no error messages in the log, etc. However, the device fails to run at all. I checked all of the obvious errors, such as clocks, resets, power, pin assignments, etc., but everything appears to be in order.

Then I decided to try and load SignalTap with a very simple design to verify basic functionality. Again, Quartus says it loaded the SOF correctly, but SignalTap can't find the integrated analyzer. I get "Invalid JTAG configuration" and "Instance not Found" as though I loaded nothing at all.

At this point I'm not sure if I have a bad chip or am simply doing something wrong. This is a single-supply device with all power (VCCONE and VCCIO) pins running at 3.3V. The JTAG port is wired according to the documentation with zener clamps and otherwise appears to function. At this point, even if the clock weren't working, I would still expect the analyzer core to show up, but I'm not sure what else to check. This is my first Max 10 design, and there are a lot of new options that I'm not used to from working with Cyclone and Stratix parts, so I'm hoping it's a configuration issue I have missed somehow.

Thanks for any help!
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