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measurement time delay problem in transceiver toolkit (tcl script)

August 1, 2017, 10:26 pm
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Hello,

I'm a beginner of quartus II programming.
I have a time delay problem when I measured eye diagram in transceiver toolkit using a for loop.
I think it is because of memory use.
I want to measure eye as soon as possible at a constant time interval.
Is there any tcl commands for clearing the memory in for loop?

Thank you.
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PLL and ADC in Max 10

August 1, 2017, 11:12 pm
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hi all
i have a problem to use the ADC in my design.
the main clock in my design insert from Pin Number J16, when i'm trying to insert the ADC to my design i have to use also on PLL.
during the synthesis i got an error massage "can't route from pin .... to atom ..."
when i'm trying to synthesis with pin clock M8 it is working ok (i cant change my design ...).
there is a solution for it?


thanks.
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The problem is a high level on the pins when the FPGA is turned on ep1с3т100с8n

August 2, 2017, 12:03 am
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Good day.
In the finished product, which has been produced for a long time, they found a problem when supplying power to cyclone ep1с3т100с8n at the outputs a short high level of 3.3 V, even before the configuration was started. Is this normal and something can be done about it? Thank you.
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Arria 10 IBIS zip file from here is not extarcted

August 2, 2017, 12:26 am
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Nco ip

August 2, 2017, 2:55 am
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I am using a STREAM board connected to an RF board.
My project goal is to simply send the digital signal generated by NCO IP in Quartus to the RF board through SPI communication through DAC and check the corresponding signal in the transmitter in the spectrum analyzer.
First, I created a specific digital signal using NCO IP.
My curiosity here is twofold.
1. There are several files created with NCO IP, but I do not know which files to use.
2. Is DAC possible with VERILOG programming?


I will wait for your answers.
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Cyclone IV DE2i150 GPIO output impedance

August 2, 2017, 3:43 am
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Hi,
I will couple a led driver Cyclone IV DE2i150 but I need Cyclone IV DE2i150 GPIO output impedance.
Could you help me?
Thank you.
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Testbench Events in ModelSim-Altera Starter Edition

August 2, 2017, 6:54 am
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Hello, quick question for the forum members. Are events supported in ModelSim-Altera Starter Edition?

Thanks,
Joe
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Multiply Accumulate in dsp builder advanced blocksets

August 2, 2017, 7:04 am
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Hi all,
Has anyone used dsp builder advanced blocksets ? Please help me about Multiply Accumulate. Thank you !
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Missing PCIe data

August 2, 2017, 7:15 am
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Hi, All!


I have a PCIe system. RC is Terasic CV GX board, EP is Altera CV GT board.


I write test data (inc counter value) from RC NiosII through simple DMA controller to RC Txs port, data go out EP BAR0 port and is written to EP onchip ram. Then I read from RC NiosII through RC Txs -> EP BAR0 the data from EP RAM. This memory check works fine, I check the written data and read back data it in RC NiosII.


1. When I change the destination address from EP onchip RAM to EP PCIe TXs port (send data not to EP RAM from EP BAR but directly to EP TXs Port), I see that data on EP BAR0 AVL master port are not the same, one word may be missing in burst packet (see attachment).

2. During configuration I set RC ATT and EP BAR with the same value. What is the purpose of the RC BAR and EP ATT?
I do nothing with them and the system works (to say nothing of missing words)

Thanks in advance!
Attached Images
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[DSE] Running a compilation on a remote farm through SSH

August 1, 2017, 10:09 pm
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Hello. For quite some time I've been trying to setup a compilation in Design Space Explorer, using a remote farm and SSH (two windows and cygwins) over just an ethernet cable. I've been using this: http://quartushelp.altera.com/15.0/mergedProjects/optimize/dse/dse_pro_running_remote_comp_ssh.htm<br><br>Yet seems like no matter what I do, I always receive this error: [dse.png attachement] The 'cat' part means that the 'cat' command is not recognized but I can't fix it.

This is my setup, I've tried different things: [dse2.png attachement] Any idea what might be causing this? I've tried running the agent. When using SSH through cygwins, everything seems to be fine, encrypted keys or not. This is also new to me. Is there any detailed tutorial or a working example for this?
Attached Images
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output doesn't toggle when simulating with other entities in Modelsim

August 2, 2017, 6:31 am
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Hi, I'm working on a vhdl testbench to simulate the behaviour of an I2C bus. I started with an original code (written in verilog) that works, made some changes to it an simulate it's behaviour as a stand-alone module using the .do file:

Code:
# I2C HPS
add wave -noupdate -label hps_sclk /I2C_to_GPIO/hps_sclk
add wave -noupdate -label hps_sda /I2C_to_GPIO/hps_sda_i
add wave -noupdate -label hps_sda_o_e /I2C_to_GPIO/hps_sda_o_e
# parallel store
add wave -noupdate -label gpio_input_reg /I2C_to_GPIO/gpio_input_reg
add wave -noupdate -label exph_input_reg /I2C_to_GPIO/exph_input_reg
add wave -noupdate -label expl_input_reg /I2C_to_GPIO/expl_input_reg
# inputs
add wave -noupdate -label gpio_input /I2C_to_GPIO/gpio_input
add wave -noupdate -label exp_input /I2C_to_GPIO/exp_input
# read/write byte count
add wave -noupdate -label hps_data_count_rd /I2C_to_GPIO/hps_data_count
# parallel store
add wave -noupdate -label gpio_output_pre /I2C_to_GPIO/gpio_output_pre
add wave -noupdate -label exph_output_pre /I2C_to_GPIO/exph_output_pre
add wave -noupdate -label expl_output_pre /I2C_to_GPIO/expl_output_pre
# outputs
add wave -noupdate -label gpio_output /I2C_to_GPIO/gpio_output
add wave -noupdate -label exp_output /I2C_to_GPIO/exp_output
add wave -noupdate -label dc_pwren /I2C_to_GPIO/dc_pwren
# i2c hps flags
add wave -noupdate -label hps_read_oper /I2C_to_GPIO/hps_read_oper
add wave -noupdate -label hps_data_or_address /I2C_to_GPIO/hps_data_or_address
add wave -noupdate -label hps_done /I2C_to_GPIO/hps_done
add wave -noupdate -label ack_flag /I2C_to_GPIO/ack_flag
add wave -noupdate -label hps_count /I2C_to_GPIO/hps_count
add wave -noupdate -label hps_sda_is_ack /I2C_to_GPIO/hps_sda_is_ack

# clock
force -freeze sim:/I2C_to_GPIO/hps_sclk 1 25, 0 {75 ns} -r 100

force -drive sim:/I2C_to_GPIO/gpio_input 00100010 0
force -drive sim:/I2C_to_GPIO/exp_input 0110101100 0

#######################################################################
#      write
#######################################################################
# start pulse high
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 25
run 50
# start 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 150
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 200
# 1 1 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 300
# write and wait ack
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0 -cancel 100
run 200
# 0 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 200
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0 0 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 300
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0 and wait ack
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0 -cancel 100
run 200
# 1 1 1 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 400
# 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 100
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 100
# 1 and wait ack
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0 -cancel 100
run 200
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 100
# 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 100
# 0
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0
run 100
# 1 1
force -drive sim:/I2C_to_GPIO/hps_sda_i 1 0
run 200
# 0 0 and wait ack
force -drive sim:/I2C_to_GPIO/hps_sda_i 0 0 -cancel 200
run 2000
When using the module - do file combination, it seemed to be working properly, so I moved ahead and added an I2C master entity to the bus, added a stimulus entity and a test-bench for connecting the units:

Code:
-- I omitted definition and architecture.. --
begin

  slave: I2C_to_GPIO port map (
    hps_sda_i        =>    sda,
    hps_sda_o_e        =>    sda_o_e,   
    hps_sclk        =>    scl,   
    gpio_input        =>    gpio_input,
    gpio_output    =>    gpio_output,
    write_pulse        =>    write_pulse,
    exp_input        =>    exp_input,
    exp_output        =>    exp_output,
    dc_pwren        =>    dc_pwren,
    state            =>    gpio_state ;)                // had to add this output bc sda_o_e wouldn't toggle
 
  master: i2c_master port map (
    clk        =>  clock, 
    reset_n    =>  reset_n,
    ena        =>  ena,   
    addr        =>  addr,   
    rw          =>  rw,     
    data_wr    =>  data_wr, -- data to write to slave
    busy        =>  busy,   
    data_rd    =>  data_rd, -- data read from slave
    ack_error  =>  ack_error,
    sda_i      =>  sda, 
    scl        =>  scl,
    mem_present =>  mem_present);


  stimulus_tb: stimulus port map (
    clock      => clock,
    reset_n    => reset_n,
    ena        => ena,
    addr        => addr,
    rw          => rw,   
    data_wr    => data_wr,
    scl        => scl,
    sda        => sda,
    sda_o_e        => sda_o_e,
    mem_present => mem_present,   
    start_reg  => start,
    cmd        => cmd,
    rst_n      => reset);
   
end;
The problem when using the former, is that the output hps_sda_o_e from I2C_to_GPIO entity wasn't toggling, even when I run using break points to the lines were it should, I even disconnected it from stimulus' 'sda_o_e' to make sure that there was nothing driving it, toggle the logic of the output, but still no toggling.. Finally, I added the 'state' output and made state change to a unique value every time sda_o_e was supposed to toggle. Since state did change, I set hps_sda_o_e to be the msb from state and this did the trick, I include the proccess in I2C_to_GPIO.v were hps_sda_o_e is driven:

Code:
/***********************************************************************************************************/
/* Sending the read data */
always@(negedge hps_sclk)
    if (hps_start_stop) begin
            gpio_input_reg <= gpio_input_reg[7:0];
            exph_input_reg <= exph_input_reg[7:0];
            expl_input_reg <= expl_input_reg[7:0];   
               
        if (~ack_flag) begin
            if ( hps_add_is_matching & ~hps_write_flag) begin
                sda_oe <= 1'b1;
                state <= 8'h81;              //
            end else begin
                sda_oe <= 1'b0;
                state <= 8'h02;            //
            end
            if (hps_read_oper & hps_data_or_address) begin
                    gpio_input_reg[7:0] <= gpio_input[7:0];
                    exph_input_reg[7:0] <= {6'b111111,exp_input[9:8]};
                    expl_input_reg[7:0] <= exp_input[7:0];   
            end
        end else if (hps_read_oper & hps_data_or_address & ~hps_done) begin
            if (ack_flag) begin
                    if (hps_data_count == 2'h2) begin                            // GPIO data input
                          if (~gpio_input_reg[7]) begin
                              sda_oe <= 1'b1;
                              state <= 8'h83;        //
                          end else begin
                              sda_oe <= 1'b0;
                              state <= 8'h03;        //
                          end
                          gpio_input_reg <= {gpio_input_reg[6:0], 1'b0};
                    end else if (hps_data_count == 2'h1) begin                // IO EXP to RDC D10 D9 data output
                       
                          if (~exph_input_reg[7]) begin            // todo change registers format to make it easier
                                sda_oe <= 1'b1;
                                state <= 8'h84;        //
                        end else begin
                                sda_oe <= 1'b0;
                                state <= 8'h04;        //
                          end
                          exph_input_reg <= {exph_input_reg[6:0], 1'b0};
                    end else if (hps_data_count == 2'h0) begin                // IO EXP to RDC D8 D1 data output
                       
                          if (~expl_input_reg[7]) begin            // todo change registers format to make it easier
                                sda_oe <= 1'b1;
                                state <= 8'h85;        //
                          end else begin
                                sda_oe <= 1'b0;
                                state <= 8'h05;        //
                          end
                          expl_input_reg <= {expl_input_reg[6:0], 1'b0};
                    end
            end else begin
                state <= 8'h06;        //
                sda_oe <= 1'b0;
            end
    end else
        state <= 8'h07;       
        sda_oe <= 1'b0;
    end// if (start_stop)


assign write_pulse = write_to_port_r;
assign sda_o_e = state[7];                    // changed from assign sda_o_e = sda_o_e;
Definitions:

Code:
module I2C_to_GPIO
(
  hps_sda_i,
  hps_sda_o_e,
  hps_sclk,
  gpio_input,
  gpio_output,
  write_pulse,
  exp_input,
  exp_output,
  dc_pwren,                                           
  state                                                // added to toggle the hps_sda_o_e output
);
---
output hps_sda_o_e;                        // Output enable HPS_SDA= '0' when '0'
output [7:0] state = 8'h00;                        // debug

---
reg hps_sda_oe = 1'b0;                                // set default value
reg [7:0] state = 8'h00;                        // debug
I want to know if this behavior is due to something that I'm missing and what could I do to prevent it. Thanks in advance!
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Hard IP for PCIe gen 3 simulation on Arria 10

August 2, 2017, 2:46 pm
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I've successfully run simulations of a gen 1 interface, but I am having real troubles doing a gen 3 sim. I'm using the Avalon streaming core for an endpoint application. I've created a testbench system through Qsys. When I run the simulation in ModelSim-Intel FPGA, I see the LTSSM states go through detect, polling, config, recovery, and then lo, but that's it. I see no activity on the streaming interface. I think I'm missing a driver for the root port BFM. For a gen 1 sim, I used the altpcietb_bfm_driver_chaining.v file from the DMA design example as the driver. I thought this same driver was included in altpcietb_bfm_rp_gen3_x8.sv automatically generated by Qsys.

I'm also not sure how to customize the testbench driver (if I can find it). All I want to do is try writing and reading BAR0, but I'm not sure where to put in the functions for this as they are described in the user guide.

I am not a PCIe expert by any means, so I'd appreciate any advice or hints anybody might have about doing this.
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MaxPlus

August 2, 2017, 3:22 pm
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Suddenly this morning my MAXplusII software quit running mid project. it has a box that says invalid authorization code. It has been installed with the same software sentinel for probably 20 years. Any thoughts as to how to make it run again?
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Need help capturing the period of a wave form. (Verilog)

August 2, 2017, 8:59 pm
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My code requires that I store the value of an input signal's period in a register. I have mocked up the code below to register the period, but I cant yet confirm that it works. In your experience do you see anything that is immediately wrong with it. I am trying to learn how to use modelsim at the moment please forgive me. Sys_clk is a 50MHz clock, and the in_signal I am working with right now is 2Hz but that may change.
Desired Inputs: System Clock, RST from controller, a signal of unknown frequency and duty cycle that is less than 50MHz(the freq is constant).
Desired Output: A registered period value in decimal form

<!-- language: verilog -->module t_sampler(input wire in_signal, input sys_clk, output reg [31:0] total_T);reg [31:0] pos_length;reg [31:0] neg_length;reg pos_cntstop;reg neg_cntstop;always @(posesge sys_clk)beginif(in_signal)begin pos_length <= pos_length +1;endelsebegin pos_length <= pos_length; pos_cntstop <=1;endif(!in_signal)begin neg_length <= neg_length +1;endelsebegin neg_length <= neg_length; neg_cntstop <=1;endif(neg_cntstop && pos_cntstop)begin total_T <= neg_length + pos_length; neg_cntstop <=0; neg_length <=0; pos_cntstop <=0; pos_length <=0;endendendmodule
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max10 clock

August 3, 2017, 4:38 am
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I am quite new in this, do max10 require external clocking ? Iam using 10M50DAF484C8G. If need which pins should be connected to external clock ?
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FPGA to NIOS connection : counter value from FPGA print in NIOS

August 3, 2017, 8:33 am
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Hello,

I have a counter which updates at clock edge of 50Mhz frequency, which I send to Nios via PIO and print the value.

But the print output is not expected, it is random, where as it suppose to be 1,2,3,....256 but it appears to be any number between 1 to 256 i.e. not in sequence.

Is there a problem in sync?

Secondly, I want to send this counter value on RS232, but it can be sent bit wise bit, does that implies I need to stop transmitting when RS232 is busy? But the counter is incrementing in every 50 Mhz so how to handle it?


Please let me know how to proceed?

Thank you
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How to set up shared on-chip memory

August 3, 2017, 10:33 am
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Hi, using Cyclone V with HPS.

I have a custom Verilog module which needs to have its own registers, as well as read/write access to 1kByte of on-chip memory. The Linux side also needs to have access to both the module's registers and the on-chip memory.

I'm able to get the module's registers memory mapped in Linux and can read/write them, using the Avalon interface.
I assume I can get on-chip memory to be memory-mapped in Linux too, at a different base address.
However I'm not sure where to begin with getting my module to read/write on-chip memory.

I'd like to just use the Verilog array syntax, like read_data <= my_memory[addr] or my_memory[addr] <= write_data, where my_memory is the shared on-chip 1kB memory.
I'd prefer not to have to write Avalon master logic, eg controlling chip selects, read/write signals, etc., from my module to access the shared memory, just the Verilog array syntax.
Is this possible?

Can someone please provide an overview or point to an example of how to have a custom module access on-chip memory which is shared with the Linux side?

thanks
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can't false path PLL input clock

August 3, 2017, 12:26 pm
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I am getting a setup delay in my design, but the path includes the clock10 input transition time and all the time in the PLL. None of this should matter since everything is driven by the output clock.

8.33 0.00 source latency
8.33 0.00 1 PIN_H13 clk10
8.33 0.00 RR IC 1 IOIBUF_X38_Y61_N1 clk10~input|i
9.51 1.18 RR CELL 3 IOIBUF_X38_Y61_N1 clk10~input|o
10.33 0.82 RR IC 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0]
10.66 0.33 RR CELL 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout
10.66 0.00 RR IC 10 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin
5.81 -4.85 RR COMP 2 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
5.81 0.00 RR IC 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]
7.55 1.74 RR CELL 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
8.69 1.14 FF IC 1 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|inclk
9.01 0.32 FF CELL 7431 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|outclk

I have false pathed the input clock but the tool seems to ignore this.
set_false_path -from [get_ports {clk10}] -to [get_clocks {main_clk}]

How do I make it ignore this delay?
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USB Blaster II Active Serial Programming Issues

August 3, 2017, 3:09 pm
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Hello,

We have recently upgraded our programming cables from the USB Blaster to the USB Blaster II. We have installed the drivers without issue and are running Quartus Prime 16.0. JTAG programming is successful, and verification is successful too, but not after first having to step the frequency from 500kHz all the way back up to 24MHz. However, when we try and program through the Active Serial mode, the quartus programmer gives the error message "Active Serial programming not supported with currently selected hardware". After reviewing the documentation, it appears the Blaster II should be able to support this.

Does anyone have any idea what is going on or how to fix this issue?

Thanks
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Trouble hardcoding an initial value of flip-flop on power up.

August 3, 2017, 4:28 pm
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Hi All,

I'm using a Max 10 FPGA.

I'm having trouble instantiating a d flip flop initially set to '1'.

From the altera.altera_primitives_components.all I am instantiating the following:

component dff
port (
D : in std_logic; -- Data Input
CLK : in std_logic; -- 100 MHz clock
CLRN : in std_logic; -- Clear Input
PRN : in std_logic; -- Preset Input
Q : out std_logic -- Output Data
);
end component;

But there is no generic that let's me hardcore a '1' there?

I want to shift in 0's when the power is recycled (by tying the pin to ground) and
so I need the initial value of the register to power up to '1'.

Thank you for your help.

Bryan Kerr
Electronics Engineer
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