↧
Certified translation
↧
Recursion in OpenCL
Correct me if I'm wrong, as far as I know FPGA should be able to run recursive algorithm since you can write recursion in Verilog.
But OpenCL was mostly meant for GPU in the beginning so there's the restriction that you can't write recursion in kernels.
Intel FPGA SDK guide mentioned the restriction was not enforced by the offline compiler, I don't have means to test it right now but does that mean we can do recursion using OpenCL for Altera FPGA? Thanks
But OpenCL was mostly meant for GPU in the beginning so there's the restriction that you can't write recursion in kernels.
Intel FPGA SDK guide mentioned the restriction was not enforced by the offline compiler, I don't have means to test it right now but does that mean we can do recursion using OpenCL for Altera FPGA? Thanks
↧
↧
LFSR doesn't generate random values during simulation Ask
I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim.
Here is the link https://stackoverflow.com/questions/...35100_45486770 to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.
Here is the link https://stackoverflow.com/questions/...35100_45486770 to the original question as I cannot post the code and problem in here as it exceeds the allowed character length.
↧
Arria V GT Development Kit Transceiver Toolkit and SMA
I'm currently running Quartus Prime 16.0 measuring bit error rates (loopback method) using the Transceiver toolkit with PRBS32. With Qsys, I can the use a custom phy to get up to 6.5 Gbps on 8 channels on the HSMC connector. I would like to use a test for the SMA Transceiver for 10G and eventually the bullseye connectors. Would I have to write my own set of blocks with the data checker, generator, reconfig controller, and the Arria V Native PHY IP to run at 10 Gbps in addition to tcl script a new GUI to emulate the Transceiver Toolkit since Qsys doesn't go higher than 6.5 Gbps? If that is the case, I haven't seen an example design utilizing the bullseye connector and SMA xcvr for higher data rates. I haven't looked into procuring the Board Test System yet but I would like to utilize the export data feature when Auto-Sweeping in the toolkit. Just wanted to see if the approach is to write my own blocks and verify with my own custom GUI generated from TCL scripts on System Console. Any guidance is appreciated!
↧
New Open-Source Image Processing Project
Hello all,
I have started an open-source project at https://github.com/electro-logic/CameraVision for doing Image Processing with FPGA.
At this stage I have a working and commented hardware / firmware / software that interface FPGA with Omnivision CMOS Image Sensor Camera OV8865 mounted on Terasic D8M module.
![]()
FPGA handle data from and to the image sensor using custom hardware module with Avalon Interface and NIOS II soft-cpu for sending data to pc. I managed to reach full image sensor resolution (8 MegaPixel). In my blog there are some details http://electro-logic.blogspot.it and soon more will follow.
Some algorithms like demosaicing and color correction are implemented in software but I hope to implement it in FPGA soon with other higher-level algorithms of computer vision.
If you like Image Processing and FPGA you are welcome to contribute to the project.
Thank you
Leonardo
PS: I have working DE1-Soc and BeMicro CV A9 (using DDR3) version of the project, if you have these boards instead of DE0-Nano let me know.
I have started an open-source project at https://github.com/electro-logic/CameraVision for doing Image Processing with FPGA.
At this stage I have a working and commented hardware / firmware / software that interface FPGA with Omnivision CMOS Image Sensor Camera OV8865 mounted on Terasic D8M module.
FPGA handle data from and to the image sensor using custom hardware module with Avalon Interface and NIOS II soft-cpu for sending data to pc. I managed to reach full image sensor resolution (8 MegaPixel). In my blog there are some details http://electro-logic.blogspot.it and soon more will follow.
Some algorithms like demosaicing and color correction are implemented in software but I hope to implement it in FPGA soon with other higher-level algorithms of computer vision.
If you like Image Processing and FPGA you are welcome to contribute to the project.
Thank you
Leonardo
PS: I have working DE1-Soc and BeMicro CV A9 (using DDR3) version of the project, if you have these boards instead of DE0-Nano let me know.
↧
↧
a problem of PCIe on Cyclone V GT Dev Kit
Hello,
I'm trying to use the PCI Express Avalon-ST DMA reference design (https://www.altera.com.cn/products/reference-designs/all-reference-designs/interface/ref-pciexpress-hp.html)，the kit is Cyclone V GT Development kit，but I'm having some troubles with the Linux driver.
I have followed the user manual step by step, but the PC still can't identify the development kit，The PCI express edge connector on development kit is X4 mode，Is it possible to insert a PC's x16 slot？
Im stuck for week right now, reading and looking for the right information...
I'm trying to use the PCI Express Avalon-ST DMA reference design (https://www.altera.com.cn/products/reference-designs/all-reference-designs/interface/ref-pciexpress-hp.html)，the kit is Cyclone V GT Development kit，but I'm having some troubles with the Linux driver.
I have followed the user manual step by step, but the PC still can't identify the development kit，The PCI express edge connector on development kit is X4 mode，Is it possible to insert a PC's x16 slot？
Im stuck for week right now, reading and looking for the right information...
↧
RapidIO II IP core with management module disabled
I have instantiated a RapidIO II IP core and unchecked the "Enable Maintenance module" checkbox. For some reason, the maintenance module Avalon-MM master port (mnt_master) still exists in the instantiated IP. Is there a reason for this? I just want to make sure that I do not need to implement something in my logic to interact with this port. I do not plan on using maintenance requests in my implementation.
FWIW, I am using a Cyclone V SX SoC. I am using Altera Quartus II SJ 15.0.2 and implementing my design (along with this IP core) in Qsys.
FWIW, I am using a Cyclone V SX SoC. I am using Altera Quartus II SJ 15.0.2 and implementing my design (along with this IP core) in Qsys.
↧
openCL memory error
Hello,
This is my first thread, I´m new at openCL and I´m doing some work to integrate this technology with some other software. So I´m trying to execute an aocx inside another program written in C++. When my code reaches this line
program = clCreateProgramWithBinary(context, 1, &device, (const size_t *)&binary_size, (const unsigned char **)&binary_buf, &binary_status, &status_ocl);
returns this error: *** Error in `../../bin/linux-arm/hpsfpga1dtest': munmap_chunk(): invalid pointer: 0x00294a98 ***
I haven´t found any help from google and I´m a bit lost. My aocx file runs in an ARM/FPGA SoC system from Intel/Altera and was cross-compiled in another host. If Iexecute it directly:
aocl program /dev/acl0 hello_world.aocx
It returns this:
aocl program: Running reprogram from /root/opencl_arm32_rte/board/c5soc/arm32/bin
Reprogramming was successful!
Can anyone tell why I receive this error? Maybe it is something to be with my own program, but I would need an explanation of this issue, thanks!!
Regards, Ricardo
This is my first thread, I´m new at openCL and I´m doing some work to integrate this technology with some other software. So I´m trying to execute an aocx inside another program written in C++. When my code reaches this line
program = clCreateProgramWithBinary(context, 1, &device, (const size_t *)&binary_size, (const unsigned char **)&binary_buf, &binary_status, &status_ocl);
returns this error: *** Error in `../../bin/linux-arm/hpsfpga1dtest': munmap_chunk(): invalid pointer: 0x00294a98 ***
I haven´t found any help from google and I´m a bit lost. My aocx file runs in an ARM/FPGA SoC system from Intel/Altera and was cross-compiled in another host. If Iexecute it directly:
aocl program /dev/acl0 hello_world.aocx
It returns this:
aocl program: Running reprogram from /root/opencl_arm32_rte/board/c5soc/arm32/bin
Reprogramming was successful!
Can anyone tell why I receive this error? Maybe it is something to be with my own program, but I would need an explanation of this issue, thanks!!
Regards, Ricardo
↧
HPS boot from SDCARD with pins routed to FPGA
Hello,
Does anybody could help me telling if is it possible to boot HPS from SDCARD (bootsel = 0x05), with SDCARD pins routed to FPGA (assume FPGA is already configured when HPS boot). I supposed it is possible, since at Qsys, on HPS peripheral pins configuration tab SDIO pin accepts FPGA (Full mode) and HPSI/O Set 0 options.
Does anybody here have already boot HPS from an SDCARD this way?
I know that some logic is necessary at FPGA side to deal with bidirectional pins (Data and CMD) but since HPS export the output_enables, it is not complicated to be done.
Thank you in advance,
Lucas
Does anybody could help me telling if is it possible to boot HPS from SDCARD (bootsel = 0x05), with SDCARD pins routed to FPGA (assume FPGA is already configured when HPS boot). I supposed it is possible, since at Qsys, on HPS peripheral pins configuration tab SDIO pin accepts FPGA (Full mode) and HPSI/O Set 0 options.
Does anybody here have already boot HPS from an SDCARD this way?
I know that some logic is necessary at FPGA side to deal with bidirectional pins (Data and CMD) but since HPS export the output_enables, it is not complicated to be done.
Thank you in advance,
Lucas
↧
↧
Unable to simulate altshift_taps, "too few port connections"
I have taken the Terasic TRDB D5M 5MP camera reference design for the Altera DE2-115 development board and written a testbench with a basic model for the camera to send pixel data. When I start the simulation I get the following warnings:
# ** Warning: (vsim-3017) ../v/Line_Buffer.v(74): [TFMPC] - Too few port connections. Expected 7, found 6.
# Time: 0 ps Iteration: 0 Instance: /ccd_capture_tb/dut_rgb2raw/L1/ALTSHIFT_TAPS_component File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) ../v/Line_Buffer.v(74): [TFMPC] - Missing connection for port 'sclr'.
The Line_Buffer.v contains instance of altshift_taps.
The file is attached to this post. I do not understand why this warning is being generated. I am using ModelSim 10.5b that came with download of Quartus Prime 16.1. I opened the design in Quartus Prime and regenerated all the IP files as well to they are up to date.
# ** Warning: (vsim-3017) ../v/Line_Buffer.v(74): [TFMPC] - Too few port connections. Expected 7, found 6.
# Time: 0 ps Iteration: 0 Instance: /ccd_capture_tb/dut_rgb2raw/L1/ALTSHIFT_TAPS_component File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/altera_mf.v
# ** Warning: (vsim-3722) ../v/Line_Buffer.v(74): [TFMPC] - Missing connection for port 'sclr'.
The Line_Buffer.v contains instance of altshift_taps.
The file is attached to this post. I do not understand why this warning is being generated. I am using ModelSim 10.5b that came with download of Quartus Prime 16.1. I opened the design in Quartus Prime and regenerated all the IP files as well to they are up to date.
↧
NAND U-Boot for Arria10 Soc Development Kit stucks
Hi Everybody,
I'm using GSRD 16.1 and EDS 16.1 on Fedora 25 (64bit) OS.
Using the procedure described at https://rocketboards.org/foswiki/Doc...srd161NandBoot, I built a U_BOOT for NAND, while keeping the prebuilt binaries untouched but it doesn't come up.
Replacing my U-BOOT with the prebuilt U-BOOT - and it works fine.
On the other hand,
Replacing the daughterboard with the microSD daughterboard:
Building my U-BOOT for microSD and using the associated procedures in http://www.alterawiki.com/wiki/SoCEDSGettingStarted, everything works smoothly.
I'm attaching a log for the NAND buildup.
Any clues?
I'm using GSRD 16.1 and EDS 16.1 on Fedora 25 (64bit) OS.
Using the procedure described at https://rocketboards.org/foswiki/Doc...srd161NandBoot, I built a U_BOOT for NAND, while keeping the prebuilt binaries untouched but it doesn't come up.
Replacing my U-BOOT with the prebuilt U-BOOT - and it works fine.
On the other hand,
Replacing the daughterboard with the microSD daughterboard:
Building my U-BOOT for microSD and using the associated procedures in http://www.alterawiki.com/wiki/SoCEDSGettingStarted, everything works smoothly.
I'm attaching a log for the NAND buildup.
Any clues?
↧
retrieve all generated clocks related to a giving reference clock
Hi all
does anyone know how to retrieve the generated clocks derived from a giving clock ? In vivado, they have something
like get_clock -include_generated_clock refclk.
thanks
does anyone know how to retrieve the generated clocks derived from a giving clock ? In vivado, they have something
like get_clock -include_generated_clock refclk.
thanks
↧
OPENCL diagnose acl0 : Copying 4095 MB of Global Memory : can we reduce the size
Hi All,
For the quicker results I wanted change the amount of data copied to global memory by changing the size of buffer In ol.cpp file in ~/sample_driver/source/util/diagnostic . But tried changing max_size and other variables but In vain .
Can you please let me know if we a do something.
Thanks,
rnivart
For the quicker results I wanted change the amount of data copied to global memory by changing the size of buffer In ol.cpp file in ~/sample_driver/source/util/diagnostic . But tried changing max_size and other variables but In vain .
Can you please let me know if we a do something.
Thanks,
rnivart
↧
↧
aocl diagnose acl0 + hangs at pcie_cra_write64 functon
Hi All ,
We are building the custom platform and while testing OS kernel hangs in sampledriver pcie_cra_write64. How can we fix this issue ?
We are building the custom platform and while testing OS kernel hangs in sampledriver pcie_cra_write64. How can we fix this issue ?
↧
error : selected device has 126 RAM location(s) of type M9k.
I made the signal with NCO IP. We then testbench the signal. First, I added .sip and .qip files to the project and compiled the following code. But I got an error and I do not know why.
![]()
![]()
↧
Licensing question
Should I be able to install and run the Quartus Prime Standard edition if a license for Quartus Prime Pro is setup on my network?
Thanks,
Matt
Thanks,
Matt
↧
FPGA to NIOS connection : counter value from FPGA print in NIOS
Hello,
I have a counter which updates at clock edge of 50Mhz frequency, which I send to Nios via PIO and print the value.
But the print output is not expected, it is random, where as it suppose to be 1,2,3,....256 but it appears to be any number between 1 to 256 i.e. not in sequence.
Is there a problem in sync?
Secondly, I want to send this counter value on RS232, but it can be sent bit wise bit, does that implies I need to stop transmitting when RS232 is busy? But the counter is incrementing in every 50 Mhz so how to handle it?
Please let me know how to proceed?
Thank you
I have a counter which updates at clock edge of 50Mhz frequency, which I send to Nios via PIO and print the value.
But the print output is not expected, it is random, where as it suppose to be 1,2,3,....256 but it appears to be any number between 1 to 256 i.e. not in sequence.
Is there a problem in sync?
Secondly, I want to send this counter value on RS232, but it can be sent bit wise bit, does that implies I need to stop transmitting when RS232 is busy? But the counter is incrementing in every 50 Mhz so how to handle it?
Please let me know how to proceed?
Thank you
↧
↧
How to set up shared on-chip memory
Hi, using Cyclone V with HPS.
I have a custom Verilog module which needs to have its own registers, as well as read/write access to 1kByte of on-chip memory. The Linux side also needs to have access to both the module's registers and the on-chip memory.
I'm able to get the module's registers memory mapped in Linux and can read/write them, using the Avalon interface.
I assume I can get on-chip memory to be memory-mapped in Linux too, at a different base address.
However I'm not sure where to begin with getting my module to read/write on-chip memory.
I'd like to just use the Verilog array syntax, like read_data <= my_memory[addr] or my_memory[addr] <= write_data, where my_memory is the shared on-chip 1kB memory.
I'd prefer not to have to write Avalon master logic, eg controlling chip selects, read/write signals, etc., from my module to access the shared memory, just the Verilog array syntax.
Is this possible?
Can someone please provide an overview or point to an example of how to have a custom module access on-chip memory which is shared with the Linux side?
thanks
I have a custom Verilog module which needs to have its own registers, as well as read/write access to 1kByte of on-chip memory. The Linux side also needs to have access to both the module's registers and the on-chip memory.
I'm able to get the module's registers memory mapped in Linux and can read/write them, using the Avalon interface.
I assume I can get on-chip memory to be memory-mapped in Linux too, at a different base address.
However I'm not sure where to begin with getting my module to read/write on-chip memory.
I'd like to just use the Verilog array syntax, like read_data <= my_memory[addr] or my_memory[addr] <= write_data, where my_memory is the shared on-chip 1kB memory.
I'd prefer not to have to write Avalon master logic, eg controlling chip selects, read/write signals, etc., from my module to access the shared memory, just the Verilog array syntax.
Is this possible?
Can someone please provide an overview or point to an example of how to have a custom module access on-chip memory which is shared with the Linux side?
thanks
↧
can't false path PLL input clock
I am getting a setup delay in my design, but the path includes the clock10 input transition time and all the time in the PLL. None of this should matter since everything is driven by the output clock.
8.33 0.00 source latency
8.33 0.00 1 PIN_H13 clk10
8.33 0.00 RR IC 1 IOIBUF_X38_Y61_N1 clk10~input|i
9.51 1.18 RR CELL 3 IOIBUF_X38_Y61_N1 clk10~input|o
10.33 0.82 RR IC 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0]
10.66 0.33 RR CELL 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout
10.66 0.00 RR IC 10 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin
5.81 -4.85 RR COMP 2 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
5.81 0.00 RR IC 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]
7.55 1.74 RR CELL 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
8.69 1.14 FF IC 1 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|inclk
9.01 0.32 FF CELL 7431 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|outclk
I have false pathed the input clock but the tool seems to ignore this.
set_false_path -from [get_ports {clk10}] -to [get_clocks {main_clk}]
How do I make it ignore this delay?
8.33 0.00 source latency
8.33 0.00 1 PIN_H13 clk10
8.33 0.00 RR IC 1 IOIBUF_X38_Y61_N1 clk10~input|i
9.51 1.18 RR CELL 3 IOIBUF_X38_Y61_N1 clk10~input|o
10.33 0.82 RR IC 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkin[0]
10.66 0.33 RR CELL 1 PLLREFCLKSELECT_X68_Y60_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT|clkout
10.66 0.00 RR IC 10 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin
5.81 -4.85 RR COMP 2 FRACTIONALPLL_X68_Y54_N0 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
5.81 0.00 RR IC 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]
7.55 1.74 RR CELL 1 PLLOUTPUTCOUNTER_X68_Y53_N1 PLL0|main_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
8.69 1.14 FF IC 1 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|inclk
9.01 0.32 FF CELL 7431 CLKCTRL_G13 GB0|altclkctrl_0|Gclk_buf_altclkctrl_0_sub_compone nt|sd1|outclk
I have false pathed the input clock but the tool seems to ignore this.
set_false_path -from [get_ports {clk10}] -to [get_clocks {main_clk}]
How do I make it ignore this delay?
↧
USB Blaster II Active Serial Programming Issues
Hello,
We have recently upgraded our programming cables from the USB Blaster to the USB Blaster II. We have installed the drivers without issue and are running Quartus Prime 16.0. JTAG programming is successful, and verification is successful too, but not after first having to step the frequency from 500kHz all the way back up to 24MHz. However, when we try and program through the Active Serial mode, the quartus programmer gives the error message "Active Serial programming not supported with currently selected hardware". After reviewing the documentation, it appears the Blaster II should be able to support this.
Does anyone have any idea what is going on or how to fix this issue?
Thanks
We have recently upgraded our programming cables from the USB Blaster to the USB Blaster II. We have installed the drivers without issue and are running Quartus Prime 16.0. JTAG programming is successful, and verification is successful too, but not after first having to step the frequency from 500kHz all the way back up to 24MHz. However, when we try and program through the Active Serial mode, the quartus programmer gives the error message "Active Serial programming not supported with currently selected hardware". After reviewing the documentation, it appears the Blaster II should be able to support this.
Does anyone have any idea what is going on or how to fix this issue?
Thanks
↧