Hi everyone!
I've been trying to make noise filter for input mic as requested in Lab 12 but I've been having some really strange issues.
Lab link ftp://ftp.altera.com/up/pub/Altera_M...12_Verilog.pdf
So what I do is whenever I got input signal I divide it by 8 and write it in FIFO. On the output I always keep sum of all FIFO registers.
The strange thing that happens is, that it is working perfectly fine when I am not dividing by anything (Just outputing the sum of all registers), and when I am dividing by 8 I only get noise as the output.
Does anybody have any idea what might cause this issue ?
Here is my code in case you couldn't understand what I've been saying :D
So long story short, this outputs just random noise, and with this change
it works perfect.
Thanks everyone!
I've been trying to make noise filter for input mic as requested in Lab 12 but I've been having some really strange issues.
Lab link ftp://ftp.altera.com/up/pub/Altera_M...12_Verilog.pdf
So what I do is whenever I got input signal I divide it by 8 and write it in FIFO. On the output I always keep sum of all FIFO registers.
The strange thing that happens is, that it is working perfectly fine when I am not dividing by anything (Just outputing the sum of all registers), and when I am dividing by 8 I only get noise as the output.
Does anybody have any idea what might cause this issue ?
Here is my code in case you couldn't understand what I've been saying :D
Code:
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module noise_filter
#(
parameter DATA_WIDTH=24,
parameter N = 4
)
(
input write,
input clock,
input [DATA_WIDTH-1:0] data_in,
output done,
output [DATA_WIDTH-1:0] sum
);
reg [DATA_WIDTH-1:0] summed;
reg [N-1:0] counter;
reg isDone;
reg [DATA_WIDTH-1:0] fifo [0:2**N-1];
integer i;
initial
begin
counter = 0;
summed = 0;
isDone = 0;
for(i = 0; i < 2**N; i= i+1)
begin
fifo[i] = 0;
end
end
always @(posedge clock)
begin
if(isDone == 1)
begin
isDone <= 0;
end
else if(write == 1)
begin
counter <= counter + 1;
fifo[counter] <= {{N{1'b0}}, data_in[DATA_WIDTH-1:N]};
summed <= summed - fifo[counter] + data_in[DATA_WIDTH-1:N] ;
isDone <= 1;
end
end
assign sum = summed;
assign done = isDone;
endmoduleCode:
fifo[counter] <= data_in;
summed <= summed - fifo[counter] + data_in;Thanks everyone!