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Problem in using the same module in project for many times

August 15, 2017, 1:12 pm
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Hi everyone,

I am trying to use one module for several times in one project cause I want to control several ADCs using one main project.

And my way to do it is like this:
Code:
ADC ADC1(.RST2(RST2),.DOUT(DOUT1),.SCLK(SCLK1),.DIN(DIN1),.CLK(CLK),.OUTDATA(OUTDATA1));
ADC ADC2(.RST2(RST2),.DOUT(DOUT2),.SCLK(SCLK2),.DIN(DIN2),.CLK(CLK),.OUTDATA(OUTDATA2));
There are only some meaningless warnings when I run this program in quartus. What's more, I am sure that the ADC code works very well.

When I only use one ADC module, for example:
Code:
ADC ADC1(.RST2(RST2),.DOUT(DOUT1),.SCLK(SCLK1),.DIN(DIN1),.CLK(CLK),.OUTDATA(OUTDATA1));//ADC ADC2(.RST2(RST2),.DOUT(DOUT2),.SCLK(SCLK2),.DIN(DIN2),.CLK(CLK),.OUTDATA(OUTDATA2));
The result is perfect when I download it to my board. Same if I comments the second line.

However, if I am trying to control this two together, I cannot get good results from the board.

Is there any one can help me? Thank you very much!

Yours
Yonghang
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Quartus 17.0 Nios II IDE crashes

August 15, 2017, 5:39 pm
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In the Nios II IDE (Quartus 17.0), when I go to Debug Configurations->Target Connection and click on Refresh Connections, the program hangs. Has anyone else experienced this bug? Any suggestions?

Any advice is much appreciated!

Calvin
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Edimax USB WiFi dongle?

August 15, 2017, 10:41 am
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Hello all,
I am trying to use the Edimax USB WiFi dongle with my DE0-Nano-Soc board. I have used this dongle on my Raspberry Pi boards, so I thought this would be compatible as well.

I am using a USB hub to share both the Bluetooth and Wifi dongles. Upon booting, the Nano-SoC does see the dongle but does not obtain an IP address. ifconfig doesn't show wlan0 in its configuration.

I have read in other Altera forums that a driver may be needed? I have used this interface "driveless" on my Raspberry Pi with no problems. Also, it appears that the /etc/network/interfaces file is configured correctly. Has anyone successfully use a USB WiFi adapter with their Nano-soc board?

Thanks in advance for the help...

Here is an excerpt of the boot process:

usb 1-1: new high-speed USB device number 2 using dwc2
INIT: version 2.88 booting
usb 1-1: New USB device found, idVendor=05e3, idProduct=0608
usb 1-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
usb 1-1: Product: USB2.0 Hub
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 4 ports detected
Starting Bootlog daemon: bootlogd.
usb 1-1.3: new high-speed USB device number 3 using dwc2
Configuring network interfaces... usb 1-1.3: New USB device found, idVendor=7392, idProduct=7811
usb 1-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-1.3: Product: 802.11n WLAN Adapter
usb 1-1.3: Manufacturer: Realtek
usb 1-1.3: SerialNumber: 00e04c000001
wlan0: ERROR while getting interface flags: No such device
eth0: device MAC address 96:ca:7d:**:**:**
udhcpc (v1.20.2) started
usb 1-1.4: new full-speed USB device number 4 using dwc2
Sending discover...
usb 1-1.4: New USB device found, idVendor=0a12, idProduct=0001
usb 1-1.4: New USB device strings: Mfr=0, Product=2, SerialNumber=0
usb 1-1.4: Product: CSR8510 A10

Here is my /etc/network/interfaces file:

# /etc/network/interfaces -- configuration file for ifup(8), ifdown(8)


# The loopback interface
auto lo
iface lo inet loopback


# Wireless interfaces
iface wlan0 inet dhcp
wireless_mode managed
wireless_essid any
wpa-driver wext
wpa-conf /etc/wpa_supplicant.conf


iface atml0 inet dhcp


# Wired or wireless interfaces
auto eth0
iface eth0 inet dhcp
iface eth1 inet dhcp


# Ethernet/RNDIS gadget (g_ether)
# ... or on host side, usbnet and random hwaddr
iface usb0 inet static
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NIOS II Multi-Processor System's On-chip Memory

August 15, 2017, 9:59 pm
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Hi,

I was just wondering if anyone can help me in finding the answer of the following given question;

Q. Suppose we have a NIOS II Multi-Processor System and all the processors are executing a same set of instructions simultaneously, let's take an example of 5 cores in which one is master core and other four are slave cores. There is only ONE shared On-Chip memory for all the cores. If a master core declares an array of 1024 elements in its own code, how could the master core share the 'ADDRESS' of this array with other cores??

I want to split the declared array length among four cores equally so that each core can operate on the given subset of data, like in this case, 256 elements for each core.

So, simply I wanna know how can a NIOS II core share its variable or array location (address) with other cores so that they can make use of it??

Looking forward to hear from you soon. Thank you in advance..
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Connecting a PCIe board to a PC

August 16, 2017, 2:37 am
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Hello,

Suppose I have an Altera evaluation board with an integrated PCIe connector.
The board is connected to the PC, it's powered on, but isn't programmed.

Will the PC recognize it ?
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a10_ref directory not available in installation

August 16, 2017, 3:46 am
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I have downloaded the Altera FPGA SDK 16.0 from download center which is about 20GB.
I have installed Pro edition using setup_pro.sh which automatically installs the BSP for the Arria 10 device but I am not able to find the a10_Ref folder into installation.
I am using CentOS. (3.10.0-514.el7.x86_64 #1 SMP Tue Nov 22 16:42:41 UTC 2016 x86_64 x86_64 x86_64 GNU/Linux)

Can anyone help what I missed?
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Cyclone IV E Configuration with Enhanced Configuration Devices

August 16, 2017, 5:23 am
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Hallo

We have a DE0-NANO Board with the EP4CE22F17C6 FPGA. We are planning to use this FPGA and create our own custom board. There are two questions that we are a bit confused about

1. Is Decompression feature supported in the FPGA EP4CE22F17C6
2. Is this FPGA compatible with the Enhanced Configuration devices (EPC4,EPC8,EPC16) ?? Is it possible to configure the FPGA EP4CE22F17C6 using one this EPC4/EPC8/EPC16 and use the "Page Mode Select" option in case of multiple configuration files?
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Arria 10 Native Transceiver PHY - 10GBASE-R

August 16, 2017, 8:12 am
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Hi,
I have a question concerning XCVR clock domains.. I will be referencing Arria 10 Transceiver PHY User Guide (UG-01143 2017.04.20).

Chapter 2.6.2
Figure 55

Here we can see clocking for 10GBASE-R mode of XCVR. I am interested especially in Enhanced PCS TX and RX FIFOs and their WR/RD clocks.
From this figure, we can see that WR clock of TX FIFO is tx_coreclkin and it's supposed to be 156.25 MHz from FPGA fabric (specifically my 10GbE MAC). Internal "Parallel Clock" depends on the width of PCS/PMA interface (default is 40b and 257.8125MHz). So far, so good.

Next, in Figure 58, we see a case with FEC support (which I don't use, but it's interesting anyway) and 64b PCS/PMA interface (so parallel clock is 161.13MHz).
FPGA-side of FIFOs is still 156.25MHz and diagram shows that we can either supply our own clock to rx_coreclkin or create one with PLL using same reference clock.

2.6.2.1.1 TX FIFO and RX FIFO
In 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and
the RX FIFO behaves as a clock compensation FIFO.

Chapter 2.6.2.1
Note:
For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of
TX phase compensation FIFO (PCS data) and the write clock of TX phase
compensation FIFO (XGMII data in the FPGA fabric). This can be achieved by using the
same reference clock as the transceiver dedicated reference clock input as well as the
reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock.

Question: Doesn't this mean, that WR and RD clock of TX FIFO must be same frequency? How can this be, when one is ~257MHz and second is ~156MHz?

More on this in Chapter 5.2.1.1.1:
In Phase Compensation mode, the TX Core FIFO decouples phase variations between
tx_coreclkin and PCS_clkout_x2(tx) . In this mode, read and write of the TX
Core FIFO can be driven by clocks from asynchronous clock sources but must be same
frequency. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout1 (TX
parallel clock) to clock the write side of the TX Core FIFO.

Again.. How? This seems as a major bug in documentation!

As for RX FIFO, previous note continues:
The same core PLL can be used to drive the RX XGMII data. This is because the RX
clock compensation FIFO is able to handle the frequency PPM difference of ±100 ppm
between RX PCS data driven by the RX recovered clock and RX XGMII data.

100 ppm is very little (~15KHz difference on this speeds), so basically, I must use same frequency on RD and WR clocks (which goes against diagram and 156.25MHz claim).

More in Chapter 5.2.2.10.4:
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the
block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered
sets (OS) are deleted and Idles are inserted to compensate for the clock difference
between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a
maximum packet length of 64,000 bytes).

Question: Should I insert ASYNC FIFO on XGMII between XCVR and MAC?

My problem is that packets are getting lost (almost half of them never arrives to the MAC and instead RX LOCAL FAULT is received from XCVR).

Question: Where does RX LOCAL FAULT come and what does it really tell me?

I have tried several configurations and, so far, 40bit PCS/PMA interface and tx_pma_div_clkout with division factor 33 (produces 156.25MHz) works "least broken" (but it's still unacceptable, of course).

Example of statistics from Spirent-Arria test:
TX: 1 000 000
RX: 579 105
FCS ERR: 706
BER: 0

MAC RX: 579 349
MAC DISCARD: 245
MAC TX: 579 105

(TX seems to be working well enough, packets are generated with PRBS)

More problems emerge when using Intel 10GbE PCI-E card and real packets:
TX: 23400
RX: 3494
RX ERROR: 52
MAC RX: 10 590
MAC DISCARD: 3
MAC TX: 10 587

Here more than half packets are lost on MAC RX nad only 1/3 of those sent actually arrives.

I've also tried using 64bit PCS/PMA interface (so parallel clock is ~161MHz) and used tx_clkout for MAC, but surprisingly, nothing really changed and problems were still there.

Development board with SFP+ is used (and actual transceivers used were Finistar and Intel - several of them and all are tested and working properly).

Chapter 2.4.3
Table 13.

Enable tx_pma_div_clkout port
On/Off
Enables the optional tx_pma_div_clkout output clock. This clock is generated by the serializer. You can use this to drive core logic, to drive the FPGA - transceivers interface.

Figure 252 shows possible WR CLKs:
You can control the write port using tx_clkout or tx_coreclkin . Use the
tx_clkout signal for a single channel and tx_coreclkin when using multiple
channels.

This is quite logical - sharing one parallel clock for multiple channels.. But those other mentions with 156.25MHz as WR CLK are quite confusing.

Can anyone help me please?
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Compiler Warning: Threads may reach barrier out of order

August 16, 2017, 10:48 am
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Hi all,

I am writing a matrix vector multiplication kernel code. And I am using two barrier(CLK_LOCAL_MEM_FENCE) in my kernel function. My code works on FPGAs.

However, when I compile my kernel, there is always a Compiler Warning: Threads may reach barrier out of order - allowing at most 2 concurrent workgroups.

I found that if I deleted a for loop in my kernel , the warning will disappear. And if I add the similar for loop to other kernels like vector reduction, the compiler warning appears. The for loop looks like this:

 for(uint x = get_local_id(0); x < width; x += get_local_size(0)){
running_sum += row[x] * vector[x];
}
The code inside the loop doesn't matter. Even though there's nothing inside the for loop, the compiler warning still appears.

So how to solve the problem? :)
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Transceiver link connection error

August 16, 2017, 10:26 pm
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Hello, I'm a beignner of Quartus II tools.

Now I'm using a Stratix V and the transceiver toolkit function.
But there was an error of transceiver links while I'm measuring BER.
The error script in tcl command window was as follows,

"error: alt_xcvr_reconfig_eye_viewer_set_vertical_step: null"

The transceiver link suddenly stopped in a for loop (controlled by a tcl script) with the error.
I couldn't figure out that reason of the error.
Attached is the figure of the link status.

Can anyone help me?

Thank you
Insun Shin
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Question about creating opencl library

August 17, 2017, 12:13 am
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Hi,
In the Intel FPGA SDK for OpenCL Programming Guide,it's said that when creating opencl library,only HDL files is accepted,and additional files such as Quartus Prime IP File are not allowed.My question is would the compiler accept HDL files in which IP core such as FFT is called?
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Fixed-link Feature

August 17, 2017, 1:23 am
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这种特性主要是为了解决没有使用mdio进行管理的Phy设备。

首先是设备树，内核，以及内核配置三块。

第一：
设备树：
有两种写法，据测试现在都是可行的：
之前是这种写法，
A 'fixed-link' property in the Ethernet MAC node, with 5 cells, of the form <a b c d e> with the following accepted values:
- a: emulated PHY ID, choose any but but unique to the all specified fixed-links, from 0 to 31
- b: duplex configuration: 0 for half duplex, 1 for full duplex
- c: link speed in Mbits/sec, accepted values are: 10, 100 and 1000
- d: pause configuration: 0 for no pause, 1 for pause
- e: asymmetric pause configuration: 0 for no asymmetric pause, 1 for asymmetric pause
现在是推荐这种写法：
A 'fixed-link' sub-node of the Ethernet MAC device node, with the followingproperties:
* 'speed' (integer, mandatory), to indicate the link speed. Accepted values are 10, 100 and 1000
* 'full-duplex' (boolean, optional), to indicate that full duplex is used. When absent, half duplex is assumed.
* 'pause' (boolean, optional), to indicate that pause should be enabled.
* 'asym-pause' (boolean, optional), to indicate that asym_pause should be enabled.
* 'link-gpios' ('gpio-list', optional), to indicate if a gpio can be read to determine if the link is up.


第二是暂时不能使用ltsi版本，建议使用master版本。

第三是内核配置要配置支持该特性：FIXED_PHY。
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Cyclone III and 2xSDRAM

August 17, 2017, 5:32 am
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I need to open topic because I couldn't find answers anywhere so maybe someone can help.
Card is designed around EP3C40F484C6N with 2 SDRAM chips IS42S16320B-6TL but they are connected on opposite sides of FPGA.
Goal was to create 32bit interface but without sharing signals(ADDR and such like normal 32bit interface should be).
Idea was to be able to control each chip better by direct interface to the FPGA and now I see that this was bad idea.
Running LFSR tests on both chips is possible up to 80MHz but after that all fails.
First problem is that each SDRAM_CLK uses his own PLL so there might be problems with that.
SDRAM1_CLK is connected to PLL_4 and SDRAM2_CLK to PLL3.
To avoid Quartus using random PLL I did this in *.qsf:

Quote:
set_location_assignment PLL_4 -to "pll:pll|altpll:altpll_component|pll_altpll:auto_g enerated|pll1"
set_location_assignment PLL_3 -to "pll2:pll2|altpll:altpll_component|pll_altpll:auto _generated|pll1"
This says that 2 PLLs are generated who needs to be in sync. As I know they should be in sync by default but maybe there is something I don't know.
After that I have edited SDC file and added there what's needed to separate both chips.

INPUT SIGNALS
Quote:
create_generated_clock -name sdram_clk -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[2]}] [get_ports sdram_clk_o];
create_generated_clock -name sdram2_clk -source [get_pins {pll2|altpll_component|auto_generated|pll1|clk[0]}] [get_ports sdram2_clk_o];
set input_clock [get_clocks sdram_clk]; # Name of input clock
set input_clock2 [get_clocks sdram2_clk]; # Name of input clock
set tco_max 5.800; # Maximum clock to out delay (external device)
set tco_min 3.200; # Minimum clock to out delay (external device)
set trce_dly_max 0.240; # Maximum board trace delay
set trce_dly_min 0.200; # Minimum board trace delay
set input_ports [get_ports {sdram_dq_io[*]}];# List of input ports
set input_ports2 [get_ports {sdram2_dq_io[*]}];
# Input Delay Constraint
set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max - $trce_dly_min] $input_ports;
set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min - $trce_dly_max] $input_ports;

set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max - $trce_dly_min] $input_ports2;
set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min - $trce_dly_max] $input_ports2;

#set_multicycle_path -setup -from $input_clock -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 2
set_multicycle_path -from [get_clocks {sdram_clk}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold -end 2
OUTPUT SIGNALS
Quote:
set fwclk [get_clocks sdram_clk]; # forwarded clock name (generated using create_generated_clock at output clock port)
set fwclk2 [get_clocks sdram2_clk];
set tsu 1.500; # destination device setup time requirement
set thd 0.800; # destination device hold time requirement
set trce_dly_max 0.240; # maximum board trace delay
set trce_dly_min 0.200; # minimum board trace delay
set output_ports [get_ports {
sdram_cke_o
sdram_csn_o
sdram_rasn_o
sdram_casn_o
sdram_wen_o
sdram_dq_io[*]
sdram_ba_o[*]
sdram_a_o[*]
sdram_dqm_o[*]
sdram_dq_io[*]
}]; # list of output ports

set output_ports2 [get_ports {
sdram2_cke_o
sdram2_csn_o
sdram2_rasn_o
sdram2_casn_o
sdram2_wen_o
sdram2_dq_io[*]
sdram2_ba_o[*]
sdram2_a_o[*]
sdram2_dqm_o[*]
sdram2_dq_io[*]
}]; # list of output ports

# Output Delay Constraints
set_output_delay -clock $fwclk -max [expr $trce_dly_max + $tsu - $trce_dly_min] $output_ports;
set_output_delay -clock $fwclk -min [expr $trce_dly_min - $thd - $trce_dly_max] $output_ports;

set_output_delay -clock $fwclk -max [expr $trce_dly_max + $tsu - $trce_dly_min] $output_ports2;
set_output_delay -clock $fwclk -min [expr $trce_dly_min - $thd - $trce_dly_max] $output_ports2;
Next problem is this and could be related to phase shift coz for both chips needs to be different. On SDRAM1 all traces are 28mm, all but CLK who is 23mm. However on SDRAM2 all traces are also 28mm, only CLK is 14mm. This complicates things even more and right now I don't see option how to solve this. If someone is willing to discuss this serious complication I would really appreciate. If there is need for more data i can provide.
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Custom Platform CycloneV

August 17, 2017, 6:59 am
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Cheers,

Currently I am working with Intel openCL sdk for cyclone V. I completed the getting started guide and now I am researching more in deep about the quartus project created in bin folder for compilation with aocl of the project. AOCL generates one folder a 2 files in bin folder, project.aocx, project.aoco and project<folder>. Inside project folder there is a quartus project. I read the custom platform tool guide for opencl and opencl cyclone v andthe information is not clear for me.

What means custom platform? I am understanding a custom platform as a new project to build a new electronic device. If my understanding about this information is not bad, it means that creating a custom platform is a obligatory step for build a electronic device with altera soc fpga. In my case I will use a cyclone v, so in order to save time I reuse (copy and paste) the c5soc template board. I change the name of the folder to myc5soc, and the board_spec.xml name parameter to myc5soc. I compile this and host application and then run in cyclone v dev kit board but I got a message of issue from the execution in linux in soc-fpga cyclone v:

"
Context callback: Program was compiled for a different board. aocx is for board myc5soc whereas device is c5soc
Use aocl program to safely transition to the new board
.
Context callback: Invalid binary
ERROR: CL_INVALID_BINARY
"

I don't understand the issue, because I just change the name and not the platform_type parameter in xml file which I guess is more critical that a simple platform name. However, I am trying to delete my5soc folder, and make a backup of c5soc to customized the c5soc template without change anything and just modify the verilog template for change the frequency of ledfpga more slowly.

Another question: What is the process to add a verilog module when the compilation step is done. I mean, if I compile a project and this generate me a aocx file, what about if i need to change something as add a extra module or just edit the verilog template (top.v) in the project and compile again. it is just possible modifying the template at the beginning of the process before compile or I can modify after and then compile just the last part for saving time.

My goals for this researching are:
- Create a project written in opencl (filter and image processing) and then add a interface (in verilog languaje) to use the SDI video port of the development board.
- Create a getting started guide to use opencl in cyclone v with the project mentioned.

I will be deeply thankful for your help.
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Uart Baud Rate Drop

August 17, 2017, 8:09 am
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Hi all

I'm currently facing a somehow strange effect on my custom SoC Board (incl. a Cyclone V SX --> 5CSXFC2C6U23C8(N)).
While the preloader and uboot are running (at the moment initialized by the DS-5 Debugger over JTAG) I can verify them by UART prompt (8-N-1, baud 115200). As soon as I kill the connection and start my bare metal application (In this case a simple hello world printing via printf (-DPRINTF_UART used for the compile) I receive garbage on the prompt.

So far I have verified the baud rate during the boot process with a oscilloscope --> baud = 116100 Hz (guess +/-3% are ok!)
When I measure the frequency while the bare metal application prints I see a frequency of: baud = 92000 Hz

This is somehow strange as the baud rate is defined by a divisor and the L4_SP_clk frequency (100MHz) which in my opinion are not changing between those two processes. I also tested the exact same setup with the Cyclone V Soc Development Board and never saw any of this happen.

Has anyone experienced some similar situations? Please let me know if you need more information!

Best

Stefan
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Quartus 15.1.2. use Design partition with In-System Memory content Editor

August 17, 2017, 8:57 am
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Hi Everyone,

Does anyone know if it's possible to generate design partitions (qxp file) that contains memory that I can access via In-System Memory Content Editor at a higher level?
- I'm using Quartus 15.1.2

More details to explain my issue:
1. I have a sub module that contains a memory instance (which is created with megawizard with option Enabled for In-System Memory Content Editor")
For example this memory instance is called "Mnew"
2. Then I export this module as "submodule.qxp" file.
3. I import the submodule.qxp file into a different design (a top level)
4. Then generate an image (top.sof file)
5. Then loads the image to a device
6. Then use In-System Memory Content Editor to access this memory instance "Mnew"

I have tried these steps, but the In-System memory content editor only seems to find memory instances at top level :(
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Arria 10 GX FPGA Development Kit Installer - does it exist?

August 17, 2017, 9:56 am
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I am trying to find the installer for the Arria 10 GX dev kit. Typically in the past the Altera Dev Kits have downloads that install the board test system, clocking tool, etc. I can't find the installer for this one.

On this page:

https://www.altera.com/products/boar...0-gx-fpga.html

There are links at the bottom which *LOOK* like the right download, but these are only zip files that do not install anything. Nor is there a board test system, clocking tool, or anything executable to use. Does anyone know where this might be?
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verilog header files in Qsys component editor

August 17, 2017, 1:31 pm
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I am trying to use the Qsys component editor to create an instance of one of my verilog files to use in Qsys.

I have a header file (registers.vh) that has the definitions for a number of `defines that are used in the verilog file. I haven't figured out how to tell Qsys component editor where to find this file. When I try to analyze the RTL files I get the error message:

Error: Verilog HDL File I/O error at meas.v(51): can't open Verilog Design File "registers.vh" File: /abaxis/engine ii/fpga/custom/meas/hdl/meas.v Line: 51


I tried adding the file to the synthesis files list but that didn't help

How do I deal with this?

Thanks

Rod
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New Guy Needs Help

August 17, 2017, 6:56 pm
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I am a student so I downloaded the Quartus Prime lite. The problem I am getting is on the top row and somewhere in the bottom center of the screen. I am trying to type VHDL code to run a simple LED on and off switch. On the top row, when I start typing the usual LIBRRY ieee, that last two ee do not show. When I run my mouse over it, the cursor turns into a finger pointer as though there is a link to something yet I see nothing. If I scroll about 10 lines down and start typing, I see everything. There is something there yet I can not see it. Is there a fix for that or is there something I am not setting correctly. Can anyone help me please. Thank you
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How to feed rx_dataout back to tx_datain in Cyclone IV GX transceiver?

August 17, 2017, 7:30 pm
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Hi, all:

I'm using Cyclone IV GX (EP4CGX50CF23I7) to design some project with transceiver.
As illustrated below, how to loop rx_dataout back to tx_datain?
rx_dataout and rx_clkout is synchronous, with my present transceiver parameters setting, tx_datain is synchronous with ref_clk or tx_clkout. In other word, It can obviously not just assign tx_datain = rx_dataout.
How should I modify the parameter setting of transceiver? Or how should I do to transmit the data received form the receiver without any data loss.

Thanks in advance.
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