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preloader not loading u-boot image

August 17, 2017, 6:43 pm
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Hi magic forum,

I've been trying to make a small bare-metal program working on terasic de10 board with altera cyclone V soc ARM on it. I have some trouble when trying to boot the program from sd card. Here is a brief summary what I did:

For the FPGA part, I just use the example program called DE10-Standard_GHRD from DE10 system CD, compiled with Quartus and generate preloader from it according to this(pg. 69-70). Basically I leave everything as default but enabled FAT-SUPPORT, BOOT_FROM_SDMMC, disabled WATCHDOG_ENABLE. Then I run make to get preloader-mkpimage.bin.

For the software, I made a small program to blink LED, to load this program, I first tried with DS-5 debugger and load through JTAG to the board, it works fine.

Then I tried to load the program from sd card, I've write the preloader(preloader-mkpimage.bin) to a2 partition and put this LED blinking program image(blinking.img) in the fat partition, however, this time it won't work. I can see from putty terminal that the preloader tried to load the image but it stuck at reading blinking.img. However if i replace the blinking.img with linux image, then the linux will be booted. So I think the preloader is ok.

Any ideas which part I might do wrong? I double checked the program entry address and matched the image name with the one I specified in bsp editor.

Thanks in advance!
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Triple Speed Ethernet

August 18, 2017, 1:33 am
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Hello everyone,
I am new to FPGA, I have an Altera DE2-115 kit and i was working on triple speed Ethernet, and have successfully done the "Using Triple Speed Ethernet Tutorial", but i want some help to understand some part of the code given with the tutorial.

// Triple-speed Ethernet MegaCore base address
volatile int * tse = (int *) 0x00102000;


// Initialize the MAC address
*(tse + 3) = 0x116E6001;
*(tse + 4) = 0x00000F02;


// Specify the addresses of the PHY devices to be accessed through MDIO interface
*(tse + 0x0F) = 0x10;
*(tse + 0x10) = 0x11;


// Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback
*(tse + 0x94) = 0x4000;


// Write to register 16 of the PHY chip for Ethernet port 1 to enable automatic crossover for all modes("| = OR")
*(tse + 0xB0) = *(tse + 0xB0) | 0x0060;


// Write to register 20 of the PHY chip for Ethernet port 2 to set up delay for input/output clk
*(tse + 0xB4) = *(tse + 0xB4) | 0x0082;


// Software reset the second PHY chip and wait
*(tse + 0xA0) = *(tse + 0xA0) | 0x8000;
while ( *(tse + 0xA0) & 0x8000 )
;


// Enable read and write transfers, gigabit Ethernet operation, and CRC forwarding
*(tse + 2) = *(tse + 2) | 0x0000004B;


Thanks.
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NIOS II Custom Instruction CRC

August 18, 2017, 1:34 am
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Hello,

I am trying to get the custom instruction set to compile, but can not solve following issues..

1.I try to create the CRC components, as per given in Nios II Custom Instruction User Guide - Implementing a Nios II Custom Instruction in Qsys .
I am using Quartus17.0 prime lite edition, and the DE2-115 board with cyclone IV E. First, I tried on windows 10, but it doesn't work. When I am trying to configure .sof file in FPGA the error is coming like "JTAG Cable not detected" .
2.I tried on Windows XP. As given in PDF and Readme text, I am able to compile and configure on FPGA through NIOS2-eds command shell.
The problem I am facing is that , when I am giving the command ./create-this-app the error is coming like .bsf file is failed to generate.
The difference in the procedure given in PDF and my implementation is the device, I am choosing is CYCLONE IV E. So, please give me insight regarding ,are there any changes required other than given in PDF. How I can resolve this issue?

I am using the following files:
Nios II Custom Instruction User Guide
Design Files for Nios II Custom Instruction User Guide

Thank you in advance
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Access QSPI from HPS C code without linux (bare metal)

August 18, 2017, 1:58 am
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Hi FPGA experts.
I need your help for de1-soc.
In the document http://www.mouser.com/catalog/specsh...manual_v06.pdf it is stated that QSPI Flash can contain user data obious thing for he flash memory. Iwant to read/write data to this memory from c code from HPS.
I see the pin conection of te FPGA to this memory and can do verilog to access it. But I hope there should be some wise way to solve my task through accessing the memory at some address or so directly from ARM trough this fancy AXI bus.
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Mega Wizard dual Clock FIFO Strange behavior !!!!!

August 18, 2017, 4:25 am
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Hullo guys , I have a Cyclone ||| board and im working on an application that uses dual clock 16-bit , 16-word deep FIFO . The write signal and clock r from the FPGA itself, and the read signal and clock r from external MCU. Everything is working fine , except when I write certain value to the FIFO , then the whole operation is acting weird . For example when I write 0xFFFF the values are not latched to the FIFO and I keep reading from the FIFO strange values and the empty flag never gets set !!!! . At first I thought it was a problem with the IOs of the FPGA , but I tried to display 0xFFFF to the IOs and they were working fine .
Any explanation ????
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Altera avalon I2C

August 18, 2017, 4:39 am
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Hello,

I am using cyclone v SE SoC and I want to use altera avalon I2C master protocol in my Qsys design. But the document for IP shows that I2C IP does not support Cyclone V SE SoC. So is there any other IP for I2C??
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Generate binary files for third party programmers

August 18, 2017, 5:13 am
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Hi everyone,

One of our PCB's is using removable flash adapters, where a flash is placed which holds the firmware for our FPGA's. This is done to have a generic PCB where you could easily switch between different FPGA designs and therefore different functions of the PCB itself. To program the flash with the .sof file we usually use the Altera Byteblaster. But we regulary have requests from our suppliers for a binary file to program the flash with a third party programmer.
Now there are different file formats from Altera which seem to be raw binary files like .rpd, .rbf or .hexout files. But all of them seem to have more than only firmware data to have included. Which means, if I load them to the flash like they are, the FPGA design won't work.
My target now is to have a binary file after generation with Quartus which holds the design data in the way as it can be downloaded to a flash by a third party programmer. Is there any documentation or does anyone have experience with this topic?
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Using Avalon-ST interface in OpenCL project.

August 18, 2017, 5:47 am
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Hi,

I am very new to programming in OpenCL on FPGAs. My question is if I want to include in my project Avalon-ST interface how do I include it in OpenCL file?
If I understood well it is done by linking to some kind of library?

Thank you for all replys!
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What to do if on-chip memory is too small for Nios II program

August 18, 2017, 6:20 am
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All Nios II tutorials explain how to use on-chip memory to store the Nios II program. However, what does one do if the program is too big to fit in there? Then one would have to use off-chip memory. However, I do not know how this is incorporated into the design flow.


In other words, in tutorials Qsys system we connect the instruction master of the processor to on-chip memory. Thereafter, when we execute the program from Nios II Ecplise IDE, the program is downloaded into the on-chip memory automatically (I think) and executed. How do I make the program be put into off-chip memory like SDRAM or SRAM or Flash? Is off-chip program download as simple as with on-chip memory i.e one click and the Nios II program is downloaded and executed?


Finally, which file generated by the Nios II Eclipse IDE contains the size of the program? Is the size of the ELF file all that I need to know?
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JTAG chain

August 18, 2017, 4:27 pm
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My board has an Atmel SAM4L MCU as well as the Altera MAX 10 (10M02) FPGA. I'm programming both via JTAG. Will there be any problems if I place those 2 chips in the same JTAG chain, so they can share the same JTAG connector?
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Added a few constraints to .sdc file and the whole design broke?

August 18, 2017, 5:06 pm
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Hello,
I am using the Arria 10 Dev. Board to test out the transceivers. I have a simple design using the Arria 10 Transciever Native PHY with enhanced PCS as well as the associated reset core and PLL. I have very simple logic driving the PHY and have an SFP plugged into the board with a bus analyzer and a loopback cable. When I synthesize, download and run it works flawlessly. I send some sequences as well as a short frame, see them on the bus analyzer, and receive them back in the FPGA.
Now... I add a simple .sdc file defining the clocks that feed the logic and the PHY using the "The Quartus II TimeQuest Timing Analyzer 2014.08.08" as a guideline. The .sdc file is as such:
Code:
create_clock -name CLK_275MHZ -period 3.636 [get_ports {CLK_275MHZ}]
create_clock -name REFCLK_SFP_RX_P -period 1.55 [get_ports {REFCLK_SFP_RX_P}]
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -asynchronous -group { CLK_275MHZ } -group { REFCLK_SFP_RX_P }
Run synthesis again, download, and the whole thing has gone haywire--not just a few bits incorrect, not a frame dropped, but totally haywire without any sensible data. But, there is at least enough being transmitted so that the receiver can lock and descramble--so the cable hasn't gone dark or locked up. I have a bus analyzer, so I can see that the problem originates from the transmit side. Also, if I comment out lines 2-5, it will go back to working fine. I am using Quartus 16.1.2 Standard on Windows.
Any suggestions on where to start would be appreciated. I don't think going on and making the design more complex without ever adding an .sdc file is a workable solution, but, for the time-being, it is the only avenue I have.
I can share more aspects of the design if that would help.
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Cyclone V SoC Development Kit

August 18, 2017, 7:10 pm
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Hi guys,

I have bought this kit recently and ran some provided reference design examples on it (Altera Quartus projects, DS-5, RocketBoards.org, and so on). They work great.
Now, I want to learn more about this device and/or its provided IPs (in Qsys). I also want to learn more about its capability (i.e. what daughter cards or extension boards can interface with it). So, can I ask you, or at least, do you know what other modules or boards I should consider buying in order to interface with my board ?? Where should I look into ??

Thanks,
th_altera
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Pin matching issue on my Cyclone V GX Starter Kit

August 19, 2017, 3:31 am
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Hello everybody,
I bought a Cyclone V Starter Kit (not the Development Kit) because I want to experiment digital electronics from simple logic gates and gradually the FPGA world. As I compile my design using pin assignments from "Default" demo project (I cannot find a standard pin assignments), the compilation stops and these errors come out in compilation console:

Error (171016): Can't place node "LEDR[1]" -- illegal location assignment PIN_F6
Error (171016): Can't place node "LEDR[3]" -- illegal location assignment PIN_G7
Error (171016): Can't place node "SW[0]" -- illegal location assignment PIN_AC9
Error (171016): Can't place node "SW[1]" -- illegal location assignment PIN_AE10
Error (171016): Can't place node "SW[2]" -- illegal location assignment PIN_AD13
Error (171016): Can't place node "SW[3]" -- illegal location assignment PIN_AC8
Error (171016): Can't place node "SW[4]" -- illegal location assignment PIN_W11

Pins assignments are like in instruction manual PDF supply with "System CD". What's wrong? What shall I do?
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How to simulate NCO using Modelsim

August 19, 2017, 2:38 am
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hello,

i want to implement a pipeline ADC and I need to use a sine input, i just learned that i can use NCO to generate the waveform,

when i compiled in quartus ii, there are errors like "Error (204009): Can't generate netlist output files because the license for encrypted file "***/nco-library/asj_nco_madx_cen.v" is not available", and someone told me i should compile and simulate directly in Modelsim.

So i tried Modelsim and i have some questions on simulation:

Altera guidebook suggests that i should add .vo file to the compile directory, and i compiled it with my top-level verilog file and testbench, but there are errors when simulating like "Error: (vsim-3033) Instantiation of 'altmult_add' failed. The design unit was not found.", i dont know how to deal with that.

furthermore, do i need to specify the precompiled libraries?
just as the page suggests(http://quartushelp.altera.com/15.0/m...m_func_sim.htm)

thanks in advance~
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save the values from nios 2 console

August 20, 2017, 12:38 am
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hi
hi,i am able to print a set of values to nios 2 console

the values are too large . so need to save the data for further evaluation. how can i do that ? i need to see it i nios 2 console also, is there any options like enable a log file or something ?
 like above i can do that , but then its not possible to see it in terminal, when i tried at the same time , the first error came and i stopped nios 2 terminal, then its saving to a text file.
and when i try to do it in run configuration,

its not the nios 2 console is saving to the text file, its console is saving to the text file like below.
Using cable "CV SoCKit [USB-1]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK

Downloading 00020000 ( 0%)
Downloading 000316A8 (90%)
Downloaded 70KB in 0.1s

Verifying 00020000 ( 0%)
Verifying 000316A8 (90%)
Verified OK
Starting processor at address 0x00020230


is there any way that print it in nios 2 console and at the same time it will save from nios 2 console?

update:: i am using windows 7

thanks and regards
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Unique Memory Initialization Files for Multiple Nios Instances

August 20, 2017, 5:55 am
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I want different applications running on multiple instances of a single Nios design. How do I specify unique memory initialization files?
(I rather not have two Nios designs and two BSPs, different in name only.)

// for example:
nios_cpu cpu0 (...); // this one should use cpu0_mem_init.hex
nios_cpu cpu1 (...); // this one should use cpu1_mem_init.hex

Thanks!
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Ddr4 vref

August 20, 2017, 1:18 pm
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Is it necessary to connect 0.6V to the VREF pins on Arria 10 when using DDR4 ?

Thanks!
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Installation error for NIOS II.

August 20, 2017, 10:58 pm
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I have downloaded "10.1_acds_web_edition.iso" from "ftp://ftp.altera.com/outgoing/release/" and then I have downloaded "10.1sp1_nios2eds_windows"(service pack 1). After installing the 1st software successfully while I am trying to install the 2nd one, 1st I was asked for the path where I mentioned "C:/altera/10.1" but for the 2nd time when I was asked for the path then if i am providing either "C:/altera/10.1" or "C:/altera" both are showing the error.
I am attaching the screenshot of the error. Please help me out.
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Installation error for NIOS II.(For windows 7 64-bit)

August 20, 2017, 11:04 pm
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I have downloaded "10.1_acds_web_edition.iso" from "ftp://ftp.altera.com/outgoing/release/" and then I have downloaded "10.1sp1_nios2eds_windows"(service pack 1). After installing the 1st software successfully while I am trying to install the 2nd one, 1st I was asked for the path where I mentioned "C:/altera/10.1" but for the 2nd time when I was asked for the path then if i am providing either "C:/altera/10.1" or "C:/altera" both are showing the error.
I am attaching the screenshot of the error. Please help me out.
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Quartus II error, cann't open *.bdf file

August 21, 2017, 12:24 am
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I use Quartus II 9.0 as the development tool and choose the BDF as the design input. At the begin, everything is fine and I have complteted the design and perfromed the simulation by simulator of Quartus II. However, the quartus output one warning message (Error:Cann't open file E:\hardware\CPLD\design.bdf and Cann't find requested location) after one time of synthesis. Then, I closed the project and open the project again. The BDF file can not be opened. The error message is shown as above. Is there any solution?

Thanks!
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