I am using cyclone IV device connecting to a DDR2 sdram. Now I want to verify if connection between FPGA and DDR2 is OK. So i instantiated a ddr2_controller_with_altmemphy and using the example_top as top level entry. After I compile all the project there is no error or timing vilation. But after I download the sof to FPGA, ddr2 calibration fail. After I add the signal in signal_tapII, I can see that afer the seq enter Calculate Read Resynchronization Phase (s_rrp_seek), then the ctl_cal_fail asserted. Here is the signal_tap waveform. Can anyone give me some suggestion. Thanks!
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↧
DDR2 calibration fail using cyclone IV device
↧
frequency meter on cyclone IV E ,without display frequency
hi everybody.
sorry for my english.
I ask for your help for released an simple frequency meter with vhdl (i am newbie on FPGA):
![]()
Input
"ref_clock" is 50 MHz periode 20ns of cyclone IV E.
"signal" is mesured signal from encoder
Output
cycle of test errors every 1 sec
if frequency >= 1000 Hz ==>error1 = 1 //1 is logic HIGH
if frequency >= 2000 Hz ==> error1 = 1 and error2 = 1
else error1 = 0 and error2 = 0 //0 is logic LOW
thank you.
sorry for my english.
I ask for your help for released an simple frequency meter with vhdl (i am newbie on FPGA):
Input
"ref_clock" is 50 MHz periode 20ns of cyclone IV E.
"signal" is mesured signal from encoder
Output
cycle of test errors every 1 sec
if frequency >= 1000 Hz ==>error1 = 1 //1 is logic HIGH
if frequency >= 2000 Hz ==> error1 = 1 and error2 = 1
else error1 = 0 and error2 = 0 //0 is logic LOW
thank you.
↧
↧
Problem with Compiling Examples for DE1-SOC
Hi Everyone,
I'm kinda new to OpenCL with Altera boards and I'm trying to compile the examples for DE1-SOC board using the OpenCL SDK and all of them gets an error which I can't seem to figure out why are they failing.
They all gives me:
Can anyone help me?
Thank you!
I'm kinda new to OpenCL with Altera boards and I'm trying to compile the examples for DE1-SOC board using the OpenCL SDK and all of them gets an error which I can't seem to figure out why are they failing.
They all gives me:
Code:
system_integrator: main.cpp:470: int ReadKernelData(altera_xercesc_2_6::XERCES_DOMDocument*, OpenCLSystem*): Assertion `document != __null' failed.Aborted (core dumped)
Error: System integrator FAILED.I
Refer to vector_add/vector_add.log for details.Can anyone help me?
Thank you!
↧
jtag programming bug
Hi all,
I'm using DE0-CV board and running Nios II on this board.
(I'm running a custom application on the board which is basically 7 different ''for'' loops. I can find the duration and beginning and end of each loop with looking at the EM signals generated by the FPGA.)
My problem is sometimes when I program the board (using Quartus programmer and usb blaster) the duration of my application may become much more longer (1.5x) than other runs (with exact same inputs and code). In other words, each time I disconnect the USB cable and reconnect it and reprogram the board, the runtime might be either normal or 1.5x slow (but it is the same across each programming interval. i.e. after I program the board, each time that I run the application it takes same amount of time) so it seems like the reason for inconsistency is programming the board.
I was wondering if anybody has seen something like this? I would really appreciate it if somebody can help me figuring out what the problem is.
BTW I'm using Quartus/Eclipse (latest version) on Linux.
I'm using DE0-CV board and running Nios II on this board.
(I'm running a custom application on the board which is basically 7 different ''for'' loops. I can find the duration and beginning and end of each loop with looking at the EM signals generated by the FPGA.)
My problem is sometimes when I program the board (using Quartus programmer and usb blaster) the duration of my application may become much more longer (1.5x) than other runs (with exact same inputs and code). In other words, each time I disconnect the USB cable and reconnect it and reprogram the board, the runtime might be either normal or 1.5x slow (but it is the same across each programming interval. i.e. after I program the board, each time that I run the application it takes same amount of time) so it seems like the reason for inconsistency is programming the board.
I was wondering if anybody has seen something like this? I would really appreciate it if somebody can help me figuring out what the problem is.
BTW I'm using Quartus/Eclipse (latest version) on Linux.
↧
Trouble running an old Quartus-II
For a very long time, I've been using Altera EPM7128SLC84's for which I had boards made back a couple of decades ago as reuseable test fixtures or attachments to them. I occasionally have to reprogram them, and like to use Modelsim to help avoid "stupid" errors. I've been trying for about 8 months to get Quartus-II 13.0SP1 to work but haven't had the time or the needed information to set up that software pack in order to get it to work properly. Admittedly, some of the test fixtures I use in my lab are Xilinx boards, and I have used them because their software makes using them "dirt-simple". They simply require the design entry and the software automatically creates all the needed files to run right into the simulator and show the simulation output. I don't know "where the rocks are, so I can't walk on the water". The Quartus-II I've been trying to use is v13.0SP1 with Modelsim Starter, which is apparently the last version that supported these older CPLD's.
Most of my clients are as long in the tooth as I, and are more comfortable with schematics than with HDL, so I use them most of the time, just so we all are on the same page. I do use VHDL from time to time. However, modules entered in VHDL end up as symbols on a schematic, so my clients can grasp what's going on.
Could someone tell me what and how parameters have to be set in order to make this software work with these CPLD's and with 3120A's and with VHDL?
thanks in advance,
Uli
Most of my clients are as long in the tooth as I, and are more comfortable with schematics than with HDL, so I use them most of the time, just so we all are on the same page. I do use VHDL from time to time. However, modules entered in VHDL end up as symbols on a schematic, so my clients can grasp what's going on.
Could someone tell me what and how parameters have to be set in order to make this software work with these CPLD's and with 3120A's and with VHDL?
thanks in advance,
Uli
↧
↧
Help needed in understanding "Net Delay Summary"
Hi,
Timequest Analyzer is reporting "Net Delay Summary" in red (Screenshot attached for the reference). Paths highlighted in red in the report are inside Qsys generated design. So, I do not have much control over the path. In general how important are these violations/report?
The max delay (Required) shown in the analyzer is 2.00 for all the paths in the IPs inside the Qsys design. I do not understand how this can be same for all the paths?
Timequest Analyzer is reporting "Net Delay Summary" in red (Screenshot attached for the reference). Paths highlighted in red in the report are inside Qsys generated design. So, I do not have much control over the path. In general how important are these violations/report?
The max delay (Required) shown in the analyzer is 2.00 for all the paths in the IPs inside the Qsys design. I do not understand how this can be same for all the paths?
↧
SPI communication
I am using a STREAM FPGA board connected to an RF board.
Up until now, Quartus has been able to output frequencies to the NCO IP.
Next, I want to send the output frequency to the transmitter of the RF board and confirm it through the spectrum analyzer. I do not know how to connect the two boards (RF, STREAM).
I do not understand why the downloaded user guide uses SPI techniques.
I would like to get good advice or related guidance for me.
Up until now, Quartus has been able to output frequencies to the NCO IP.
Next, I want to send the output frequency to the transmitter of the RF board and confirm it through the spectrum analyzer. I do not know how to connect the two boards (RF, STREAM).
I do not understand why the downloaded user guide uses SPI techniques.
I would like to get good advice or related guidance for me.
↧
HPS t o FPGA access time measuring
Hi everybody,
I am currently playing around with the Cyclone V SoC Development board.
I have a QSys system running resembling the Golden system reference design apart from the fact that the h2f_axi_clock is controlled by a PLL residing on FPGA side.
The h2f_axi_clock is 50 MHz in my case.
I have an IP test (with many registers) up and running according to the GSRD and connected directly to H2F_axi_master. I used the Linux example to run a Linux (3.7) application on the HPS. From within the application I can write to and read from my IP test in the FPGA, the memory address range is mmaped to the linux user space for this purpose.
Now the question:
The time taken to lauch 2 read (or write ) access from an application to my IP registers was mush more than expected (we should have a bandwith of 3.5 GHZ/s I think) :
According to signal tap (by tracking the chipselect signal): 1 read access takes only 40ns , (1 write, 20ns) whereas between 2 read access there is a 320 ns (same as for write access) . And my application is simple: mmap IP address writes 32-bit values to 10 registers and read back results at the end (by storing them in an array of uint32_t : uint32_t IP_reg[10]).
read instruction: IP_regs[0]= *((unsigned long *) (map_base + (target & MAP_MASK)+24 ));// (10 accesses such as this one)
write instruction: *((unsigned long *) (map_base + (target & MAP_MASK) +24 )) = 1;// (10 accesses such as this one)
How can I accelerate several read write accesses to FPGA IPs from the HPS ?
Thanks in advance,
----------------------------
My IP interface: mm_avalon
Processor : 925 MHz, ARM cortex A9 dual core
Board: Altera cyclone V SX SoC
I am currently playing around with the Cyclone V SoC Development board.
I have a QSys system running resembling the Golden system reference design apart from the fact that the h2f_axi_clock is controlled by a PLL residing on FPGA side.
The h2f_axi_clock is 50 MHz in my case.
I have an IP test (with many registers) up and running according to the GSRD and connected directly to H2F_axi_master. I used the Linux example to run a Linux (3.7) application on the HPS. From within the application I can write to and read from my IP test in the FPGA, the memory address range is mmaped to the linux user space for this purpose.
Now the question:
The time taken to lauch 2 read (or write ) access from an application to my IP registers was mush more than expected (we should have a bandwith of 3.5 GHZ/s I think) :
According to signal tap (by tracking the chipselect signal): 1 read access takes only 40ns , (1 write, 20ns) whereas between 2 read access there is a 320 ns (same as for write access) . And my application is simple: mmap IP address writes 32-bit values to 10 registers and read back results at the end (by storing them in an array of uint32_t : uint32_t IP_reg[10]).
read instruction: IP_regs[0]= *((unsigned long *) (map_base + (target & MAP_MASK)+24 ));// (10 accesses such as this one)
write instruction: *((unsigned long *) (map_base + (target & MAP_MASK) +24 )) = 1;// (10 accesses such as this one)
How can I accelerate several read write accesses to FPGA IPs from the HPS ?
Thanks in advance,
----------------------------
My IP interface: mm_avalon
Processor : 925 MHz, ARM cortex A9 dual core
Board: Altera cyclone V SX SoC
↧
Mtu
MTU是什么
提到以太网，离不开两个模型：OSI模型和TCP/IP模型。
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image002.png[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image004.png[/IMG]
以太网对数据帧的长度有一个限制，最大值是1500。链路层的这个特性称作MTU（最大传输单元）。如果I P层数据报的长度比链路层的MTU还要大，那么IP层就需要进行分片，每一片都要小于MTU。
MTU怎么修改
Windows下查看和修改方法：
netsh interface ipv4 show subinterfaces
netsh interface ipv4 set subinterface "本地连接" mtu=3800 store=persistent
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image010.jpg[/IMG]
Linux下查看和修改方法：
执行ifconfig或者cat /sys/class/net/eth0/mtu
ifconfig eth0 down; echo "9800" > /sys/class/net/eth0/mtu; ifconfig eth0 up
Intel PSG SoC FPGA下怎么使mtu可以修改到9800呢？
当然也是上面那么修改，只是在修改前，需要修改以下几个地方。据我经过一个晚上持续的打流测试，修改后能够 稳定运行：
1）修改drivers/net/ethernet/stmicro/stmmac/stmmac_common.h #define JUMBO_LEN 9800;
2）修改设备树max-frame-size 为9800；
3）编译内核和设备树。
验证方法：
遗留的问题
虽然MTU能够设置为9800了，但是真实的收发报文达不到9800.现在只能达到8192。
下图：Mtu都设置为9800，发8150能发送和接收，但8151没有收取到报文发送出来。
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image011.png[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image013.jpg[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image014.png[/IMG]
提到以太网，离不开两个模型：OSI模型和TCP/IP模型。
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image002.png[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image004.png[/IMG]
以太网对数据帧的长度有一个限制，最大值是1500。链路层的这个特性称作MTU（最大传输单元）。如果I P层数据报的长度比链路层的MTU还要大，那么IP层就需要进行分片，每一片都要小于MTU。
MTU怎么修改
Windows下查看和修改方法：
netsh interface ipv4 show subinterfaces
netsh interface ipv4 set subinterface "本地连接" mtu=3800 store=persistent
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image010.jpg[/IMG]
Linux下查看和修改方法：
执行ifconfig或者cat /sys/class/net/eth0/mtu
ifconfig eth0 down; echo "9800" > /sys/class/net/eth0/mtu; ifconfig eth0 up
Intel PSG SoC FPGA下怎么使mtu可以修改到9800呢？
当然也是上面那么修改，只是在修改前，需要修改以下几个地方。据我经过一个晚上持续的打流测试，修改后能够 稳定运行：
1）修改drivers/net/ethernet/stmicro/stmmac/stmmac_common.h #define JUMBO_LEN 9800;
2）修改设备树max-frame-size 为9800；
3）编译内核和设备树。
验证方法：
- 发送指定长度报文
- Windows下使用ping命令，添加-l参数；
- Linux下使用ping命令，添加-s参数；
- 接收、分析报文
- tcpdump或者wireshark工具抓包分析
遗留的问题
虽然MTU能够设置为9800了，但是真实的收发报文达不到9800.现在只能达到8192。
下图：Mtu都设置为9800，发8150能发送和接收，但8151没有收取到报文发送出来。
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image011.png[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image013.jpg[/IMG]
[IMG]file:///C:/Users/martinfeng/AppData/Local/Temp/msohtmlclip1/01/clip_image014.png[/IMG]
↧
↧
Driver / aocl diagnose problems
Hey everyone,
I'm having problems with getting an Arria10 custom platform to work on my Windows 7 and Windows 10 machines.
The fit created for the platform is made by adapting the Arria 10 reference design by interchanging the original DDR4 core with our DDR3 IP core and changing the pinout to match the changes made. As the project is time constrained, no changes have been made to the PCIe IP to quickly get the platform operational for a demo.
Compiling the fit did not result in any problems and the PCIe device is recognized by the PC, as it should be.
However, when moving to getting the drivers to work problems started to show up. I have tried to run the device on both a Windows 10 and a Windows 7 PC, and both PCs run into different problems.
After running aocl install and a reboot, the Windows 10 PC reports in device manager that our board is an "Other device -> PCI device". The hardware ID matches the ID in the .inf script used when installing the drivers and it shows the problem code 0000001C: missing driver. Next, the Jungo Connectivity drive seems to work correctly as no problems are reported. Now, when running aocl diagnose with debugging environmental variables enabled, the following output is reported indicating that something goes wrong with interrupts:
I already created a support ticket for this problem, but all they said about it is that this probably is a host problem and that I should try to get the drivers working on a Windows 7 machine, and so I did.
On Windows 7, I run into a totally different problem. Here, after running aocl install and performing a reboot, the PCI device is correctly recognized as an Intel FPGA accelerator. However, both the accelerator and the Jungo drivers report problem ID 00000034, which according to google tells that Windows cannot determine the settings for this device.
When running aocl diagnose, now the following error shows:
Any help for both problems would be very welcome!
Kind regards,
Remy Quist
I'm having problems with getting an Arria10 custom platform to work on my Windows 7 and Windows 10 machines.
The fit created for the platform is made by adapting the Arria 10 reference design by interchanging the original DDR4 core with our DDR3 IP core and changing the pinout to match the changes made. As the project is time constrained, no changes have been made to the PCIe IP to quickly get the platform operational for a demo.
Compiling the fit did not result in any problems and the PCIe device is recognized by the PC, as it should be.
However, when moving to getting the drivers to work problems started to show up. I have tried to run the device on both a Windows 10 and a Windows 7 PC, and both PCs run into different problems.
After running aocl install and a reboot, the Windows 10 PC reports in device manager that our board is an "Other device -> PCI device". The hardware ID matches the ID in the .inf script used when installing the drivers and it shows the problem code 0000001C: missing driver. Next, the Jungo Connectivity drive seems to work correctly as no problems are reported. Now, when running aocl diagnose with debugging environmental variables enabled, the following output is reported indicating that something goes wrong with interrupts:
Code:
:: MMD DEBUG LEVEL set to 10000
:: [acla10_ref0] PCI Class Code and Rev is: 12000101
:: [GLOBAL-MEM] Init: Bar 4, Total offset 0x10000, diff_endian is 0
:: [PCIE-CRA] Init: Bar 4, Total offset 0x0, diff_endian is 0
:: [MEMWINDOW] Init: Bar 4, Total offset 0xc870, diff_endian is 0
:: [DMA-CTR] Init: Bar 0, Total offset 0x0, diff_endian is 0
:: [VERSION] Init: Bar 4, Total offset 0xcfc0, diff_endian is 0
:: [PRBASEID] Init: Bar 4, Total offset 0xcf80, diff_endian is 0
:: [CADEID] Init: Bar 4, Total offset 0xcf70, diff_endian is 0
:: [UNIPHYSTATUS] Init: Bar 4, Total offset 0xcfe0, diff_endian is 0
:: [UNIPHYRESET] Init: Bar 4, Total offset 0xcfd0, diff_endian is 0
:: [KERNEL] Init: Bar 4, Total offset 0x4000, diff_endian is 0
:: [PLL] Init: Bar 4, Total offset 0xb000, diff_endian is 0
:: [TEMP-SENSOR] Init: Bar 4, Total offset 0xcff0, diff_endian is 0
:::::: [MEMWINDOW] Read 64 bits (0x0) from 0x0 (0xc870 with offset)
:::::: [MEMWINDOW] Wrote 64 bits (0x0) to 0x0 (0xc870 with offset)
:::::: [acla10_ref0] Changed segment id to 0.
:::::: [MEMWINDOW] Read 64 bits (0x0) from 0x0 (0xc870 with offset)
:: [acla10_ref0] Doing PCIe-to-fabric read test ...
:::::: [VERSION] Read 32 bits (0xa0c7c1e3) from 0x0 (0xcfc0 with offset)
:: [acla10_ref0] PCIe-to-fabric read test passed
:::::: [UNIPHYSTATUS] Read 32 bits (0x0) from 0x0 (0xcfe0 with offset)
:: [acla10_ref0] Uniphys are calibrated
:::: [DMA] Successfully locked descriptor table memory.
:: [acla10_ref0] Enabling PCIe interrupts.
:::::: [PCIE-CRA] Wrote 32 bits (0x0) to 0xcfa0 (0xcfa0 with offset)
:: [acla10_ref0] Interrupt handler:
:: KMD Bar4 addr 0xFFFF9E817B5A0000
:: Read <- 0x7b5acf90
:: Mask 0x1
:: Write -> 0x7b5acfa0
MMD ERROR: [acla10_ref0] failed to enable interrupts in the KMD.
Phys Dev Name Status Information
acla10_ref0 Failed Board name not available.
Failed initial tests, so not working as expected.
Please try again after reprogramming the device.
Found no active device installed on the host machine.On Windows 7, I run into a totally different problem. Here, after running aocl install and performing a reboot, the PCI device is correctly recognized as an Intel FPGA accelerator. However, both the accelerator and the Jungo drivers report problem ID 00000034, which according to google tells that Windows cannot determine the settings for this device.
When running aocl diagnose, now the following error shows:
Code:
aocl diagnose: failed 32 times. First error below:
Unable to open the kernel mode driver.
Please make sure you have properly installed the driver. To install the driver, run
aocl install
DIAGNOSTIC_FAILEDKind regards,
Remy Quist
↧
Does Altera provide a synchronization chain megafunction for asynchronous inputs
It is possible to write a synchronizer chain to synchronize incoming asynchronous signals and prevent metastability. It shall be a few lines of code. Does Altera have a special megafunction to do this or atleast some guidelines so Quartus understands that we are trying to infer a synchronization chain?
↧
Quartus Error 35030
I have a Cyclone V HPS design on the SoCKit board which includes some custom logic connecting to LOANIO.
My custom logic basically replaces the SPIM0 module in the HPS, so I took the SPIM0[CLK, MISO, MOSI, SS] and clicked LOANIO so I could pass them to the outside world.
I initially got the 12016 error "Net hps_spisensor_MISO", which fans out to '<long text...>LOANIO69' is connecting a Partition with logic other than a single Bidirectional pin". I wasn't sure what this meant, but I got rid of the error by changing my ghrd_top.v file's, MISO declaration from "input" to "inout". This seemed fishy. The below errors are all for the remainder of the signals in my custom logic, which are all outputs.
Next I started seeing error 35030: "Partition "<long text>:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity"
Followed by several 35032: "Output port '<long text>hps_io_gpio_inst_LOANIO57[0]' on partition '<long text>:border' must drive a top level pin but is driving '<long text> :border|gpio_inst".
Followed by several 13176: "Port I_GPIO1_PORTA_I of HPS atom '<long text>hps_gio_gpio_inst_LOANIO57[0]~output' must be connected to a top level pin"
etc, etc.
Below shows the relevant portions of the "ghrd_top.v" file showing how I'm doing the loan IO.
`include "top/config_soc.v"
module ghrd_top (
output wire hps_spisensor_CLK,
output wire hps_spisensor_MOSI,
inout wire hps_spisensor_MISO, // I had to change this from input to inout
output wire hps_spisensor_CSN,
);
// internal wires and registers declaration
wire [66:0] loan_io_in;
wire [66:0] loan_io_out;
wire [66:0] loan_io_oe;
wire spisensor_clk_internal;
wire spisensor_mosi_internal;
wire spisensor_miso_internal;
wire spisensor_csn_internal;
assign loan_io_out[57] = spisensor_clk_internal;
assign loan_io_out[58] = spisensor_mosi_internal;
assign loan_io_out[59] = 1'b0; // arbitrary
assign loan_io_out[60] = spisensor_csn_internal;
assign loan_io_oe[57] = 1'b0;
assign loan_io_oe[58] = 1'b0;
assign loan_io_oe[60] = 1'b0;
assign spisensor_miso_internal = loan_io_in[59];
soc_system u0 (
.hps_0_h2f_loan_io_in (loan_io_in),
.hps_0_h2f_loan_io_out (loan_io_out),
.hps_0_h2f_loan_io_oe (loan_io_oe),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO57 (hps_spisensor_CLK),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO58 (hps_spisensor_MOSI),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO59 (hps_spisensor_MISO),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO60 (hps_spisensor_CSN),
.sensormaster_0_sensorconduit_spi_clk_out (spisensor_clk_internal),
.sensormaster_0_sensorconduit_spi_cs_n (spisensor_csn_internal),
.sensormaster_0_sensorconduit_spi_miso (spisensor_miso_internal),
.sensormaster_0_sensorconduit_spi_mosi (spisensor_mosi_internal),
);
endmodule
I could not paste the image properly, so attached are some snapshots.
![]()
![]()
My custom logic basically replaces the SPIM0 module in the HPS, so I took the SPIM0[CLK, MISO, MOSI, SS] and clicked LOANIO so I could pass them to the outside world.
I initially got the 12016 error "Net hps_spisensor_MISO", which fans out to '<long text...>LOANIO69' is connecting a Partition with logic other than a single Bidirectional pin". I wasn't sure what this meant, but I got rid of the error by changing my ghrd_top.v file's, MISO declaration from "input" to "inout". This seemed fishy. The below errors are all for the remainder of the signals in my custom logic, which are all outputs.
Next I started seeing error 35030: "Partition "<long text>:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity"
Followed by several 35032: "Output port '<long text>hps_io_gpio_inst_LOANIO57[0]' on partition '<long text>:border' must drive a top level pin but is driving '<long text> :border|gpio_inst".
Followed by several 13176: "Port I_GPIO1_PORTA_I of HPS atom '<long text>hps_gio_gpio_inst_LOANIO57[0]~output' must be connected to a top level pin"
etc, etc.
Below shows the relevant portions of the "ghrd_top.v" file showing how I'm doing the loan IO.
`include "top/config_soc.v"
module ghrd_top (
output wire hps_spisensor_CLK,
output wire hps_spisensor_MOSI,
inout wire hps_spisensor_MISO, // I had to change this from input to inout
output wire hps_spisensor_CSN,
);
// internal wires and registers declaration
wire [66:0] loan_io_in;
wire [66:0] loan_io_out;
wire [66:0] loan_io_oe;
wire spisensor_clk_internal;
wire spisensor_mosi_internal;
wire spisensor_miso_internal;
wire spisensor_csn_internal;
assign loan_io_out[57] = spisensor_clk_internal;
assign loan_io_out[58] = spisensor_mosi_internal;
assign loan_io_out[59] = 1'b0; // arbitrary
assign loan_io_out[60] = spisensor_csn_internal;
assign loan_io_oe[57] = 1'b0;
assign loan_io_oe[58] = 1'b0;
assign loan_io_oe[60] = 1'b0;
assign spisensor_miso_internal = loan_io_in[59];
soc_system u0 (
.hps_0_h2f_loan_io_in (loan_io_in),
.hps_0_h2f_loan_io_out (loan_io_out),
.hps_0_h2f_loan_io_oe (loan_io_oe),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO57 (hps_spisensor_CLK),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO58 (hps_spisensor_MOSI),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO59 (hps_spisensor_MISO),
.hps_0_hps_io_hps_io_gpio_inst_LOANIO60 (hps_spisensor_CSN),
.sensormaster_0_sensorconduit_spi_clk_out (spisensor_clk_internal),
.sensormaster_0_sensorconduit_spi_cs_n (spisensor_csn_internal),
.sensormaster_0_sensorconduit_spi_miso (spisensor_miso_internal),
.sensormaster_0_sensorconduit_spi_mosi (spisensor_mosi_internal),
);
endmodule
I could not paste the image properly, so attached are some snapshots.
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New Guy Needs Help with vectors
I have a code for a MUX whereby I have an input named SW which comprises of SW (0 through 3). I am using case statement for a seven segment display. This is just to show 0 all the way to F. I copied this code from another program I used when I had the NEXYS4 DDR FPGA development board which used the Vivado IDE. For example
case SW is
when "00000"=> a_to_g <="1000000";
when "00001"=> a_to_g <="1111001";
when "00010"=> a_to_g <="0100100";
when "00011"=> a_to_g <="0110000";
when "00100"=> a_to_g <="0011001"; etc.....
So the first instance would yield a 0 on the seven segment display. Then a 1, 2, 3, etc.... So I am trying to do this from 0 through F so I am wondering how to declare SW because SW actually SW(0), SW(1) SW(2), SW(3), and SW(4). In the beginning of the code, I declared SW as such. SW : in STD_LOGIC_VECTOR (4 downto 0);. Can anyone help me to make this happen. I am sure there is a way but I can not figure it out. I was used to using vivado IDE using the NEXYS4 DDR. When I used to declare SW as a vector in vivado, it automatically had be declare each individual SW(0 through 4). Please help. Thank you.
case SW is
when "00000"=> a_to_g <="1000000";
when "00001"=> a_to_g <="1111001";
when "00010"=> a_to_g <="0100100";
when "00011"=> a_to_g <="0110000";
when "00100"=> a_to_g <="0011001"; etc.....
So the first instance would yield a 0 on the seven segment display. Then a 1, 2, 3, etc.... So I am trying to do this from 0 through F so I am wondering how to declare SW because SW actually SW(0), SW(1) SW(2), SW(3), and SW(4). In the beginning of the code, I declared SW as such. SW : in STD_LOGIC_VECTOR (4 downto 0);. Can anyone help me to make this happen. I am sure there is a way but I can not figure it out. I was used to using vivado IDE using the NEXYS4 DDR. When I used to declare SW as a vector in vivado, it automatically had be declare each individual SW(0 through 4). Please help. Thank you.
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7 Segment display
Is there a way to choose a certain seven segment display and disable the other 7 on the DE2-115 board. For example is it possible to put a statement like SSEG <= "11111110" which would disable all of the seven segment displays except for the very first one. Thanks in advance for the help
↧
Pin matching issue on my Cyclone V GX Starter Kit
Hello everybody,
I bought a Cyclone V Starter Kit (not the Development Kit) because I want to experiment digital electronics from simple logic gates and gradually the FPGA world. As I compile my design using pin assignments from "Default" demo project (I cannot find a standard pin assignments), the compilation stops and these errors come out in compilation console:
Error (171016): Can't place node "LEDR[1]" -- illegal location assignment PIN_F6
Error (171016): Can't place node "LEDR[3]" -- illegal location assignment PIN_G7
Error (171016): Can't place node "SW[0]" -- illegal location assignment PIN_AC9
Error (171016): Can't place node "SW[1]" -- illegal location assignment PIN_AE10
Error (171016): Can't place node "SW[2]" -- illegal location assignment PIN_AD13
Error (171016): Can't place node "SW[3]" -- illegal location assignment PIN_AC8
Error (171016): Can't place node "SW[4]" -- illegal location assignment PIN_W11
Pins assignments are like in instruction manual PDF supply with "System CD". What's wrong? What shall I do?
I bought a Cyclone V Starter Kit (not the Development Kit) because I want to experiment digital electronics from simple logic gates and gradually the FPGA world. As I compile my design using pin assignments from "Default" demo project (I cannot find a standard pin assignments), the compilation stops and these errors come out in compilation console:
Error (171016): Can't place node "LEDR[1]" -- illegal location assignment PIN_F6
Error (171016): Can't place node "LEDR[3]" -- illegal location assignment PIN_G7
Error (171016): Can't place node "SW[0]" -- illegal location assignment PIN_AC9
Error (171016): Can't place node "SW[1]" -- illegal location assignment PIN_AE10
Error (171016): Can't place node "SW[2]" -- illegal location assignment PIN_AD13
Error (171016): Can't place node "SW[3]" -- illegal location assignment PIN_AC8
Error (171016): Can't place node "SW[4]" -- illegal location assignment PIN_W11
Pins assignments are like in instruction manual PDF supply with "System CD". What's wrong? What shall I do?
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Qsys disable interface based on parameter
Hi,
I have a VHDL component packed as Qsys Component Editor and I need to disable interface based on parameter set by user.
I have used naive approach and have this in TCL:
This causes following error:
I kinda get why it isn't allowed (so that's not my question).
What I'd like to know is how should I do it when I want to enable/disable certain interfaces based on user's choice in component configuration in Qsys..
Thanks for any help :)
I have a VHDL component packed as Qsys Component Editor and I need to disable interface based on parameter set by user.
I have used naive approach and have this in TCL:
Code:
add_parameter C_MDIO BOOLEAN false
set_parameter_property C_MDIO DEFAULT_VALUE false
set_parameter_property C_MDIO DISPLAY_NAME C_MDIO
set_parameter_property C_MDIO TYPE BOOLEAN
set_parameter_property C_MDIO UNITS None
set_parameter_property C_MDIO DESCRIPTION "Enables MDIO Controller"
set_parameter_property C_MDIO HDL_PARAMETER true
...
#
# connection point MDIO_MASTER
#
add_interface MDIO_MASTER conduit end
set_interface_property MDIO_MASTER associatedClock MDIO_CLK
set_interface_property MDIO_MASTER associatedReset ""
set_interface_property MDIO_MASTER ENABLED [ get_parameter_value C_MDIO ]
set_interface_property MDIO_MASTER EXPORT_OF ""
set_interface_property MDIO_MASTER PORT_NAME_MAP ""
set_interface_property MDIO_MASTER CMSIS_SVD_VARIABLES ""
set_interface_property MDIO_MASTER SVD_ADDRESS_GROUP ""
add_interface_port MDIO_MASTER MDIO_IN mdioin Input 1
add_interface_port MDIO_MASTER MDIO_OUT mdioout Output 1
add_interface_port MDIO_MASTER MDIO_T mdiot Output 1Code:
Error: get_parameter_value not allowed during GLOBAL
while executing
"get_parameter_value C_MDIO "
invoked from within
"set_interface_property MDIO_MASTER ENABLED [ get_parameter_value C_MDIO ]"What I'd like to know is how should I do it when I want to enable/disable certain interfaces based on user's choice in component configuration in Qsys..
Thanks for any help :)
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A10 SGMII to SGMII communication
Hello there,
I'm trying to build my Ethernet system using Arria 10 SoC board. Now, I'm able to have a successful communication between the FPGA and my PC through ethernet port (all TX/RX packets are working fine). But when I plug the ethernet cable between two FPGAs directly no response is found and all LEDs are off. I believe it is something related to configuring TSE MAC and SGMII? any helps or suggestions would be highly appreciated.
Thank you in advance.
I'm trying to build my Ethernet system using Arria 10 SoC board. Now, I'm able to have a successful communication between the FPGA and my PC through ethernet port (all TX/RX packets are working fine). But when I plug the ethernet cable between two FPGAs directly no response is found and all LEDs are off. I believe it is something related to configuring TSE MAC and SGMII? any helps or suggestions would be highly appreciated.
Thank you in advance.
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↧
3D eye measurement in Transceiver toolkit using Stratix V
Hello,
I'm Insun. I'm a beginner of Stratix.
I've measured 3D eye contour using Stratix V for testing the signal integrity.
However, I don't know how can I convert the "eye width" and "eye height" into real dimension like time and voltage.
I already read a related document "overcome high-speed I/O verification challenges with Stratix V on-die instrumentation" which explains about the 3D eye measurement and concept of phase and vertical steps.
And I understood the concept of phase and vertical steps.
But I need to know the time and voltage of eye width and eye height results, not just sampling steps.
Please help me to get the answer.
Thank you.
I'm Insun. I'm a beginner of Stratix.
I've measured 3D eye contour using Stratix V for testing the signal integrity.
However, I don't know how can I convert the "eye width" and "eye height" into real dimension like time and voltage.
I already read a related document "overcome high-speed I/O verification challenges with Stratix V on-die instrumentation" which explains about the 3D eye measurement and concept of phase and vertical steps.
And I understood the concept of phase and vertical steps.
But I need to know the time and voltage of eye width and eye height results, not just sampling steps.
Please help me to get the answer.
Thank you.
↧
3D eye measurement in transceiver toolkit using Stratix V
Hello,
I'm Insun. I'm a beginner of Stratix.
I've measured 3D eye contour using Stratix V for testing signal integrity.
However, I don't know how can I convert the "eye width" and "eye height" into real dimension like time and voltage.
I already read a related document "overcome high-speed I/O verification challenges with Stratix V on-die instrumentation" which explains about the 3D eye measurement and concept of phase and vertical steps.
And I understood the concept of phase and vertical steps.
But I need to know the time and voltage of eye width and eye height results, not just sampling steps.
Please help me to get the answer.
Thank you.
I'm Insun. I'm a beginner of Stratix.
I've measured 3D eye contour using Stratix V for testing signal integrity.
However, I don't know how can I convert the "eye width" and "eye height" into real dimension like time and voltage.
I already read a related document "overcome high-speed I/O verification challenges with Stratix V on-die instrumentation" which explains about the 3D eye measurement and concept of phase and vertical steps.
And I understood the concept of phase and vertical steps.
But I need to know the time and voltage of eye width and eye height results, not just sampling steps.
Please help me to get the answer.
Thank you.
↧
SPI to Avalon MM Master IP
Hi
I am greatly confused by the SPI to Avalon MM Master IP core in Quartus Prime (16.0). After referring to the online documentation https://www.altera.com/documentation...a1401395000089 and https://www.altera.com/content/dam/a...mbedded_ip.pdf I only have more questions. It seems that the IP core uses encoding in the byte streams. Why is this done and is it possible to turn this off? It seems like an unnecessary step in data processing for the SPI master. Additionally, the read and write processes that illustrated look identical, I'm sure this can't be intentional. What is the "Command" byte sequence that is referred to in these images? I have so many questions! Can someone help me to understand this process better?
Thanks in advance.
I am greatly confused by the SPI to Avalon MM Master IP core in Quartus Prime (16.0). After referring to the online documentation https://www.altera.com/documentation...a1401395000089 and https://www.altera.com/content/dam/a...mbedded_ip.pdf I only have more questions. It seems that the IP core uses encoding in the byte streams. Why is this done and is it possible to turn this off? It seems like an unnecessary step in data processing for the SPI master. Additionally, the read and write processes that illustrated look identical, I'm sure this can't be intentional. What is the "Command" byte sequence that is referred to in these images? I have so many questions! Can someone help me to understand this process better?
Thanks in advance.
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