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QSYS I2C Slave to Avalon Addressing Issue

August 23, 2017, 6:41 am
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I have a QSYS design in which the peripherals do not appear to be decoded correctly. They work fine when controlled by System Console through the JTAG port, but not when controlled through the I2C port.

My design includes a QSYS system with the following components:
  • JTAG to Avalon Master Bridge
  • Altera I2C Slave to Avalon MM Bridge
  • 3 x Altera PIO (at addresses 0x0 to 0x0f, 0x10 to 0x1f, 0x20 to 0x2f)
  • 4 x quadrature encoder counter (my designs; at 0x30 to 33, 0x34 to 0x37, 0x38 to 0x3b, 0x3c to 0x3f)

I can go into System Console and execute read and write TCL commands through the JTAG port and all the peripherals operate properly and are located at their correct addresses. I have four fixed bytes at addresses 0x00-0x03 and they show up only at addresses 0x00-0x03, as expected.

When controlled through the I2C port, I see the same fixed bytes at address 0x00-0x03, but I also see them repeated every 0x10 addresses (at 0x10-0x13, 0x20-23, etc...). I can't access or control any other peripherals. [ I am using the linux i2cget and i2cset commands ]

I can see the correct address being sent using an oscilloscope.The I2C signals look clean. I am using the I2C Slave in 8-bit address mode with no address bit stealing. I am using Quartus distribution 17.0.2 Build 602. The device is a 10M02SCU169I7G.

Thank you in advance.
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Wrong results when running design on hardware

August 23, 2017, 9:18 am
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Hello,

My design is made of a chain of single work-item kernels transfering data using channels.
It runs fine on emulation, and the FPGA binary is built correclty (95% of estimated usage).

Here is my problem:
Both emulation and hardware run up to completion (no deadlock), but only the emulation produces correct results.

The machines used for development and deployment are different, and it is not possible to use the same machine for both steps.
The only part that is recompiled in the deployment machine is the host binary, so I guess that could be the issue but not sure where to start looking for the problem cause.

Also, the host part processes the output from the FPGA after the latter has finished. Could any host compilation be affecting results?
Did anyone experience a similar issue?

Any hints will be apprecciated.

Leonardo
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In PCIe DMA reference design, export TX Slave interface to allow use in rest of FPGA

August 23, 2017, 9:25 am
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Extremely new to QSys and couldn't find good information by searching. :confused:

How do I export the TX Slave interface (TXS) in the attached QSys system to make it available to the rest of the FPGA design? I would like both the internal sources (rd_dcm_master and wr_dcm_master) and external sources (elsewhere in the FPGA) to be able to use this interface to master PCIe transactions. i.e., I would like QSys to create an arbiter and export one of the sources.

Thanks!
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Avalon-MM to LPDDR2 HMC IP not permitting burst counts larger than 4?

August 23, 2017, 10:24 am
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Hello,

I'm using one of the Hard Memory Controllers on a 5CGXFC5C6F27C7 from the Terasic Cyclone V GX Starter Kit. The board has a single LPDDR2 chip. I've instantiated the IP, and can get it working perfectly well as long as I don't try to burst reads larger than 4 transfers together (see screenshot).

If I set burstcount to 8 or higher, the core seems to accept the read command (waitrequest_n goes low and then high again), but never returns any data (see screenshot, readdatavalid stays low indefinitely).

I've set AVL_MAX_SIZE to 128 in the MegaWizard, which should result in a maximum burst size of 128. I've included the top level of the generated IP that shows the parameters I've used.

Any clues as to why larger bursts seem to be getting rejected? I must be doing something wrong, but I've run out of ideas. The requests appear to match the Avalon-MM burst timing diagrams shown in the spec:
https://www.altera.com/content/dam/a...valon_spec.pdf

I see the same behavior under Quartus 16.1.2 and 17.0.
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Dynamic phase reconfiguration of ALTPLL in Cyclone IV

August 23, 2017, 12:35 pm
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I am trying to dynamically control the phase of a clock signal by using an ALTPLL.
Generated a the ALTPLL with phase control signals, but I have not been able to find a detailed description of the signals, timing diagrams or design examples. The ALTPLL IP Core User Guide does not contain much.

Signals that I need more information on are:
Input [2:0] phasecounterselect
Input phaseupdown
Input phasestep
Input scanclk
Output locked
Output phasedone

Does anybody have more information on this.
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BCD 2 digit Adder

August 23, 2017, 3:11 pm
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Hi guys, im doing a project for a course.
we are making a BCD adder ( first by making full adder , 4 bits adder, then use 4 bit adder to make the BCD adder)
the system will add 6 if the sum is more than 10
i have problems with adding 6 here's a photo





i have that problem b[2], b[1] drives an input pin.

i learned to use quartus today. Sadly my instructor asked us to learn it by ourselves and i got tried can you help me. Thanks in advance.
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Avalon I2C (Master) Core only supports MM interface -OR- ST interface, not both

August 23, 2017, 5:42 pm
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The Avalon I2C (Master) Core only supports memory mapped access to the command and receive FIFOs -or- streaming access to the FIFOs, not both. This isn't precisely a bug, but is poor design. There's no reason that selecting the streaming access to the FIFO option for the I2C Master in QSys shouldn't allow either.

I'm tempted to "fix" it in the altera_avalon_i2c_csr.v file, but I'm not sure of the ramifications. Has anyone tried this?

Of course, the downside is that the library would have to be pulled out of the QSys flow so that it didn't keep getting overwritten by the standard library (at least, that's my understanding of how QSys works).

Further, it appears that the Nios II I2C driver only supports the memory mapped version. This seems reasonable enough, given that the Nios II doesn't _have_ a streaming port, but does make things inconvenient.

Maybe the simpler thing is to acknowledge defeat and write my own I2C driver for the Nios (utilizing a custom memory mapped streaming channel chunk of verilog).

Thoughts?

Calvin
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arria 10 jtag problem while using ds5

August 23, 2017, 7:30 pm
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hi all,
I canot connect to my arria10 board when using ds5 to debug hps,but in quartus16.1 programmer tool i can see the hps device.
which the differences between the ds5 and the quartus about thire jtag connection things?
does someone take any problems like this?

best wishes,
hl
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Referent Clock PCIe

August 23, 2017, 9:36 pm
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Hi guys


I'd like if you can help my about PCIe pins connector.


I have to communicate by PCIe two FPGAs, so I have to build a PCB like "Mother Board" where my FPGAs will communicate.
My PCB will has a two PCIe female connector in orden to establish PCIe communication. I've searched by internet and I noticed that there are a differential pins called REFCLK.
Some websites I've watched that they use REFCLK and another don't, but they don't tell nothing about REFCLK pins, so I'd like someone can help in orden to don't make mistake when make my PCB.


My question is:
If I connect one FPGA to another FPGA by PCIe, Must I ALWAYS use pins REFCLK or not???
I've searched by internet and I always find about lanes Rx and Tx, but I haven't found a good information about REFCLK.


My another question is:
if one FPGA is root- port and another is endpoint.....REFCLK is established by root-port or not ??


Thanks for your replys.
Regards.
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Quartus license activated using FPGA Devolepemnt kit expired in 3 months

August 23, 2017, 10:07 pm
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We purchased an Arria 10 FPGA development kit (DK-DEV-10AX115S-A-0H) in the year 2016. Using the NIC ID of the board a license file for Quartus Prime Version 17.0.0 Standard edition was generated on 29 may 2017.
Later on 16th August 2017 we got a message saying that the license got expired and we were unable to use Quartus for generating programming files.
As per our understanding the development kit we purchased comes with a free subscription to Quartus for the life time and maintenance support for one year from date of license generation.

Currently we are running the software on a 30 days grace period. Please help me to have a better understanding of the issue and possible remedies at the earliest.
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DE10 Nano problems with linux OS

August 23, 2017, 11:38 pm
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Good day.

I recently bought the DE10 nano. When I connect it to the HDMI screen and start linux. I have some problems and doubts.


--I can not change the resolution of the screen, it has a default one that automatically configures but not all the monitors are adjusted properly.
- The Linux distribution does not shut down or restart, . I had to remove the power supply to turn it off.
-Only has a port to use or a keyboard or a mouse. Is it possible to use a USB hub with external power to use both (mouse and keyboard) at the same time ?.
-Is there any manual on Linux OS?

Thanks in advance for the support.
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Quartus Prime Lite Edition Clock

August 24, 2017, 1:17 am
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Dear all;
I designed a circuit in Quartus. When I control output signals of circuit with oscilloscope I can not get correct results. I think reason of wrong measurement result is clock signal. I didn't assign H1 input as clock, but Quartus assigns H1 as clock. I followed this path Assignments->Settings->Advanced Settings->Auto Global Clock->Off to turn off global clock. But under clocks H1 appear as clock. Could you help me please how I can close global clock assignment? Sincerely.
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Epf10k100

August 24, 2017, 2:37 am
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Hi there

I have downloaded Quartus II 9.0 SP2 Web Edition believing that it would support all FLEX devices but I don't see EPF10K100 device which I am after; I do see EPF10K70 device and below. Please advise what I need to do. I would appreciate if you could help me ASAP. Thanks very much
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Don't see Inbox - Messaging

August 24, 2017, 3:41 am
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Hi There,

Just joined the forum! I don't see Inbox - Messaging. I also don't see email button to send emails to Members List. Please help. Thanks
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MAX 10 Startup Delay

August 24, 2017, 10:46 am
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I am experiencing a long delay between power up and the MAX 10 device starting to operate. This delay can be anything from under 1 second (acceptable) to 40 seconds or more.


  • Device: 10M02SCE144C8G single supply (3.3V) device.
  • Programmer Hardware: ByteBlaster II programmer through the JTAG port.
  • Compiler / Programmer Software: Quartus Prime 16.1.2


Device Settings:

  • Operating Settings and Conditions: Voltage, VCCA voltage: 3.3V
  • Device Assignments -Voltage
    • Default I/O standard: 3.3-V LVTTL
    • Core voltage: 1.2V (default and cannot be changed)

  • Device Assignments - Configuration:
    • Configuration scheme: Internal Configuration
    • Configuration mode: Single Uncompressed Image (96Kbits UFM)
    • Force VCCIO to be compatible with configuration I/O voltage - YES
    • Generate compressed bitstreams - ON

  • Device Assignments - General (check boxes):
    • Auto-restart configuration after error - ON
    • Release clears before tri-states - OFF
    • Enable device-wide reset (DEV_CLRn) - OFF
    • Enable device-wide output enable (DEV_OE) - OFF
    • Enable nCONFIG,nSTATUS, and CONF_DONE pins - OFF
    • Enable JTAG pin sharing - OFF
    • Enable CONFIG_SEL pin - OFF

  • The Configuration Pins listed above are assigned as outputs to drive logic, except for nCONFIG which is connected to a pull-up resistor (100K to 3.3V) and a push button switch.
  • Power On Reset scheme: Instant ON (this is default and cannot be changed)


Power Supply:
  • Voltage: 3.3V
  • 3.3V Ramp Up time (tRAMP): 980uS


This delay also occurs after programming the device using a .pof file. When using a .sof file to program the device, the start up is instant. I have tried 3 different boards and all three boards have the same issue / behavior.

Any advice / ideas? What am I missing here?

Regards,
Sean
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changing the jagClock

August 24, 2017, 11:47 am
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hi all,

I'm trying to change the clk of my jtag. The problem is this command works perfectly fine:
"jtagconfig --getparams 1 JtagClock"

the output is "6M"


but when I try to change it by:
"jtagconfig --setparams 1 JtagClock 24M"

it says "no parameter named JtagClock"

do you have any idea what the problem might be?
I'm using the latest version of Quartus on Linux

Thanks,
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aocl diagnose failed : AAL issues

August 24, 2017, 12:06 pm
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Hello
I am trying to run a .aocx file.
when i do aocl diagnose , i get the following :
aocl diagnose: Running diagnose from /home/saravind/bdw_fpga_pilot_opencl_v1.0/bdw_fpga_pilot_opencl_bsp_v1.0/linux64/libexec
ccip_mmd.cpp:1003:serviceAllocateFailed() **Error : Failed to allocate Service
ccip_mmd.cpp:1123:runtimeAllocateServiceFailed() **Error : Runtime AllocateService failed
ccip_mmd.cpp:453:open() **Error : ALIAFU allocation failed


Error: Failed to initialize the OpenCL/AAL system.
Error: Ensure a correct OpenCL image is programmed on the FPGA, and that the CCI driver has been loaded.
Using platform: Altera SDK for OpenCL
CL device ID = 64
Failed clGetDeviceIDs.
Error code: -1
aocl diagnose: failed.

I think this issue is due to some library environment variable settings.
Please let me know if you know of any possible reasons/solutions to this issue.
Thank you.
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UART RS232 connection between Matlab and NiosII

August 24, 2017, 3:18 pm
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Hello,

There is sync problem between niosII and Matlab. I tried to send a uint8 data from Matlab to Nios II via RS232 but the data is sometimes missed or repeated. I tried delaying read in the nios II or sending data in Matlab but it doesn't work.

Is there any recommendation for the implementation?

Thank you

Best regards
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Error: Compiler Error, not able to generate hardware

August 24, 2017, 2:37 pm
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Can someone help me with this issue:

[........hello_world]$ aoc -v device/hello_world.cl -o bin/hello_world.aocx --board a10gx
aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/fpga
You are now compiling the full flow!!
aoc: Selected target board a10gx
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
Checking if memory usage is larger than 100%
aoc: First stage compilation completed successfully.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_sender_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_reorder_const_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_writestream_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_boardtest_system.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_receiver_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_nop_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_readstream_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_read_writestream_cra_cra_rin g.ip.
Error: Quartus Prime IP Generation Tool was unsuccessful. 8 errors, 0 warnings
Error (293001): Quartus Prime Full Compilation was unsuccessful. 10 errors, 0 warnings
Error: Flow compile (for project /home/fpga/Downloads/hello_world/bin/hello_world/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error (23031): Evaluation of Tcl script /home/fpga/intelFPGA_pro/17.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 17 errors, 0 warnings
Error: Compiler Error, not able to generate hardware
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aoc cannot find valid licences file

August 24, 2017, 8:16 pm
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Hello. I'm trying out compiling Altera OpenCL on a new workstation. After acquiring the license file and installing Quartus II and OpenCL SDK. I tried to compile some OpenCL.
But aoc refuses to do so with the following message.


Code:
marty@labpc:~$ aoc test.cl -o test --board c5soc
Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to test/test.log for details.
But I can launch Quartus successfully and I'm sure that I have OpenCL licences(It says so in Altera Licensing Center).
Why is this happning. How can i diagnose this?

OS: Ubuntu 14.04
CPU: Ryzen R7 1700X
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