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Installation issue Altera EDS 17.0.0.290 on Ubuntu 16.04.3 LTS

August 24, 2017, 10:52 pm
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Hello,

I have installd the EDS on my Linux System \usr\local\DS-5\
Compiling my code runs well and the Eclise GUI seemto be working well.
But I get always the following error message when I try to open the USB Blaster in the Debug config in the Eclipse GUI.
Error executing the device_browser.py

When I execute the device_browser.py stand alone in the terminal I get:
ImportError: Can't find modul Java.lang

Additional when I run the post_installation Shell script from the LINUX terminal, I get the message: "No Default toolkit set" at the end.

It would be very nice if somebody could help me.

Regards

Tom
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SPI to Avalon MM Master IP

August 23, 2017, 6:42 am
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Hi

I am greatly confused by the SPI to Avalon MM Master IP core in Quartus Prime (16.0). After referring to the online documentation https://www.altera.com/documentation...a1401395000089 and https://www.altera.com/content/dam/a...mbedded_ip.pdf I only have more questions. It seems that the IP core uses encoding in the byte streams. Why is this done and is it possible to turn this off? It seems like an unnecessary step in data processing for the SPI master. Additionally, the read and write processes that illustrated look identical, I'm sure this can't be intentional. What is the "Command" byte sequence that is referred to in these images? I have so many questions! Can someone help me to understand this process better?

Thanks in advance.
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Quartus license activated using FPGA Devolepemnt kit expired in 3 months

August 23, 2017, 10:07 pm
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We purchased an Arria 10 FPGA development kit (DK-DEV-10AX115S-A-0H) in the year 2016. Using the NIC ID of the board a license file for Quartus Prime Version 17.0.0 Standard edition was generated on 29 may 2017.
Later on 16th August 2017 we got a message saying that the license got expired and we were unable to use Quartus for generating programming files.
As per our understanding the development kit we purchased comes with a free subscription to Quartus for the life time and maintenance support for one year from date of license generation.

Currently we are running the software on a 30 days grace period. Please help me to have a better understanding of the issue and possible remedies at the earliest.
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DE10 Nano problems with linux OS

August 23, 2017, 11:38 pm
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Good day.

I recently bought the DE10 nano. When I connect it to the HDMI screen and start linux. I have some problems and doubts.


--I can not change the resolution of the screen, it has a default one that automatically configures but not all the monitors are adjusted properly.
- The Linux distribution does not shut down or restart, . I had to remove the power supply to turn it off.
-Only has a port to use or a keyboard or a mouse. Is it possible to use a USB hub with external power to use both (mouse and keyboard) at the same time ?.
-Is there any manual on Linux OS?

Thanks in advance for the support.
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Quartus Prime Lite Edition Clock

August 24, 2017, 1:17 am
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Dear all;
I designed a circuit in Quartus. When I control output signals of circuit with oscilloscope I can not get correct results. I think reason of wrong measurement result is clock signal. I didn't assign H1 input as clock, but Quartus assigns H1 as clock. I followed this path Assignments->Settings->Advanced Settings->Auto Global Clock->Off to turn off global clock. But under clocks H1 appear as clock. Could you help me please how I can close global clock assignment? Sincerely.
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Epf10k100

August 24, 2017, 2:37 am
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Hi there

I have downloaded Quartus II 9.0 SP2 Web Edition believing that it would support all FLEX devices but I don't see EPF10K100 device which I am after; I do see EPF10K70 device and below. Please advise what I need to do. I would appreciate if you could help me ASAP. Thanks very much
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Don't see Inbox - Messaging

August 24, 2017, 3:41 am
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Hi There,

Just joined the forum! I don't see Inbox - Messaging. I also don't see email button to send emails to Members List. Please help. Thanks
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MAX 10 Startup Delay

August 24, 2017, 10:46 am
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I am experiencing a long delay between power up and the MAX 10 device starting to operate. This delay can be anything from under 1 second (acceptable) to 40 seconds or more.


  • Device: 10M02SCE144C8G single supply (3.3V) device.
  • Programmer Hardware: ByteBlaster II programmer through the JTAG port.
  • Compiler / Programmer Software: Quartus Prime 16.1.2


Device Settings:

  • Operating Settings and Conditions: Voltage, VCCA voltage: 3.3V
  • Device Assignments -Voltage
    • Default I/O standard: 3.3-V LVTTL
    • Core voltage: 1.2V (default and cannot be changed)

  • Device Assignments - Configuration:
    • Configuration scheme: Internal Configuration
    • Configuration mode: Single Uncompressed Image (96Kbits UFM)
    • Force VCCIO to be compatible with configuration I/O voltage - YES
    • Generate compressed bitstreams - ON

  • Device Assignments - General (check boxes):
    • Auto-restart configuration after error - ON
    • Release clears before tri-states - OFF
    • Enable device-wide reset (DEV_CLRn) - OFF
    • Enable device-wide output enable (DEV_OE) - OFF
    • Enable nCONFIG,nSTATUS, and CONF_DONE pins - OFF
    • Enable JTAG pin sharing - OFF
    • Enable CONFIG_SEL pin - OFF

  • The Configuration Pins listed above are assigned as outputs to drive logic, except for nCONFIG which is connected to a pull-up resistor (100K to 3.3V) and a push button switch.
  • Power On Reset scheme: Instant ON (this is default and cannot be changed)


Power Supply:
  • Voltage: 3.3V
  • 3.3V Ramp Up time (tRAMP): 980uS


This delay also occurs after programming the device using a .pof file. When using a .sof file to program the device, the start up is instant. I have tried 3 different boards and all three boards have the same issue / behavior.

Any advice / ideas? What am I missing here?

Regards,
Sean
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changing the jagClock

August 24, 2017, 11:47 am
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hi all,

I'm trying to change the clk of my jtag. The problem is this command works perfectly fine:
"jtagconfig --getparams 1 JtagClock"

the output is "6M"


but when I try to change it by:
"jtagconfig --setparams 1 JtagClock 24M"

it says "no parameter named JtagClock"

do you have any idea what the problem might be?
I'm using the latest version of Quartus on Linux

Thanks,
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aocl diagnose failed : AAL issues

August 24, 2017, 12:06 pm
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Hello
I am trying to run a .aocx file.
when i do aocl diagnose , i get the following :
aocl diagnose: Running diagnose from /home/saravind/bdw_fpga_pilot_opencl_v1.0/bdw_fpga_pilot_opencl_bsp_v1.0/linux64/libexec
ccip_mmd.cpp:1003:serviceAllocateFailed() **Error : Failed to allocate Service
ccip_mmd.cpp:1123:runtimeAllocateServiceFailed() **Error : Runtime AllocateService failed
ccip_mmd.cpp:453:open() **Error : ALIAFU allocation failed


Error: Failed to initialize the OpenCL/AAL system.
Error: Ensure a correct OpenCL image is programmed on the FPGA, and that the CCI driver has been loaded.
Using platform: Altera SDK for OpenCL
CL device ID = 64
Failed clGetDeviceIDs.
Error code: -1
aocl diagnose: failed.

I think this issue is due to some library environment variable settings.
Please let me know if you know of any possible reasons/solutions to this issue.
Thank you.
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Error: Compiler Error, not able to generate hardware

August 24, 2017, 2:37 pm
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Can someone help me with this issue:

[........hello_world]$ aoc -v device/hello_world.cl -o bin/hello_world.aocx --board a10gx
aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/fpga
You are now compiling the full flow!!
aoc: Selected target board a10gx
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
Checking if memory usage is larger than 100%
aoc: First stage compilation completed successfully.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_sender_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_reorder_const_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_writestream_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_boardtest_system.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_kernel_receiver_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_nop_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_readstream_cra_cra_ring.ip.
Error: Error opening /home/fpga/Downloads/hello_world/bin/hello_world/ip/kernel_system/kernel_system_avs_mem_read_writestream_cra_cra_rin g.ip.
Error: Quartus Prime IP Generation Tool was unsuccessful. 8 errors, 0 warnings
Error (293001): Quartus Prime Full Compilation was unsuccessful. 10 errors, 0 warnings
Error: Flow compile (for project /home/fpga/Downloads/hello_world/bin/hello_world/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.
Error (23031): Evaluation of Tcl script /home/fpga/intelFPGA_pro/17.0/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 17 errors, 0 warnings
Error: Compiler Error, not able to generate hardware
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UART RS232 connection between Matlab and NiosII

August 24, 2017, 3:18 pm
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Hello,

There is sync problem between niosII and Matlab. I tried to send a uint8 data from Matlab to Nios II via RS232 but the data is sometimes missed or repeated. I tried delaying read in the nios II or sending data in Matlab but it doesn't work.

Is there any recommendation for the implementation?

Thank you

Best regards
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aoc cannot find valid licences file

August 24, 2017, 8:16 pm
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Hello. I'm trying out compiling Altera OpenCL on a new workstation. After acquiring the license file and installing Quartus II and OpenCL SDK. I tried to compile some OpenCL.
But aoc refuses to do so with the following message.


Code:
marty@labpc:~$ aoc test.cl -o test --board c5soc
Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to test/test.log for details.
But I can launch Quartus successfully and I'm sure that I have OpenCL licences(It says so in Altera Licensing Center).
Why is this happning. How can i diagnose this?

OS: Ubuntu 16.04
CPU: Ryzen R7 1700X
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Installation issue Altera EDS 17.0.0.290 on Ubuntu 16.04.3 LTS

August 24, 2017, 10:52 pm
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Hello,

I have installd the EDS on my Linux System \usr\local\DS-5\
Compiling my code runs well and the Eclise GUI seemto be working well.
But I get always the following error message when I try to open the USB Blaster in the Debug config in the Eclipse GUI.
Error executing the device_browser.py

When I execute the device_browser.py stand alone in the terminal I get:
ImportError: Can't find modul Java.lang

Additional when I run the post_installation Shell script from the LINUX terminal, I get the message: "No Default toolkit set" at the end.

It would be very nice if somebody could help me.

Regards

Tom
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Cyclone III Development Board - Video Image Processing Suite - Hardware revisions?

August 25, 2017, 3:32 am
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Hi,

I'm using the Cyclone III Development Board and the Video Image Processing Suite for many years.
I use the VIP-reference-design on some boards from the year 2007 a it's working fine.

In the near future I ordered three new boards with hardware from 2011, but te VIP-reference-design isn't working on them.

It works only on the old boards. I cannot see many differences on the boards.

I'm using the orginal .sof from Altera and a self-compiled .sof.
Using the self-compiled .sof I can figure out, that the Nios-programm doesn't start properly.
Nios can program and verify the .elf - but it doesn't start.

Is there a (relevant) change in the harware revision?

Best regards

Mark
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DSP Block Balancing settings using OpenCL

August 25, 2017, 4:40 am
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I am trying to compile a multi-kernel file in which one kernel, say A, has 16-bit arithmetic operations. What I see is when I change various parameters in other kernels, DSP usage in kernel A sometimes changes to slice usage. I want to control it or at least keep it consistent. I saw that there is DSP Block Balancing setting in Quartus. How can I control it from OpenCL SDK?
Thanks
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FAST_OUTPUT_ENABLE_REGISTER Assigment not recognized

August 25, 2017, 5:47 am
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I have to following code which to my understanding should be trivial to be implemented via a fast output enable register. However, the FAST_OUTPUT_ENABLE_REGISTER assignment to the pin is ignored.

Code:
entity test_comp is
  port(
    irq : out std_logic;
    ...
  );
end entity;

architecture rtl of test_comp is
  signal irq_assert : std_logic;
begin
  irq <= '0' when irq_assert else 'Z'; -- fast output enable is ignored.
  ...
  process(reset,clk)
  begin
    if reset then
      irq_assert <= '0';
    elsif rising_edge(clk) then
      ...
      if some_condition then
        irq_assert <= '1';
      else
        irq_assert <= '0';
      end if;
      ...
    end if;
  end process;
  ...
end architecture rtl;
The following slight modification does not have the problem. The assignment is accepted.

Code:
entity test_comp is
 port(
  irq : out std_logic;
  ...
  );
end entity;

architecture rtl of test_comp is
  signal irq_assert : std_logic;
  signal irq_level : std_logic; -- must use irq_level somehow or assign syn_keep attribute  to avoid it being removed.

  attribute syn_keep: boolean;
  attribute syn_keep of irq_level : signal is true;
begin
  irq <= irq_level when irq_assert else 'Z';
  ...
  process(reset,clk)
  begin
    if reset then
    elsif rising_edge(clk) then
      ...
      if some_condition then
        irq_assert <= '1';
      else
        irq_assert <= '0';
      end if;
      ...
    end if;
  end process;
  ...
end architecture rtl;
As requested I have extended the sample by some code to drive the irq_assert signal. It really is that simple. A single condtion either sets the bit or clears it in a clocked process with the regular asynchronous reset. I really don't see anything fancy here.
Can someone clarify what is happening here?
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arm baremetal usb examples

August 25, 2017, 11:34 am
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Hi there,

I'm trying to develop a baremetal application with cyclone V arm, the user case is very much alike here ( https://alteraforum.com/forum/showthread.php?t=45542 ). As many of the posts here at the forum I can't find the right driver or library. Have those libraries be released by altera? Any one could kindly give me a link of the simple example of this kind application? thanks!
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Quartus II version to compile legacy product using EP1C4F400C6?

August 25, 2017, 12:01 pm
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Hi,

I need to make some design changes to a legacy product using a EP1C4F400C6. What version of Quartus II should I download to do this?

Thanks,
Richard
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My 1st MAX 10 design

August 25, 2017, 12:05 pm
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Well, I can't hide that I'm a bit scared. This is my 1st FPGA design and I'm doing it without having the MAX 10 here to test first.
I know that I might be asking too much :) but do you guys see anything wrong with the FPGA connections on my schematics? It's the MAX 10 10M02 144-pin EQFP package (10M02SCE144C8G).

Disregard the banks 3,5,6,8 on the bottom half. Those have the project-specific nets. My main concerns are with the JTAG port, power and clock input:

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