Altera's LPDDR3/4 Supported Reference Board

August 31, 2017, 12:35 am

≫ Next: DE1-SOC power button non-functioning in AS/EPCS mode

Hi,

I need a board with LPDDR3 or LPDDR4 to validate my IP. Do Altera have such board which contains LPDDR3/4?

Thanks & Regards,
Vijay

↧

DE1-SOC power button non-functioning in AS/EPCS mode

August 31, 2017, 6:24 am

≫ Next: Simulink FPGA in the Loop with QSYS-Components

≪ Previous: Altera's LPDDR3/4 Supported Reference Board

Apologies if this has been answered elsewhere, I seem to have read about the issue but can't locate my source now.

I've transferred my design to EPCS memory of the DE1-SOC board. Now regardless of the state of the red power button, whenever I plug in the DC adaptor, the board comes up immediately with no way apparently to switch it off except pulling the plug.

I liked being able to power up/down the board using the red button while using JTAG mode, can it not be used in AS mode at all? Can I power the board down under software-control?

↧

Simulink FPGA in the Loop with QSYS-Components

August 31, 2017, 9:00 am

≫ Next: OpenCL apparently stuck at compiling vectorAdd example

≪ Previous: DE1-SOC power button non-functioning in AS/EPCS mode

In Simulink you can use the FPGA-in-the-Loop wizard to generate blocks, which run during the simulation time on the FPGA hardware. Basically, you create a Quartus project and feed all generated HDL files in this wizard and he generates a Ready to Use Simulink block.

I own a Terasic DE2-115 board and went through the tutorials and examples of my Matlab(R2017a) installation relating to this topic and Ive also created some own examples with Quartus Prime 17 and Megafunctions like lpm_add_sub etc. Everything works fine!

However, when I do the same steps and use QSYS-components in the Quartus project I get errors during the compilation. The Wizard calls Quartus and Quartus always reports for example:

Node instance "merlin_master_translator" instantiates undefined entity "altera_merlin_master_translator". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.

It seems Quartus cant find necessary libraries for the involved QSYS IP components. If I compile the same project direct in Quartus I get no errors (..except the infos about the unused inputs/outputs for Simulink)! Unfortunately, there is apparently no way to generate the desired block then.

Ive attached a very simple example (see: QSYS_FIL.zip)
Lets say I want to replace the DE2-115 Flash block with a Hardware(FIL) block and read the first 16 values of the onboard flash. (see: 1_Simulink.PNG)

:
First, I create a flash controller with QSYS using three IP cores: clock, flash ip and Avalon MM Master Translator and afterwards I connect the pins with the FPGA.

Now I enter all generated files in the wizard, adjust the desired I/O ports for Simulink and start the build process. After a while it stops with the mentioned errors.

Im quite frustrated since those steps work as long there is no QSYS IP involved.
Does anyone have experience with that? Why is Quartus unable to find those specific libraries in this case? Am I wrong with my idea of this QSYS-design?

Attached Images

1_Simulink.PNG (17.4 KB)

Attached Files

QSYS_FIL.zip (2.68 MB)

↧

OpenCL apparently stuck at compiling vectorAdd example

August 31, 2017, 10:27 am

≫ Next: Using SignalTap to capture high rate clocks?

≪ Previous: Simulink FPGA in the Loop with QSYS-Components

Hello, I am currently struggling to make the example provided in ftp://ftp.altera.com/up/pub/Intel_Ma...als/OpenCL.pdf work.

The compilation seems to be stuck forever. It's been going on for several hours already. I really have no clue on what the problem could be.

This is the command I'm trying to make work

Quote:

aoc device/vectorAdd.cl -o bin/vectorAdd.aocx --board de1soc_sharedonly

Note that I changed the name provided in the tutorial vector_add to vectorAdd to match the actual name. However, I tried running the boardtest example with the same result, which had already the same name.

The command aoc --list-boards does correctly return de1soc_sharedonly.

I attached the quartus_sh_compile.log which I learned could help in troubleshooting from another thread.

I am currently running Windows 10 Education 64 bit ( 10.0, build 14393 ), with Quartus Prime 17.0 Build 595 04/25/2017 SJ Standard Edition and a Terasic De1SoC board. My system has 16GB of ram memory, 63.7 GB of free space on the SSD where quartus and opencl are installed, and a 5930k Intel core i7 processor.

This is the output of the command aoc --version:

Version 17.0.0 Build 595
Copyright (C) 2017 Intel Corporation

Attached Images

Immagine.jpg (17.7 KB)

Attached Files

quartus_sh_compile.zip (24.3 KB)

↧

Using SignalTap to capture high rate clocks?

August 31, 2017, 3:44 pm

≫ Next: AOC Error while running hello world

≪ Previous: OpenCL apparently stuck at compiling vectorAdd example

Hello, I would to know how accurate SignalTap is when capturing signals such as an 80-Mhz clock from a pll that is used to drive logic? When I view such a signal I see a non 50-percent duty cycle clock. My reference clock for SignalTap is my 80Mhz input clock. Could this be internal jitter on the clock from a pll?

Any ideas?

Thanks,
Joe

↧

AOC Error while running hello world

August 31, 2017, 5:55 pm

≫ Next: Unexpected performance results of OpenCL kernel execution

≪ Previous: Using SignalTap to capture high rate clocks?

Command used: aoc -v device/hello_world.cl -o bin/hello_world.aocx --board a10gx

Output:
aoc: First stage compilation completed successfully.
Error: Peak virtual memory: 1036 megabytes
Error: Processing ended: Thu Aug 31 17:34:28 2017
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error: ip-generate FAILED.

hello_world.log:
Error (125091): Tcl error: ERROR: Illegal assignment: PR_ALLOW_GLOBAL_LIMS. Specify a legal assignment name.

while executing
"set_instance_assignment -name PR_ALLOW_GLOBAL_LIMS ON -to freeze_wrapper_inst|kernel_system_clock_reset_rese t_reset_n"
(file "flat.qsf" line 66)
Error (125036): Assignment value PR_IMPL for assignment REVISION_TYPE is illegal File: .../top.qsf Line: 27
Info (125063): set_global_assignment -name REVISION_TYPE PR_IMPL File: .../hello_world/bin/hello_world/top.qsf Line: 27
Info (125076): Specified assignment value "REVISION_TYPE" must include one of the following values: "Aggregate", "Base", "CVP", "Mask", "Reconfigurable"
Error (125080): Can't open project -- Quartus Prime Settings File contains one or more errors
------------------------------------------------
ERROR: Can't open project: top

while executing
"project_open $project_name -revision $revision_name"
(file "scripts/pre_flow_pr.tcl" line 38)
------------------------------------------------
Error (23031): Evaluation of Tcl script scripts/pre_flow_pr.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 1036 megabytes
Error: Processing ended: Thu Aug 31 17:34:28 2017
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00

↧

Unexpected performance results of OpenCL kernel execution

August 31, 2017, 5:36 pm

≫ Next: How to suppress Fatal Modelsim error vsim-3807

≪ Previous: AOC Error while running hello world

Hi,

I have a simple dummy kernel that is being used for some benchmarking goal. Below is my OpenCL kernel:

Code:

__attribute__((num_compute_units(1)))

__attribute__((num_simd_work_items(16)))

__attribute__((reqd_work_group_size(256,1,1)))

__kernel void WGS256MAPI16LL1048576(const __global float *GIn, __global float *GOut, const int M, const int N, const int P) {

    const int XGL = get_global_id(0);

    const int XGRid = get_group_id(0);

    const int XGRnum = get_num_groups(0);

    const int XLSize = get_local_size(0);

    const int XLid = get_local_id(0);

    // Just a private variable

    float temp = 1.0;









    // Start of a new level of for loop

    long baseIndex1 = XGRid*XLSize*16+XLid;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    temp += temp * M;

    ...

    temp += temp * M;



    GOut[XGRid*XLSize*16+XLid] = temp;

}

As it's clear in the code, my kernel is basically does nothing special. I also have removed any DRAM access. The kernel is performing 1024 "FMA" operations and save the result into the memory, just to make sure the computation is not being optimized out by the compiler.
I deploy this kernel as a NDRange, on a Nallatech 385A. It also has been compiled with Altera 16.0 compiler. Now, basically I would like to calculate the performance of my kernel as a number of floating points per second (GFlops). Here is the section of my code, which is responsible to deploy the kernel and calculate the performance:

Code:

Event evKernel (algorithm->getKernelName ());

err = clEnqueueNDRangeKernel (queue, kernel, algorithm->getWorkDim(),

                                       NULL,

                                       globalWorkSize,

                                       localMemSize,

                                       0, NULL, &evKernel.CLEvent());

CL_CHECK_ERROR (err);

err = clWaitForEvents (1, &evKernel.CLEvent());

 

evKernel.FillTimingInfo ();

As it's clear, it logs the beginning and then end of the execution. Also I'm making sure I'm waiting for the kernel termination being triggered and then log the time.

Using all above configuration, the FPGA can deliver around 2451 GFlops, which is completely outperforming the theoretical performance as 1.5TFlops. I have checked the generated Verilog file and seen all FMA operations have been generated. Now my question is, am I doing anything wrong that I'm getting this non-sense performance number?

Thanks,
Saman

↧

How to suppress Fatal Modelsim error vsim-3807

August 31, 2017, 10:05 pm

≫ Next: Start to make Uboot.img H/W: DE0-nano-Soc (Atlas-soc,Dev-Platform, Cyclone 5)

≪ Previous: Unexpected performance results of OpenCL kernel execution

Is there a way to suppress a Fatal error in Modelsim? I'm guessing not, but it would be useful at times. Fore example, I've created a multiplier where one input is signed, the other unsigned, and the result of course signed. Quartus can't seem to infer this, so I generate core. Quartus generates a component template:

Code:

    component dds_mult is

        port (

            result     : out std_logic_vector(24 downto 0); 

            dataa_0 : in  std_logic_vector(11 downto 0);

            datab_0 : in  std_logic_vector(12 downto 0);

            clock0  : in  std_logic

        );

    end component dds_mult;

To avoid type conversions, I always modify this in my code to be:

Code:

    component dds_mult is

        port (

            result     : out signed(24 downto 0); 

            dataa_0 : in  unsigned(11 downto 0);

            datab_0 : in  signed(12 downto 0);

            clock0  : in  std_logic

        );

    end component dds_mult;

This synthesizes fine and works correctly and even SignalTap is happy.

However, Modelsim yells at me giving an error:

# ** Fatal: (vsim-3807) Types do not match between component and entity for port "result".

It's of course, correct and I can of course add the necessary type conversions to get rid of it. But it's alot of pointless code and I'd prefer to just suppress the error. I'm guessing suppressing fatal errors is not supported (I tried "-suppress 3807") but since I use this alot if would be helpful.

↧

Start to make Uboot.img H/W: DE0-nano-Soc (Atlas-soc,Dev-Platform, Cyclone 5)

August 31, 2017, 11:20 pm

≫ Next: Getting Error with DE0-nano-soc [making u-boot.img]

≪ Previous: How to suppress Fatal Modelsim error vsim-3807

HW :

https://rocketboards.org/foswiki/view/Documentation/EmbeddedLinuxBeginnerSGuide

Is Anyone who pass that "5. Configure and Compile U-BOOT" Chapter?

i got Some Errors.,

I Tried Process..1. Download atlas_linux_ghrd.tar.gz (URL : https://rocketboards.org/foswiki/pub/Documentation/EmbeddedLinuxBeginnerSGuide/atlas_linux_ghrd.tar.gz?t=1480987165)2. execute "Embedded_Command_Shell.bat" => C:\Altera\15.0\embedded\Embedded_Command_Shell.bat 3. locate my atlas_linux_ghrd.tar.gz folder => cygdrive/c/atlas_linux_ghrd.tar.gz
4. Extract "atlas_linux_ghrd.tar.gz"$ tar xzvf atlas_linux_ghrd.tar.gz5. using bsp editor $ bsp-editor &6. preloader settings directory => atlas_linux_ghrd/hps_isw_handoff/soc_system_hps_0 7. Enables FAT_Support (Radio Button) then Generate => EXIT8. Software/spl_bsp9. make10. $ wget gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux.tar.xz => Download Below Link.https://rocketboards.org/foswiki/pub...t=150424487911. Extract tar -xvf gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux.tar.xz
12. Set Enviormental Settings$ export CROSS_COMPILE=$PWD/gcc-linaro-arm-linux-gnueabihf-4.9-2014.09_linux/bin/arm-linux-gnueabihf-13. $ git clone https://github.com/altera-opensource/u-boot-socfpga.git14.$ cd u-boot-socfpga15. $ git checkout rel_socfpga_v2013.01.01_15.09.01_pr16.make mrproper 17.$ make socfpga_cyclone5_config18.$ make19. probly Can find "u-boot.img" at "u-boot-socfpga" Folder But i cannot find it ..@ number 16, after Typed "make mrproper" .. then said some errors.. how to do.. $ make mrproper process_begin: CreateProcess(NULL, /cygdrive/c/sw/atlas_linux_ghrd/software/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -print-file-name=include, ...) failed.
/usr/bin/sh: /cygdrive/c/sw/atlas_linux_ghrd/software/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc: cannot execute binary file
dirname: missing operand
Try 'dirname --help' for more information.
process_begin: CreateProcess(NULL, /cygdrive/c/sw/atlas_linux_ghrd/software/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -print-file-name=include, ...) failed.
/usr/bin/sh: /cygdrive/c/sw/atlas_linux_ghrd/software/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc: cannot execute binary file
dirname: missing operand
Try 'dirname --help' for more information.
process_begin: CreateProcess(NULL, /cygdrive/c/sw/atlas_linux_ghrd/software/gcc-linaro-5.3-2016.02-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-gcc -print-file-name=include, ...) failed.
rm: cannot remove `SPL': Is a directory
make: *** [clobber] Error 1
thanks to watch loooooong questions../.Please Give any helping talk... Thanks.

↧

Getting Error with DE0-nano-soc [making u-boot.img]

August 31, 2017, 11:24 pm

≫ Next: OpenCL guidelines to use physical pins of fpga

≪ Previous: Start to make Uboot.img H/W: DE0-nano-Soc (Atlas-soc,Dev-Platform, Cyclone 5)

↧

OpenCL guidelines to use physical pins of fpga

September 1, 2017, 2:01 am

≫ Next: Sata/sas

≪ Previous: Getting Error with DE0-nano-soc [making u-boot.img]

Cheers,

I am beginner with OpenCL SDK for cyclone V, I have experience building projects in Cyclone IV using NIOS soft core and fpga IP modules.

Now I am trying to use OpenCL in Cyclone V SOC-FPGA which has a hard processor inside. I finished successfully the first getting starter guide for OpenCL in cyclone V. I could run and edit the HelloWorld example.

However I have some questions:
1) The hello world example is compiled using aoc.exe and c5soc board profile installed by SDK OpenCL, when I perform a partial compilation (w/o build the hardware) I get a .aoco file and a folder called bin with quartus project. It is possible to edit the quartus project and then use this for make a complete compilation using .aoco file and quartus project edited? Currently, I edit the quartus project but I did this modifying the template in ALTERAOCLSDKROOT/board/c5soc-folder. I am thinking that it is not the best approach.

2) I would like to code in OpenCL using IO ports access (physical pins) of FPGA though OpenCL API functions available, but I was readying "Intel® FPGA SDK for OpenCL Custom Platform Toolkit User Guide" and this indicate me that I just able to use the interface defined in Board_spec.xml. So the question is: it is possible to add more interface as simple input output pins in fpga? If the answer is Yes, which reference guide I need to read to perform this?

I will be deeply thankful for any advising.

↧

Sata/sas

September 1, 2017, 4:52 am

≫ Next: Redirect kernel output into other port than pci with OpenCL.

≪ Previous: OpenCL guidelines to use physical pins of fpga

Hi all.
My question is about the interface of SATA/SAS. I use megafunction Stratix V Transceiver Native PHY.

I understand that the bus tx_parallel_data[63..0] is used as data bus and the utility bus signals. But unfortunately, I can't understand how divided the address space on the external drive.

For example: I want to record 32-bit word at some address 0x10. What should I record in this case, on the bus tx_parallel_data[63..0]?:confused:

Can anyone explain the principle of exchange of information with the external drive? Or give an example? I was looking at the V-Series Transceiver PHY IP Core User Guide, but the answer to my question is not found (https://www.altera.com/en_US/pdfs/li...user_guide.pdf).

Thank you in advance.

Regards, Andrey.

↧

Redirect kernel output into other port than pci with OpenCL.

September 1, 2017, 5:21 am

≫ Next: New to FPGA programming - Please Help

≪ Previous: Sata/sas

Hi I am trying to redirect kernel output into other port than pcie. I am thinking about ethernet port to send the data. Does anybody have an idea how can get access to the specific port on the board?

Thanks!

↧

New to FPGA programming - Please Help

September 1, 2017, 6:10 am

≫ Next: Muxing and demuxing multiple SDI over serial link

≪ Previous: Redirect kernel output into other port than pci with OpenCL.

Hello all,

I am new to both this forum and FPGA with OpenCL - I have some questions I hope someone can help me with.

I have intelFPGA_pro v 16.1 installed in Ubuntu Linux OS and am just trying to test out the system by running the 'aocl diagnose' operation. However, when I run it I get the following output:
"cannot find board_env.xml in /board/nalla_pcie"

I checked in /hdl/board/nalla_pcie and 'board_env.xml' is located in this directory. Can anyone tell me what is wrong? I am looking forward to getting some interesting work done :)

Thank you in advance for any help/hints.

↧

Muxing and demuxing multiple SDI over serial link

September 1, 2017, 7:08 am

≫ Next: MAX 10 - debugging NIOS II

≪ Previous: New to FPGA programming - Please Help

Hi,
we would like to implement a mux for 3 HD-SDI streams over a single serial link, at the other side the streams will be demuxed and transmitted (without buffering).
I would like to have some suggestions
Is there some reference design i could check?

↧

MAX 10 - debugging NIOS II

September 1, 2017, 8:44 am

≫ Next: Can get USB Blaster II to work on Arria 10 GX dev kit

≪ Previous: Muxing and demuxing multiple SDI over serial link

All,

We're moving from CIII parts to MAX 10; both with NIOS designs inside. Whereas the CIII design has external SRAM which is used to debug the NIOS code, the MAX10 uses OCRAM to hold the program. The MAX10 is configured with the POF file (Quartus 17.0 lite) which contains both the SOF and HEX files, and runs fine (software bit bangs to a pin which is observed on a scope). The issue is I can't attach the debugger to the MAX10 - when I do I get an error on the verify of the download.

We're using AN730 Option 3 - Code in on chip Ram. But nowhere in AN730 or other searches have I found instructions on how to debug a NIOS design inside of a MAX10.

TIA.

↧

Can get USB Blaster II to work on Arria 10 GX dev kit

September 1, 2017, 1:49 pm

≫ Next: Hello_world doesn't work for Arria 10 ubuntu 14.04

≪ Previous: MAX 10 - debugging NIOS II

Hello everyone

I am trying to set up a new Arria10 GX Dev Kit board that we recently acquired in our research lab. First thing I tried to do after installing Quartus and the board package was using the Board Test System to test the different components. For some reason, even though I followed all the instructions in setting up the USB Blaster II drivers, the BTS is complaining that it doesn't detect my board. I am using CentOS 7 and Quartus 17.0. I also realized that when I go to the "Programmer" window in Quartus (under the Tools menu), I donot get the option to add a "USBBlaster" hardware type, it only gives me "EthernetBlaster" as an option for Hardware type in the "Add Hardware" window. I apologies if any of this seems trivial or straight forward, this is my first time setting up an Altera dev kit and I am not very experienced with Altera tools in general. I would appreciate any ideas.

Update: Alright, I think I am now able to detect the device using USB Blaster; it turned out that I hadn't run the jtagd service. Now, however, when I try to configure the FPGA using the Board Test System (i.e. factory restore, or one of the test configurations) I get the following warning message: "Failed to get this device. Please make sure system console is closed. Close this GUI and check the board connection.". Any ideas?

↧

Hello_world doesn't work for Arria 10 ubuntu 14.04

September 1, 2017, 2:02 pm

≫ Next: Arria DSP block merge with fixed point in OpenCL

≪ Previous: Can get USB Blaster II to work on Arria 10 GX dev kit

1. quartus 17.0, ubuntu 14.04, opencl
2. Arria10 is used.
3. all diagnose pass.

command:
aoc device/hello_world.cl -o bin/hello_world.aocx --board a10gx

Error message in hello_world.log
System name: hello_world
java: /build/swbuild/SJ/nightly/17.0.2/297/l64/p4/quartus/ccl/ver/ver_jni_stub.cpp:122: jboolean Java_com_altera_version_AlteraProductInfo_initiali ze(JNIEnv*, jobject): Assertion `success' failed.
Aborted (core dumped)

↧

Arria DSP block merge with fixed point in OpenCL

September 1, 2017, 6:54 pm

≫ Next: Altera's LPDDR3/4 Supported Reference Board

≪ Previous: Hello_world doesn't work for Arria 10 ubuntu 14.04

Hello,

I have been trying to implement fixed point algorithms using opencl for an arria10. I am interested in this approach because I run out of DSP blocks when I used floating point so I figured I would use the 2 independent 18x18 multipliers that are in the DSP block with fixed point. I followed the tips in the programming guide and have verified in the compile reports that I am indeed using a single multiplier in the each of the DSP blocks. However it doesn't appear that the compiler is making use of the 2nd 18x18 multiplier.

I found the following and wondered if it would work so I gave it a try. It's older but I was hoping it would work
https://www.altera.com/support/suppo...92013_756.html

When I hit 100% DSP utilization, logic starts to take over the additional operations. So it appears I am only using half of the 18x18 multipliers and no block merging is taking place. I am waiting on a compile to verify this. Is there any way to leverage all of the fixed point multipliers or am I doing something wrong?

Thanks,
Rudy

↧

Altera's LPDDR3/4 Supported Reference Board

August 31, 2017, 12:35 am

≫ Next: DE1-SOC power button non-functioning in AS/EPCS mode

≪ Previous: Arria DSP block merge with fixed point in OpenCL

Hi,

I need a board with LPDDR3 or LPDDR4 to validate my IP. Do Altera have such board which contains LPDDR3/4?

Thanks & Regards,
Vijay

↧