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reserve SDRAM memory - u-boot "Bad Linux ARM zImage magic!"

August 26, 2017, 3:14 pm
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Hi,
I´m a VHDL guy, not a Linux one, but I want to try out the use of sgmdma Altera IP component, to write directly in HPS SDRAM of Altera Cyclone V Dev Kit.
By now, I´m using the GHRD 16.1, and as I could see by searching some examples and discussions, I would like to reserve memory from kernel, to avoid conflicts with Linux. I think that this approach would very good to solve my project.
So, I have just downloaded and get working the GSRD 16.1 at my kit, then I have tried to reserve memory by u-boot script just like indicated in this reference:
https://www.altera.com/support/suppo...32014_165.html

So, just to clarify: by now what I want is just to test the memory reservation. The problem I have encountered is that with this command:
setenv bootargs console=ttyS0,115200 mem=512M

I get no error, but just after typing this one:
setenv mmcboot setenv bootargs console=ttyS0,115200 mem=512M root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdtaddr}

I get a "Bad Linux ARM zImage magic!" As you can see below:

SOCFPGA_CYCLONE5 # setenv mmcboot setenv bootargs console=ttyS0,115200 mem=512M root=${mmcroot} rw rootwait;bootz ${loadaddr} - ${fdtaddr}
Bad Linux ARM zImage magic!
SOCFPGA_CYCLONE5 #

And after that with a boot command I just can´t boot Linux.

Could you please help with this issue? Am I doing something stupid or like that? By changing the boot.script and compiling it that error is the same...

Thank you in advance,
Lucas
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What do you think most popular usage of FPGA?

August 27, 2017, 8:00 am
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My question is simple as title.

What do you think most popular usage of FPGA?

In my opinion, using FPGA for prototyping ASIC is most popular. Since manufacturing ASIC is quite large scale industry, which implies lots of investment must be taken.

what are your thoughts??

thank you !
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aoc: unable to generate hardware

August 27, 2017, 11:51 pm
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Hello,
I use de5a_net_i2 board, and I need to modify the bsp to change the PCIE interface lane to x4.

On linux 64bit OS, after I set ACL_QSH_COMPILE_CMD="quartus_sh --flow compile top -c base", I run the bash shell line "aoc vector_add.cl -v --no-interleaving default".

Then the compile stopped because of error
aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware.

The quartus_sh_compile.log file lists the following:
Error(18633):The archive "base.qdb" contains a full design and cannot be imported via the import block command nor as a source file in the QSF.

Can anyone help me?
Thank you!
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Problem quartus_cpf: command not found

August 27, 2017, 11:56 pm
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Hello,

I'm a beginner user in SoC. I use quartus 16.0 and SoC EDS 16.0 on Ubuntu 14.04.

I’m trying to convert the .sof file to the .rbf file. I use SoC EDS Command Shell on Ubuntu OS(14.04)
When I introduce the below command:
quartus_cpf -c -o bitstream_compression=on soc_system_top.sof soc_system.rbf
The shell returns me this message:
quartus_cpf: command not found

How can I do to solve this problem?

Thanks for your help!
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USB Blaster driver was installed, but Altera Programmer Hardware Setup can't find it.

August 28, 2017, 2:00 am
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Dear all

I re-install my PC with new HD, because the old HD is broken.
The USB blaster is work normally before I re-install, and it's work normally when plug in other PC.

The system is win 7
I re-install the QuartusII 10.0, 11.1 sp2, and 16.0.
I install USB Blaster driver, and I can find it in windows 7 Device Manager, but the strange thing is, USB Blaster CAN NOT be find in Altera Hardware setup of Porgrammer~~~~
anyone can help me ???

I try to re-install USB Blaster driver "N" times, still can't be find by Altera hardware setup.

Please anyone can help me???

Thanks a lot !!!

Lillian Chen
Attached Images
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mSGDMA & NicheStack

August 28, 2017, 10:02 am
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Hi,

with Quartus Prime Altera has added the mSGDMA IP core to Qsys (in Pro version it is the only DMA core available). However there has long been an mSGDMA IP on alterawiki and I am not sure to what extent the two resemble. This name conflict makes information search on internet even more complicated...

My system starts the NicheStack, intializes succesfully (at least reported as succesful to STDOUT) but the RX_SGMDA never seems to accept data from the MAC (I can see with SignalTap that MAC backpressure is ON, PCS received correct frame data in buffers but no transfer to main memory is completed). My guts tell me it has to do with the descriptors. I assume it can be either:
- wrong QSYS wiring (there is no reference design using this new core - only a few designs using the sub-core units) - but this is unlikely, the wiring seems intuitive
- wrong software configuration (MAC profile wrong?)
- NicheStack bug (support added recently with Q17.0)

What I do:
Qsys (see attachment)
- no external descriptor memory instantiated
- connected the AvlMM master (mm_write) to main memory
- all AvlMM slaves (descriptor slave, response, csr) --> cpu.data_master

BSP
- compilation with
Code:
set_setting hal.make.bsp_cflags_defined_symbols "-DTSE_MY_SYSTEM"
- tse_my_system.c declaring
Code:
alt_tse_system_info tse_mac_device[MAXNETS] = {
    TSE_SYSTEM_INT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, TX_MSGDMA, RX_MSGDMA, TSE_PHY_AUTO_ADDRESS, 0)
};
Has anyone experience with this IP? Can anyone give a hint what I do wrong?

Thank you!
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System doesn't keep programming

August 28, 2017, 9:12 pm
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I'm very new to using FPGA's and I'm having a small issue using the the Max10 Eval Board. I'm able to create a system and program the board fine but every time the board looses power (I unplug it and plug it back in) the programming seams to be lost.

Is there something I need to do that I don't know about. I followed each lab (NIOS II hello world, MyFirstFPGA counter) and they work great but the program does not stick after a reset event.

I've looked all over for something I may be missing but can't find anything.

I would be very grateful for any help or suggestions.

Thanks

Joe.
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num_compute_units effect on concurrent workgroups

August 28, 2017, 11:36 am
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Hello all,

I have a kernel that uses barriers, and I have been running into a problem during compilation where the compiler throws the warning

Code:
Compiler Warning: Kernel 'sync': limiting to 2 concurrent work-groups because threads might reach barrier out-of-order.
The affected area is like this:

Code:
while(tid < vert_count)
{
      status[tid] = tid;
      tid += total_threads;
}

barrier(CLK_GLOBAL_MEM_FENCE);
I suspect this has something to do with indeterminate loop bounds, but I could be wrong and am looking for some suggestions. To circumvent the error I also tried to increase the number of compute units using the num_compute_units() attribute, but that did not change the outcome. Does anyone have any insight as to why that might be? Or more broadly, how the num_compute_units() attribute affects workgroup scheduling and concurrency?
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8B/10B ,64B/66B encoder/decoder of IP setting on Arria 10 transceiver

August 28, 2017, 7:53 pm
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Device : Arria 10 10AX66N3F40E2SG
EDA : Quartus Prime Std. 17.0
Problem :
I want to trans/receive data via Arria10 transceiver which data width is 64bits and clock rate is 127MHz.
Protocol of Transceiver just used 64B/66B
So the data rate is 127MHz*66bits = 8382Mbps(64/66B)
If I want to use 8b/10b which data width is 8bits and clock rate is 127MHz,data rate is 127MHz*10bits = 1270Mbps(8/10B).

I already succeed in Stratix IV Transceiver which using native 8B/10B encoder/decoder. (156.25MHz,16bits).

But in the Arria10-Native-Tansceiver,I select 64B/66B en/decoder(or 8B/10B en/decoder),
(preset : low latency enhanced PCS)
http://imgur.com/ADK6n3o
Qsys jump to error ,
http://imgur.com/G6qb6Zq
If I want to use 8B/10B , It disappear same error message too.
(preset : low latency standard PCS)
http://imgur.com/YqwSXbU
I tried for a few weeks , cannot solve this problem.
I don’t know which parameter in transceiver I ignored.
Can anyone help me please?
Thanks.

Attachments include docx file of my IP core setting in Arria 10(64B/66B failed) and Stratix IV (8B/10B succeed)
Attached Files
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OpenCL version qusetion

August 28, 2017, 11:03 pm
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I am a beginner of OpenCL and I bought the DE10-standard board. In the DE10-standard manual from terasc, the OS version they recommanding is CentOS 7.0

But when I install the OS and Quartus Program, the Quartus are not working... (quartus version is 16.1) So I have two question.

1, Is it Ok to use the CentOS 7.0 and Quartus 16.1?

2. If I change the version, I will change the CentOS version. Which version is best?
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Disable FPU on Arria10 SoC FPGA

August 29, 2017, 12:17 am
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Hi Support,

We need to disable FPU on Arria 10 SoC FPGA.

Please let us know the procedure how to disable FPU.



Regards,
Karthik.
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Question about Tramp of Vccaux in using EP4SE230F29I4N.

August 29, 2017, 1:17 am
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We meet some problems as the following when we use the device of EP4SE230F29I4N in Stratix IV series.
FPGA works normally after welding. However,after about half a year, fpga cannot be loaded at the temperature of -40℃ while it is normal at the normal temperature.
The failures are: nCONFIG is in constantly-high level, nStatus and CONFIG_DONE are in constantly-low level, both power supply voltage and time sequence are normal. Delaying the Tramp time of Vccaux which is about 4us when in failure can make fpga work in normal. The Tramp time when in normal temperature is the same with the time when in low temperrature. The following is our application:

1.Would you answer us the reason of the above failure and how to solve it?
2.As for time, why does fpga work normally just after welding in normal and low temperature while it trun to failure in low temperature after using ofr a period of time?
3.As for temperature, why can fpga be loaded in the normal temperature when Tramp time is 4us while cannot be loaded normally at the temperature of -40℃?
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Qsys Error: Failed to elaborate classic module C:/Users/.../yysystem.ptf

August 29, 2017, 6:58 am
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Hello,
i didn't touch my project for a while.
Now i get the error:
Error: Failed to elaborate classic module C:/Users/.../AppData/Local/Temp/alt7407_3755802541581721576.dir/0007_sopclgen/yysystem.ptf (254)

In other topics they told to close qsys, quartus and reboot the system but that all didn't help.

I only changed some c and h files on my NIOSII code (nothing related to the qsys)
Is maybe the quartus installation corrupt? If maybe yes, how to reinstall it preferably (install over the old, remove reinstall)?

Quartus II 64Bit 12.1 SP1 installed

Below the last messages of th Generate log before the error occurs:

Code:
Info: Starting classic module elaboration.
      1 [main] sh (6408) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
      0 [main] sh 5140 fork: child -1 - forked process 6408 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      2 [main] sh (6756) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
1090043 [main] sh 5140 fork: child -1 - forked process 6756 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      1 [main] sh (1376) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
3170757 [main] sh 5140 fork: child -1 - forked process 1376 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      2 [main] sh (3976) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
7258297 [main] sh 5140 fork: child -1 - forked process 3976 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      3 [main] sh (776) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
15338349 [main] sh 5140 fork: child -1 - forked process 776 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: Resource temporarily unavailable
Error: Failed to elaborate classic module C:/Users/ith/AppData/Local/Temp/alt7407_3755802541581721576.dir/0022_sopclgen/yysystem.ptf (254)
Info: Finished elaborating classic module.
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altera_onchip_flash Modelsim simulation error

August 29, 2017, 8:05 am
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Hi,

I'm trying to simulate the altera_onchip_flash for the MAX10 (10M25DA) FPGA by using the Altera-Modelsim. I cannot simulate the module because I get this eror:

ERROR: ./e_OnChipFlash/synthesis/submodules/altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.

Is there any way to solve this problem ?

Thanks in advance

Daniel
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Programming Issue with Active Serial Programming

August 29, 2017, 9:16 am
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We are trying to program a EP1C12Q240C8N device using Quartus II 6.0 Web on a Windows 7 PC with the Byte Blaster II programmer. Getting a cannot recognize silicon device ID error. The programming operation works fine on another device on the board using JTAG. We have tried a sample board that was previously programmed and also get the same error. My first inclination is to order another programmer, although I'm not sure why it would work with JTAG in one case and not with ASP in another. However, before I order another programmer, should I upgrade to more recent hardware? From what I can ascertain, 11.0 would be the latest version that supports this device, unless I'm misinterpreting something. Should I also use a USB connected device rather than a parallel port programmer?

Thanks!
Blair
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USB Blaster not recognized in Windows 7

August 29, 2017, 12:00 pm
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I downloaded Version 17, standard edition (17.0.0 Build 595). I had been using version 16. I used both simultaneously, but later uninstalled Version 16. Before I uninstalled V16 I was using USB Blaster.
Now, when I run either signal tap or programmer, I am not given USB Blaster as an option, only Masterblaster (which I do not have).
Since I may have uninstalled the driver when I uninstalled V16, I followed the instructions for installing the drivers in Windows 7.
When I look at device drivers I "Altera USB Blaster" listed under Universal Serial Bus Controllers. I do not see it listed under Ports (COM and LTP), even when it is plugged in.
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Generating a simulation test bench and the automated script for Triple-Speed Ethernet

August 29, 2017, 3:19 pm
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Generating a simulation test bench and the automated script
In “Triple-Speed Ethernet MegaCore Function User Guide” (Ethernet Altera IP Core MAC) ug_ethernet.pdf
On page 21 paragraph 2-2
Generating a Design Example or Simulation Model
It is mentioned


“In the parameter editor, click Example Design to create a functional simulation model (design example that includes a test bench). The test bench and the automated script are located in the
<variation name>_testbench directory."


But I didn’t find any option like it, how to reach this option?
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Qsys - Generic QUAD SPI controller II support flash device

August 30, 2017, 12:54 am
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Hello, all.

I am using Quartus Prime 17.0.
I consider using Altera Generic QUAD SPI controller II using Qsys, and using QSPI Flash.
QSPI Flash which that I am in trouble can procure is not included in the choice.
All of Micron N25Qxxx contained in the present choice are Obsolute.
Moreover, Micron MT25QL512ABB is in a situation with difficult procurement.
Then, what should I do using Cypress S25FL512S/S70FL01GS by Altera Generic QUAD SPI controller II?

Reguads,
hide-u.
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Obtaining CL_INVALID_KERNEL error when setting cl_float4 as a kernel argument

August 30, 2017, 5:13 am
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Hello,

I have got a question about the function 'clSetKernelArg()' and the error code 'CL_INVALID_KERNEL'.

My problem:
My kernel function takes nine parameters.
When I try to set the kernel arguments via the function 'clSetKernelArg()' everything works fine until I want to set a cl_float4. I then get a 'CL_INVALID_KERNEL' error.

Is cl_float4 not supported by FPGA?
When I run the same code on CPU or GPU everything works fine.

Any hints will be apprecciated.

Tobias
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Altera TSE Test Benches

August 30, 2017, 5:32 pm
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Hello all, I was looking at the pdf provided by altera (AN 585: Simulation Debugging UsingTriple Speed Ethernet Testbench) and was looking to use their provided testbench. It asks that i download AN585_test_case.zip from Literature:Application notes link but it is not there. Any ideas?

If it is gone, does anyone have a good sample testbench that I could use to test the TSE? thank you!
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