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"External connection" conduit on DDR2 controller (with ALTMEMPHY)

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I am working on a Cyclone IV design, and need a DDR2 controller.

Using Qsys, I have added the IP block DDR2 SDRAM CONTROLLER with ALTMEMPHY

One of the interfaces on this IP is labeled "external_connection" and contains three signals, all outputs: local_init_done, local_refresh_ack, reset_phy_clk_n

I get a Qsys warning that this must be exported or connected to a matching conduit.

My problem is that I don't know what I am supposed to do with these signals.

the link to online documentation for the IP doesn't work, I get the "404" error at the Altera website. I have tried looking in the "Embedded Peripherals IP User Guide" under "SDRAM Controller core" but there is no mention of these signals that I can find.

Can anyone help me?

Rod

how to initialize f2h_sdram from system console

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I searched the forum, I consulted google, but was unable to find any relevant information. Hoping someone can point me in the right direction.

I am using a cyclone 5 (it is actually the MitySoM module from Critical Link, an Altera partner). I want to write data from the FPGA to the DDR mempry over the f2h_sdram bridge. More specifically, I am from trying to using the frame buffer from Altera's VIP in a video application.

In trying to bring this system up, i want to be able to use system console so it's not software dependent. I want to use trace system + system console to verify before bringing software into it.

I know that the HPS peripherals , and the bridge specifically, needs to be initialized. I know the u-boot bootloader normally does this. How can I initialize the bridge if I'm just using just system console?

Thanks for any help

Qsys without nios II

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please let me know that, can i implement an algorithm in Qsys without using Nios processor. means using only programmable logic[i.e. fpga area] while excluding the soft-core. Or should i go with quartus II and megafunctions ?
thanks in adavance

Arria 10 core PLL error 15744

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I'm getting the following error when instantiating a generated Arria 10 core PLL (fpll_inst):


Code:

  Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( prot_mode == UNUSED ) OR ( pllcout_enable == PLLCOUT_DISABLE ) OR ( m_cnt_in_src == M_CNT_IN_SRC_CSCD_CLK ) OR {((vco_freq_hz-7'h64)<=(cnt_div*f_out_c2))}
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): prot_mode = BASIC_TX
    Error (15744): f_out_c2 = 12135922
    Error (15744): vco_freq_hz = 5000000000
    Error (15744): pll_c2_pllcout_enable = PLLCOUT_ENABLE
    Error (15744): pll_c_counter_2 = 412
    Error (15744): pll_c_counter_2_in_src = M_CNT_IN_SRC_PH_MUX_CLK

Looking into the qsys file I see that


Code:

<parameter name="gui_hssi_prot_mode" value="0" />
But in the xml file generated from the qsys file I observe:


Code:

<parameter name="prot_mode" value="basic_tx" />
How can I control this parameter, or the others to satisfy the requirements?

Cyclone 10 GX PCIe dev kit?

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Are there any Cyclone 10 GX PCIe dev kits available or will any such dev kits be available soon?

The BSP Editor unable to edit or create the HPS BSP

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Hi, All:

I create a QSys system for my Cyclone V SoC chip, and according to the manual, I need to create the BSP for the chips then I can run my QSys system correctly.
According to the manual, I open the Embedded Command Shell.bat in Administrator, and enter

Code:

bsp-editor &
to open the BSP Editor.
But in the BSP Editor, I see the menu File -> New HPS BSP... is gray, I can not click on it.

I try to open a example bsp file in the CD of my development board, the BSP Editor reported several errors, and can not open them.
The errors like:

Code:

Available BSP type values for the --type argument are:[hal, ucosii]
BSP type "spl" unknown
NullPointerException

I see that is a error due to the BSP Editor can not find the HPS BSP Informations.
I try to reinstall the software, even install in my virtual machine, but all of them are got same erros.
What's wrong with my approach?
Thank you very much.
Dmitri Abramovic

DE0-nano-SoC - Is it possible to reconfigure it at run-time?

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Hi all,

as the title says, I would like to know that before buying.

Thanks!

Implementing the ADC Controller with MegaWizard (DE0-Nano board) problems

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Hello,

I am using the ADC IP controller as a .bdf file in a hardware-based environment. I ve connected all pins with the used interface in order to interact with the ADC128S002 Analog-to-Digital Converter (thanks to the good documentation).
But here s one issue I am facing with that documentation (ftp://ftp.altera.com/up/pub/Altera_M...0-Nano_ADC.pdf).
On chapter 3.3 it clearly emphasizes that the ip core is going to update itsself regulary. Here is the quote: "The MegaWizard version of the controller allows access to between two and eight channels, with channel values updating automatically." But thats not the case when I want to check a 1.5 V battery or several power banks from different microcontrollers using signaltap and watching at each channel data could get captured. I ve checked pin assigments in quartus as well as gpio header connection but no data can be caugth. Since the ADC is using the SPI protocol I can watch its dynamic behaviour on signaltap. It looks fine, but data isnt pushed into any channel. Has anybody some approach to solve that problem?

emif avalon handshake signals are unstable.

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I am implementing a DDR4 memory interface using the emif controller.
The emif code is generated by QSYS, using Arria 10/10AX115N3F45E2SG on a NALLATECH 510T board.
The design is basically working, the calibration success signal goes high, I never seen calibration fail on this board. Clock is running at 266MHz.
Most memory access cycles are fine but sometimes I receive a wrong data value, the previous access cycle value.

The problem is with the avs_waitrequest_n and avs_readdatavalid signals.
All documentation shows nice clean signals, each cycle gets a nice avs_waitrequest_n pulse and avs_readdatavalid as required.
When I capture these signals using Signaltap I dont see that.
The avs_waitrequest_n signal pulses low twice in most cycles, sometimes it remains low for extended 30+ clock cycles.
The avs_readdatavalid also pulses high multiple times for when performing a read of burstlenght 1.
The attached image shows an example in which there are 4 read cycles.

The first two cycles starting at t-825 and t-750 are completed and return the correct data.
But the avs_waitrequest_n pulses low twice for each cycle and the avs_readdatavalid pulses high 5-10 times.

The third cycle at t-550 shows the avs_waitrequest_n pulse low once followed by an extended low period which bleeds into the next cycle.
This fourth cycle then fails be returning the data from the third cycle.

The traces of the avs_waitrequest_n and avs_readdatavalid signals are registered versions of the signals, I didnt want to connect a probe directly.

How come avs_waitrequest_n and avs_readdatavalid toggle like this?


FPGA : Arria 10/10AX115N3F45E2SG
Board : NALLATECH 510T
DDR : DDR 4
Quartus : 16.0.2
Attached Images

DE1-SoC - Cyclone V HPS fallback boot from FPGA

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We are currently using DE1-SoC boards at a university in our teaching modules - one module dealing with the FPGA side and the other is dealing with bare-metal programming on the HPS.

During the last couple of years that we have run the bare-metal ARM HPS module, we have been relying on a bit of a dirty hack of using debugging scripts to force load a uboot-spl (preloader) and a bare metal program into memory using the debugger within DS-5. This has allowed us to get the students running code and debugging it, albeit somewhat messily. The main issue is whenever the chip resets (one of the things we show is using the watchdog timer for example) it clears away the program and preloader and so it doesn't boot back up - the debugger has to be disconnected and re-launched to get the software back in to place.

There are ways around this, such as placing the application and preloader onto an SD card and booting from that, however this is not an approach which will work for us logistically - it would require buying 100+ SD card readers and microSD cards (which will inevitably get lost or misplaced), and that's not to mention the IT headache of getting the readers and software set up to write to them. Alternatively we could put a preloader on a microSD card that is left permanently in the boards, and have that boot the bare metal application from QSPI flash memory which can be programmed, albeit slowly, using JTAG. However I don't like these approaches.

What I have come to try and do is get booting from the FPGA side set up. We have build our own customised version of the DE1-SoC Computer (actually it was built from scratch with much of the flaky university program IP replaced with stuff that works properly, but anyway, I digress), so adding 64k on-chip RAM at the base address of the HPS to FPGA bridge is not an issue. After much fiddling around over the last few days trying to setup a BSP and compiler the uboot spl over the last couple of days, I finally managed to get the HPS to boot my preloader in the FPGA. I still need to modify the preloader to jump to RAM containing the bare metal application uploaded through DS-5, but that should be fairly trivial (I hope!).

The biggest issue with all of this is the fact that Terasic in their infinite wisdom cheaped out and didn't solder on a DIP switch for controlling CSEL and BSEL to the board - there is a footprint, but rather than soldering a 20p switch they instead hardwired CSEL to 0x0 and BSEL to 0x5 using resistors. This means that the boards as is without modification are permanently set to boot from an SD card. In order to get the board to boot from FPGA I had to do some soldering on one of the DE1-SoC boards to change BSEL to 0x1. I have no desire to do this to 100+ DE1-SoC boards.

Having looked further at the documentation, I see that it should be possible to have the BootROM failback to loading a preloader in the FPGA if it fails to find a valid image in the location that BSEL specifies. My hope was that I could leave BSEL as 0x5 (SD Card), and simply not install an SD card. This would of course mean there is no valid image, and so if set up correctly should failback to booting the preloader in my FPGA image. However, this doesn't seem to work.

I've correctly got the preloader set up in the image, and have adjusted the FPGA design to ensure that the f2h_boot_from_fpga_on_failure signal is tied to 1 (so it should boot from FPGA on failure). Despite this when I try with a board that I haven't changed BSEL on (still 0x5), the board doesn't boot the preloader. Connecting with the debugger I see that the HPS is sat in an infinite loop at ~0x0274 if I recall correctly (I can double check) which isn't in the FPGA, it's probably the BootROM code but without delving deep into the disassembly it's not immediately obvious where it is stuck.

Has anybody been successful with failback boot from FPGA?

Alternatively are there any suggestions as to what might be going wrong here?

I wonder if it is possible that because there is no uSD card present it simply crashes trying to initialise a card that isn't there. I am awaiting a uSD card - once I get it I will try to see if just installing a blank SD card is enough to get it to failback. In the meantime I figured I'd post a query.

Parser for (Altera) FPGA programming files

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I've created a small parsing utility that shows the contents of some Altera (+ others??) .SOF/.POF/.RBF/.JIC/.RPD files.

It's a very rudimentary experimental tool but it can show some of the contents of theses files (CRCs, checksums, flags, etc...)

Sometimes it can help people understand why their files fail programming, etc.

There's little information available on this (proprietary) topic so if you have anything to add or correct, or find a file that doesn't process, please leave a msg.


(I've tested it against 100s of examples but the combinations are endless so it will break sooner or later...)
Attached Files

An issue about compiling the OpenCL to FPGA

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Hi,

I met an issue about compiling the OpenCL HelloWorld/Vector_add code to FPGA.

Quartus Prime can offload the VHDL code into the FPGA board but the OpenCL SDK and compiler can not program to the FPGA board instead.

[root@localhost vector_add]# aoc -v device/vector_add.cl -o bin/vector_add.aocx --board de5a_net_i2 --report
aoc: Environment checks are completed successfully.
You are now compiling the full flow!!
aoc: Selected target board de5a_net_i2
aoc: Running OpenCL parser....
/root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/tests/vector_add/device/vector_add.cl:23:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
__kernel void vector_add(__global const float *x,
^
/root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/tests/vector_add/device/vector_add.cl:24:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
__global const float *y,
^
2 warnings generated.
aoc: OpenCL parser completed successfully.
aoc: Compiling....
aoc: Linking with IP library ...
Checking if memory usage is larger than 100%


+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 19% ;
; ALUTs ; 10% ;
; Dedicated logic registers ; 10% ;
; Memory blocks ; 11% ;
; DSP blocks ; 5% ;
+----------------------------------------+---------------------------;
aoc: First stage compilation completed successfully.
Error: Compiler Error, not able to generate hardware



I set up all required driver/BSP (board supported package from Terasic)/env variables/libraries and followed the official manual carefully but still have this issue.

[root@localhost vector_add]# aoc --list-boards
Board list:
de5a_net_i2

But whlie running the aocl diagnose:


[root@localhost vector_add]# aocl diagnose
aocl diagnose: Running diagnose from /root/intelFPGA_pro/17.0/hld/board/de5a_net_i2/linux64/libexec
aocl diagnose: failed 32 times. First error below:
Vendor: Terasic


Found no active device installed on the host machine.


Please make sure to:
1. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to the correct board package.
2. Install the driver from the selected board package.
3. Properly install the device in the host machine.
4. Configure the device with a supported OpenCL design.
5. Reboot the machine if the PCI Express link failed.

Configuration:
FPGA board: Terasic De5a-Net FPGA with Arria 10
Quartus Prime Pro Edition with OpenCL SDK

All the manuals and drivers can be found here:
https://www.terasic.com.tw/cgi-bin/p...o=970&PartNo=4



A similar question in the forum but still didn't have solutions yet:
https://alteraforum.com/forum/archiv...p/t-45872.html

I am looking for any helps/advise! Thank you so much!

All the best,
Jiawen

OpenCL channels connections to the kernel IO MIA.

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Hi,

I am adding read and write channels to OpenCL code and I see that they are correctly instantiated in <kernel>_system.v SV file, but there is no connection to the I/O. I am using a10_ref design as a baseline and have added the following to my board_spec.xml file:

<channels>
<interface name="data_port" port="data_out" type="streamsink" width="32" chan_id="data0_in"/>
<interface name="data_port" port="data_in" type="streamsource" width="32" chan_id="data0_out"/>
</channels>

In OpenCL code I declare these as IO channels:

#pragma OPENCL EXTENSION cl_intel_channels : enable
channel float DATA_IN __attribute__((depth(0)))
__attribute__((io("data0_in")));
channel float DATA_OUT __attribute__((depth(0)))
__attribute__((io("data0_out")));

float data_read = read_channel_intel(DATA_IN);

float data_to_send = test_value;
write_channel_intel(DATA_OUT,data_to_send);

One would expect these channels to be brought up to at least <kernel>_system.v SV file IO, but this is not so. The <kernel>_system instance has correct Avalon-ST sink and sources but they are "bolted up" to bit width translators and then trail ends.

If someone has done this, and I know some of you have, you know whom I am talking about: OpenCL certified board vendors; please share the knowledge.

Cheers.

Reading the mAX ii ufm

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Hi,
how can i read the .pof file from the ufm of max ii (EPM570GF256)

Please teach me appropriate Software.

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Hello,

I have Flex6000「EPF6024AQC240-2」,EPC1441PCB,USB-Blaster.

I'd like to do a configuration using these.
Which Software is appropriate?

I think 「Quartus Ⅱ Version 9.0」
But I can't configuration…

Please advaice me:oops:

Implement mux using for loop

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Hi
I think it is possible to implement a mux using a for loop like in the following example:

Code:

type array_type is array (7 downto 0) of std_logic_vector(15 downto 0);
signal mux_in:    array_type;
signal mux_slct: unsigned(2 downto 0);
signal mux_out: std_logic_vector(15 downto 0);

...

p_mux : process(mux_slct,mux_in)
begin
  mux_out <= (others=>'0');
  for i in 0 to 7 loop
      if i=mux_slct then
        mux_out <= mux_in(i);
      end if;
  end loop;
end process p_mux;

My problem is that Quartus seems (based on RTL viewer) to synthesise it as a priority circuit which is not efficient at all.
Does anyone knows if:
-> something is missing in my code?
-> Quartus doesn't support this construction?
-> Some config of the synthesis tool could solve this?

I'm using Quartus II 32-bit Version 12.1 Build 243 01/31/2013 SJ Web Edition

Thanks in advance,

Jean

Information needed for slave addressing from master...

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Hi All,
I am having 256 bit data width and 64 bit address width avalon bfm master and 512 bit data width 30 bit slave.In between i have one interconnect.
The base address is 64'h 0000_0010_0000_0000(Byte addressable) .while i am sending the data to the 512 bit slave next address range is what?

Is it 64'h0000_0010_0000_0040 or 64'h0000_0010_0000_0020 ? Which data width i have to take master or slave ...

Please someone guide me .


Thanks
Venkat

working with uart 16550 altera IP

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Hi,
Hi,

We are using altera UART 16550 core from qsys (for now with time limit restriction ) and copied the full example tests from "Embedded Peripherals IP user guide " ( UG-01085 ) , example 8-3 .

We build project in NIOS II operating system ucos II and run it in debugging mode step by step.

1. after altera_16550_uart_open(...) , default baud rate =0 in altera_16550_uart_state structure.
2. after alt_16550_uart_config(...) were the baud rate needs to be changed to 115200 we see the boudrate still equals 0 in structure altera_16550_uart_state.
3. still, we continue to execute the first test ( baud rate test ). on the first alt_16550_uart_read(...) the test hang and we didn't see even one byte transmitted / received .

(to make that nothing was transmitted , we have connected the transmit port to external terminal and indeed saw nothing)

someone knows what we are missing?


Thank you!

Reducing memory replication

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Hi, I'm working on an OpenCL kernel that is using a 2MB dataset and I've currently been reading in the entire 2MB into on-chip memory, performing the operations (random read/writes) and then outputting the 2MB result back to global memory.

I've had no problems doing this as a single-work-item kernel but when I attempt to parallelize the kernel by adding a for-loop with a #pragma unroll 1 I get a massive blowup in local-memory usage from the tools

+--------------------------------------------------------------------+
; Estimated Resource Usage Summary ;
+----------------------------------------+---------------------------+
; Resource + Usage ;
+----------------------------------------+---------------------------+
; Logic utilization ; 39% ;
; ALUTs ; 21% ;
; Dedicated logic registers ; 19% ;
; Memory blocks ; 697% ;
; DSP blocks ; 5% ;
+----------------------------------------+---------------------------;


  • Private memory: Potentially inefficient configuration
  • Requested size: 2097152 bytes
  • Implemented size: 33554432 bytes
  • Number of banks: 2 (banked on lowest dimension)
  • Bank width: 1024 bits
  • Bank depth: 8192 words
  • Total replication: 16 - Replicated 16 times to create private copies for simultaneous execution of 16 threads in the loop containing accesses to the array.
  • Running memory at 2x clock to support more concurrent ports
  • Additional information: Requested size 2097152 bytes, implemented size 33554432 bytes, replicated 16 times total, stallable, 4 reads and 3 writes. - Reduce the number of write accesses or fix banking to make this memory system stall-free. Banking may be improved by using compile-time known indexing on lowest array dimension. - Replicated 16 times to create private copies for simultaneous execution of 16 threads in the loop containing accesses to the array. - Banked on lowest dimension into 2 separate banks. - See Best Practices Guide: Local Memory for more information.
  • Private memory implemented in on-chip block RAM.


Any ideas on how to stop this replication?

"External connection" conduit on DDR2 controller (with ALTMEMPHY)

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I am working on a Cyclone IV design, and need a DDR2 controller.

Using Qsys, I have added the IP block DDR2 SDRAM CONTROLLER with ALTMEMPHY

One of the interfaces on this IP is labeled "external_connection" and contains three signals, all outputs: local_init_done, local_refresh_ack, reset_phy_clk_n

I get a Qsys warning that this must be exported or connected to a matching conduit.

My problem is that I don't know what I am supposed to do with these signals.

the link to online documentation for the IP doesn't work, I get the "404" error at the Altera website. I have tried looking in the "Embedded Peripherals IP User Guide" under "SDRAM Controller core" but there is no mention of these signals that I can find.

Can anyone help me?

Rod
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