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how to initialize f2h_sdram from system console

September 15, 2017, 12:49 pm
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I searched the forum, I consulted google, but was unable to find any relevant information. Hoping someone can point me in the right direction.

I am using a cyclone 5 (it is actually the MitySoM module from Critical Link, an Altera partner). I want to write data from the FPGA to the DDR mempry over the f2h_sdram bridge. More specifically, I am from trying to using the frame buffer from Altera's VIP in a video application.

In trying to bring this system up, i want to be able to use system console so it's not software dependent. I want to use trace system + system console to verify before bringing software into it.

I know that the HPS peripherals , and the bridge specifically, needs to be initialized. I know the u-boot bootloader normally does this. How can I initialize the bridge if I'm just using just system console?

Thanks for any help
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Qsys without nios II

September 15, 2017, 1:32 pm
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please let me know that, can i implement an algorithm in Qsys without using Nios processor. means using only programmable logic[i.e. fpga area] while excluding the soft-core. Or should i go with quartus II and megafunctions ?
thanks in adavance
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Arria 10 core PLL error 15744

September 15, 2017, 11:35 pm
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I'm getting the following error when instantiating a generated Arria 10 core PLL (fpll_inst):


Code:
  Error (15744): The settings must match one or more of these conditions:
    Error (15744): ( prot_mode == UNUSED ) OR ( pllcout_enable == PLLCOUT_DISABLE ) OR ( m_cnt_in_src == M_CNT_IN_SRC_CSCD_CLK ) OR {((vco_freq_hz-7'h64)<=(cnt_div*f_out_c2))}
    Error (15744): But the following assignments violate the above conditions:
    Error (15744): prot_mode = BASIC_TX
    Error (15744): f_out_c2 = 12135922
    Error (15744): vco_freq_hz = 5000000000
    Error (15744): pll_c2_pllcout_enable = PLLCOUT_ENABLE
    Error (15744): pll_c_counter_2 = 412
    Error (15744): pll_c_counter_2_in_src = M_CNT_IN_SRC_PH_MUX_CLK
Looking into the qsys file I see that


Code:
<parameter name="gui_hssi_prot_mode" value="0" />
But in the xml file generated from the qsys file I observe:


Code:
<parameter name="prot_mode" value="basic_tx" />
How can I control this parameter, or the others to satisfy the requirements?
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Cyclone 10 GX PCIe dev kit?

September 15, 2017, 11:51 pm
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Are there any Cyclone 10 GX PCIe dev kits available or will any such dev kits be available soon?
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The BSP Editor unable to edit or create the HPS BSP

September 16, 2017, 1:31 am
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Hi, All:

I create a QSys system for my Cyclone V SoC chip, and according to the manual, I need to create the BSP for the chips then I can run my QSys system correctly.
According to the manual, I open the Embedded Command Shell.bat in Administrator, and enter

Code:
bsp-editor &
to open the BSP Editor.
But in the BSP Editor, I see the menu File -> New HPS BSP... is gray, I can not click on it.

I try to open a example bsp file in the CD of my development board, the BSP Editor reported several errors, and can not open them.
The errors like:

Code:
Available BSP type values for the --type argument are:[hal, ucosii]
BSP type "spl" unknown
NullPointerException
I see that is a error due to the BSP Editor can not find the HPS BSP Informations.
I try to reinstall the software, even install in my virtual machine, but all of them are got same erros.
What's wrong with my approach?
Thank you very much.
Dmitri Abramovic
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DE0-nano-SoC - Is it possible to reconfigure it at run-time?

September 16, 2017, 7:07 am
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Hi all,

as the title says, I would like to know that before buying.

Thanks!
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Implementing the ADC Controller with MegaWizard (DE0-Nano board) problems

September 16, 2017, 4:57 pm
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Hello,

I am using the ADC IP controller as a .bdf file in a hardware-based environment. I ve connected all pins with the used interface in order to interact with the ADC128S002 Analog-to-Digital Converter (thanks to the good documentation).
But here s one issue I am facing with that documentation (ftp://ftp.altera.com/up/pub/Altera_M...0-Nano_ADC.pdf).
On chapter 3.3 it clearly emphasizes that the ip core is going to update itsself regulary. Here is the quote: "The MegaWizard version of the controller allows access to between two and eight channels, with channel values updating automatically." But thats not the case when I want to check a 1.5 V battery or several power banks from different microcontrollers using signaltap and watching at each channel data could get captured. I ve checked pin assigments in quartus as well as gpio header connection but no data can be caugth. Since the ADC is using the SPI protocol I can watch its dynamic behaviour on signaltap. It looks fine, but data isnt pushed into any channel. Has anybody some approach to solve that problem?
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Can not Log in the Account of MyAltera in Official Website https://www.altera.com/

September 17, 2017, 5:29 pm
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Hi,


I tried to log in the MyAltera but it shows the invalid value. I tried to reset the password and created a new account but still didn't work. Is there any problem of the login database of your website? Does anyone have the same issue?


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how to program epm240 with MCU？

September 18, 2017, 2:06 am
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hello,
my epm240 code is working well,how can I programming epm240 with STM32 MCU?
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Constraining byte deserializer after ALTLVDS_RX

September 18, 2017, 2:29 am
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Hello everyone.
I just ended up with problem using ALTLVDS_RX megafunction.
I need to recieve 12 bit data from CMOS sensor (ADC is not adjustable for 10 bit resolution), so I generated 6 bit ALTLVDS_RX with external PLL and a byte deserializer with mod-2 counter.
Now I have 6 bit input with 74.25 MHz clock and 12 bit output with 37.125 MHz clock generater from the same PLL. 12 bit output register is feeded by 74.25 MHz clock. After that I want to use 37.125 MHz as main system clock for image processing. Everything compiles but TimeQuest told me that nothing will work. My SDC file contains:
-create_clock....
-derive_pll_clocks -create_base_clocks
-derive_clock_uncertainty

So I suppose that I need to tell TQ that CLK_EN on 12 bit register force it to refresh half of the feeding clock, and everything is fine and synchronous, but I don't know how to, except set_fallse_path, but I think it's not the right solution.
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Problem on Linux PCI Express driver for an Avalon-MM DMA reference design

September 15, 2017, 8:51 am
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Hi Everyone,

I'm following this link http://www.alterawiki.com/wiki/Refer...MA_-_Stratix_V to setup DMA communication for Stratix V device. I have successfully program the FPGA and the hardware side seems to be Okay. However, I have difficulty running the Linux Driver provided in the above link for Linux. Before telling what exactly the problem is it might be good to know that I have ubuntu and the kernel version is 3.19.

So, trying to install the driver I got this message running dmesg.

Altera DMA 0000:01:00.0: can't enable device: BAR 0 [mem 0x00000000-0x000001ff 64bit pref] not claimed

Worth to mention, when I run lspci command here is what I get:
01:00.0 Non-VGA unclassified device: Altera Corporation Device e003 (rev 01)

So I assume there should be any problem with the hardware side because the linux can detect the pcie connected device.

Is anyone have any thoughts what might be the problem ? Thank you in advance for any help.

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DE5_NET OpenCL support on Ubuntu 16.10

September 15, 2017, 8:59 am
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I'm trying to use the OpenCL SDK for the Terasic DE5_Net board.
I'm using the BSP provided by Terasic in their website.

But I start having (at least) two differences with the expected setup.

1) I am using the latest Quartus and OpenCL SDK Versions (Version 17.0.2 Build 602).
2) I am using an Ubuntu 16.10 with a 4.8.0-59-generic kernel version

Apparently the first point is not problematic.

The second point is more troublesome.

When you try to compile the board kernel driver (>aocl install) the compilation crashes because the get_user_pages function (from mm.h) has less parameters in newer kernels. I have tried to implement the missing function (with more parameters) getting inspiration from older kernel sources. See the implementation below
// @author David Castells-Rufas
// In new kernels (> 4.6) get_user_pages use current task info,
// so go to the more complete function. I get some inspiration from
// http://elixir.free-electrons.com/lin...m/nommu.c#L162
long get_user_pages_old_kernel(struct task_struct *tsk, struct mm_struct *mm,
unsigned long start, unsigned long nr_pages,
int write, int force, struct page **pages,
struct vm_area_struct **vmas)
{
int flags = 0;


if (write)
flags |= FOLL_WRITE;
if (force)
flags |= FOLL_FORCE;


return __get_user_pages(tsk, mm, start, nr_pages, flags,
pages, vmas, NULL);
}


When I do this, the driver compiles but when I execute I get some errors and the system finally crash.
With this [failing] driver you can still do >aocl diagnose (without parameters) but when you try ">aocl diagnose acl0" the system starts transferring memory, and the application detects a lot of memory errors...
Transferring 8192 KBs in 16 512 KB blocks ...
Error! Mismatch at element 1008: 3f0 != 1efbf0, xor = 001ef800
Error! Mismatch at element 1009: 55b1a2e9 != 1229541c, xor = 4798f6f5
...

To solve these issues I have looked for a debian package with a kernel having the get_user_pages function with the long list of parameters. I found it to be 4.4.0-24-generic. So I installed it and recompiled the driver against it.

After rebooting my system using the 4.4.0 kernel the OpenCL driver works and ">aocl diagnose acl0" runs smoothly.
However I would like to work with the newer kernel as it has other implications (for other drivers).


Anyone knows whether there are drivers adapted to newer Linux Kernels?
Or whether anyone has tried to do it or either Altera/Intel or Terasic have internal people working on that?

Thanks !
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Altera_mm_interconnect functionality

September 18, 2017, 4:37 am
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Hi All,
I have 256 bit input data and 64 bit address in input side of mm_interconnect. In output side 256 bit data and 30 bit address.
How this altera_mm_ interconnect transfer the data for 2 beat transfer. Will it club two 256 bit data and generate one 512 bit write data in output side or Based on byte_enable signal will it send two
256 bit data.
Please someone explain functionality of this.I could not find any spec pdf releated to this.



Thanks
Venkat
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include path to header files from bsp

September 18, 2017, 7:53 am
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Hello,

I've got a question:

I created a NIOS II application with BSP from the Micro C/OS II hello-template using the the eclipse SBT.
My problem is that i always have to write the complete relative path when i for example want to include
the generated system-header file (system.h) into a file of my application folder for some reason.

shouldn't it be possible just to write #include "system.h" instead of #include "../project_name_bsp/system.h" , since this file is part of the BSP?
I already saw examples where they included system.h and other device-driver-headers without writing the whole relative path each time.

Did i missed something? Do i have to adapt something in the bsp settings? Cleaning the project and re-generating the BSP did not change anything.
Thanks in advance

rookie2017
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Using PCIe pins as GPIO on Cyclone IV GX FPGA Development Kit

September 18, 2017, 11:02 am
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Hi,
I am looking into purchasing the Cyclone IV GX FPGA Development Kit from Terasic but was wondering if the following is possible.
I need to physically interface to another FPGA board that has a min PCIe slot. However the communication protocol over which the two boards
will communicate will not be PCIe. The protocol will be proprietary but will mimic a bus that is closest to SPI. My question is, can I use the PCIe pins on
Cyclone IV GX FPGA Dev Kit as GPIO (general purpose Input/Output lines)? If this is possible, are there any special hooks/trick I need to consider or implement other than just simply assigning
specific pin to my signal? All feedback is welcome, and thank you!!!
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Cyclone V Fractional PLLs don't output expected clock frequency

September 18, 2017, 1:05 pm
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I'm using Quartus 17.0.2. I have trying to generate a 148.5MHz clock with a 50MHz input reference clock. When I put the PLL in fractional mode and enter 148.5M as my target frequency the megawizard states that it can achieve the exact frequency of 148.5MHz and provided no warning message about not being able to get the exact clock rate. (See attached image.)

However, when I look at the STA report I see that the actually frequency of the clock is 148.53515625MHz.
And the multiply/divide values are as follows:

For VCO:
Multiply= 4563
Divide = 512
For Clock output:
Multiply = 1
Divide = 3

Why is the PLL telling me that it can achieve my exact frequency when it's really not??

The frequency observed in hardware on an oscilloscope is indeed about 148.54MHz which is not what I specified in the megawizard.

What makes this even worse is that a VCO multiply value of 4562 would actually generate a frequency closer to what I requested (even though not exact). So that's pretty bad behavior for the tool.
Attached Images
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Altera mm interconnect

September 19, 2017, 2:59 am
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Hi All,
Please anyone explain the functionality of altera_mm_interconnect. If you have any link for that please post .

Thanks
Venkat
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Linux boot runs application differently to command line

September 19, 2017, 4:54 am
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Hi,
I'm running linux 3.10.87-ltsi on a Cyclone V.
I have an application that starts multiple threads, and changes the priority on some of these as well. It also loads two kernel drivers to give me access to a GPIO interrupt and contiguous memory for FPGA access.

All of these load and run fine, if I run them from the ssh shell.
However, if I run them from a script that systemd runs at boot time, then although the drivers load correctly, and the threads priorities get set correctly the application itself doesn't seem to run at the same performance level - ie we get data loss.

Is there any trick to persuading linux to run the application as if it were run from the command line once boot had finished?

Or any hints as to what I should watch for when starting applications during boot?

Regards,
Simon
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Setup timing violation

September 19, 2017, 5:25 am
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Should I just split the combinatorial logic at line 15 of the following verilog module or https://github.com/promach/internal_...eck_data.v#L15 across several registers ?


Code:
`include "define.v"

module check_data (clk, data_out, data_in, test_failed);  // verifying the memory (circular buffer) read and write processes

input clk;
input [(`DATA_WIDTH-1) : 0] data_out;  // memory output
input [(`DATA_WIDTH-1) : 0] data_in;  // memory input

output reg test_failed = 0;

wire data_out_is_valid;

always @(posedge clk)
begin
    if(((data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY) != (data_in + 1)) && data_out_is_valid)  // due to "delay.v"
    test_failed <= 1;
end

assign data_out_is_valid = (data_in >= `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY) &&
              (data_in < `MEMORY_SIZE + `MEMORY_SIZE + `USER_HOLDOFF + `ALIGNMENT_DELAY);

endmodule
Attached Images
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Arria V GX (5AGXMB7) with Elpida DDR3 calibration passes, doesn't work

September 19, 2017, 7:46 am
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Hi!
Has anybody tried working with Arria V GX Hard IP DDR3 UniPHY connected to a DDR3 successfully?
In my case it is 5AGXMB7 connected to two Elpida (now Micron) EDJ4216EFBG-GN-F in x32 configuration on my custom board.
The calibration for DDR3 passes successfully every time but the data on read gets corrupt after an arbitrary number of read commands.
Same with the write operation. It stops writing after writing some number of words at a page.
After changing a page the operation continues.
Looks like the operations stop acting appropriately when they get overlapped by a refresh operation.
Also the soft reset helps to resume normal operation for a small period.
Any ideas on possible solutions?
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