September 19, 2017, 5:05 pm
My project (GHRD derivative with custom IP and EMIF blocks) gets through the first phases of compilation fine, but about 10 seconds into the Assembler phase (just enough time to output the first 3 lines of status text to the messages window) the "Sorry" dialogue window pops us so I can report the crash to Intel.
I get absolutely no useful input as to:
a.) what just happened (I get the software crashed, but give me some breadcrumbs somewhere I can follow!)
b.) searchable warning or error message/number
c.) nothing logged in reports showing any issue that might explain the crash, or what leads up to it
Anybody seen something similar, and willing to share your work-around or solution? Any ideas where I might find some clues?
Thanks,
-VJR
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September 19, 2017, 11:54 pm
Hi, I am trying to run the hello world design example downloaded from Altera using the emulator on Windows 8.1 with Visual Studio 2015. When I try to run "aoc -march=emulator -v device/hello_world.cl -o bin/hello_world_emulation.aocx", i get the linker error regarding to "kernel32.lib".
By referring to this thread, https://www.alteraforum.com/forum/sh...ad.php?t=46646
I somehow fix the error by manually added additional path (C:\Program Files (x86)\Windows Kits\8.1\Lib\winv6.3\um\x64) to LIB environment variable.
But, i still get the error: "Linker Failed"
This is the output i get from my "hello_world.log" file:
LINK : fatal error LNK1104: cannot open file 'ucrt.lib'
It is possible cause by I didn't manage to run the "äocl_diagnose" successfully??
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↧
September 20, 2017, 12:33 am
Hi all Altera members!:)
I use the megafunction QDRII + and SRAM. At initialization there is a problem. The Pin Local_init_done is held at zero. At the same time, the local_cal_fail pin rises to logical 1:confused:. At the same time, the PLL is locked, the frequencies go to the output. When creating a project, I used standard TCL scripts for Assigments and for Timings. From the point of view of iron - everything is connected correctly. Maybe someone has a solution. Read and write it does not work. But before the pin local_cal_fail is approved, the output of avalon is incomprehensible to me data. Help please with this question:(. I am using device: "Stratix III EP3SE110F780I3", and QDR memory:"CY7C15632KV18-400BZXI". Thank you in advance.
http://s1.radikale.ru/uploads/2017/9...c1a39-full.png
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September 20, 2017, 2:27 am
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September 20, 2017, 4:08 am
Edited: wrong forum, please delete.
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↧
September 20, 2017, 4:42 am
Hi everyone,
I'm currently working on my end of degree project at university which is about using a MAX10 FPGA for Closed-loop Control Systems.
The thing is that in order to make it work, I need to be able to select the sampling instant of the ADC so I can sample whenever I want.
I've been using Qsys, but it only gives you the option to select the sampling rate. I want it to sample when I wish.
I think that it probably has something to do with the way you use the different signals that Qsys automatically generates once you configure your ADC and add it to the project:
command_valid, command_ready, start_of_packet, end_of_packet, response_valid, response_data... and so on.
I would be very grateful if you could help me with this. ;)
Just for reference, I'm using:
-A MAX10 10M50DAF484C7G
-DE10-Lite Board
Thank you in advance!
↧
September 20, 2017, 5:09 am
I used the NIOSII_processor_booting_an370 guide
(option 2) to combine an elf- and a sof-file into a
pof-file. I put the pof-file into flash and the application
ran o.k.
However, when I programmed the sof- and elf-file
separately I got this error when downloading the
elf-file:
--
Verify failed between address 0x18080000 and0x1808001F
Leaving target processor paused
--
Is it impossible to use sof- and the elf-file in this way
because of the changes necessary to put them in flash?
Thanks,
Jos
↧
September 20, 2017, 5:59 am
Hello.
I have simple question - Can I make NiosII system with External Interrupt (VIC) with some RTOS and successfully worked with interruptions ?
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September 20, 2017, 1:07 pm
I'm following the tutorial on the intelFPGA monitor program for the DE1-SoC Arm 9 core, and I'm using the sample DE1-SoC Computer program with sample program JTAG Uart demonstration. However, the board will not connect using semihosting, or any other program for that matter.
Error message reads Could not query JTAG Instance IDs.Please ensure the FPGA has been configured using the correct .sof file.
It's the correct .sof file, even tried manually connecting using the GUI button to connect, still of no avail.
I tried the NIOS II program and everything runs fine.
Why can it not communicate?
It's set to the cpu0- core and not the one that powers up in reset.
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↧
September 20, 2017, 2:52 pm
When I first installed Altera II Baseline 10.2, a directory "mp2student" was installed. I would like to use some of the those files in my course but I can't find the old CD, or any links to those files by searching. Can anyone point me to where I can find them or or a replacement CD?
Very frustrated!
JCC
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September 20, 2017, 3:44 pm
This is a Cyclone IVe design, using Quartus 17.0
I have a qsys system where I have instantiated the DRAM controller "DDR2 SDRAM Controller with ALTMEMPHY"
When I try to run analysis / synthesis I got this error:
Error (13059): The DDIO_OUT WYSIWYG primitive "core:core1|core_ddr2:ddr2|core_ddr2_controller_ph y:core_ddr2_controller_phy_inst|core_ddr2_phy:core _ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2 _phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_cl k_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_ outa[0]" feeding the pin "ddr2_clk" has multiple fan-outs
My qsys block is named "core". The only connections to the ddr2_clk are to the module port of the "core" module, and then it is an output port of the top level module. It does not connect anywhere else.
As an experiment I left the port disconnected. then I got this error:
Error (15873): Output port DATAOUT of DDIO_OUT primitive "core:core1|core_ddr2:ddr2|core_ddr2_controller_ph y:core_ddr2_controller_phy_inst|core_ddr2_phy:core _ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2 _phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_cl k_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|ddio_ outa[0]" must drive input port I of an I/O OBUF primitive. It currently drives "core:core1|core_ddr2:ddr2|core_ddr2_controller_ph y:core_ddr2_controller_phy_inst|core_ddr2_phy:core _ddr2_phy_inst|core_ddr2_phy_alt_mem_phy:core_ddr2 _phy_alt_mem_phy_inst|core_ddr2_phy_alt_mem_phy_cl k_reset:clk|altddio_bidir:DDR_CLK_OUT[0].ddr_clk_out_p|ddio_bidir_n5h:auto_generated|input _cell_h[0]"
So I noticed that it specified that the signal must be connected to an I/O port. I had previously connected it to an "output" so I changed it to be an I/O port. Back to the same error I started with.
can anyone tell me what the problem is?
Rod
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September 20, 2017, 4:41 pm
Hi,
we use MAX V series for our product, however, when I trying to debug it, I found out it does not support the SignalTap, the part number is 5M240ZT100C5N.
So, I'm wondering is there any other CPLD/FPGA can support SignalTap and pin to pin compatible with MAXV (5M240ZT100C5N).
Thanks
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September 20, 2017, 4:48 pm
Hi All,
I remember my username and password for the forum, but i don't remember what email address I was registered with.
How can I know the email address I registered with it in the forum? It doesn't appear in my Profile section.
Thank you!
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September 20, 2017, 5:04 pm
Hi All,
While execution of the Analysis & Elaboration stage in the Quartus Prime (v16.1.2), I'm receiving the following message in the Messages Window:
"Warning (125092): Tcl Script File ../../../../../../../../../drives/H/Electronics/FPGA/VHDL/lphud_fpga/arria_v_cores_lib/hdl/serdes_pll_rtl/serdes_pll_rtl_0002.qip not found
"
But I checked and found that this file physically exists in this directory. It seems that the problem is in the path to the file. So, I think to replace the relative path to the file to the absolute path. But I don't know what TCL script is executed while the Analysis & Elaboration stage... What script should be altered with the path to the file?
Please help.
Thank you!
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September 20, 2017, 5:15 pm
Hi All,
Where can I find the log file of the Quartus Prime?
I'd like to see there what scripts / commands were executed by Quartus Prime.
What the location of the log file? Are there different log files for different stages (log for Elaboration, log for Synthesis, etc)?
Thank you!
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September 20, 2017, 5:42 am
I'm currently trying to make a small module that can read and write custom data to the Flash on the MAX10 Devkit. This fits into a bigger system, and the current state machine is just a simple test.
Now, I'm connecting the QSPI_IO, QSPI_CLK and QSPI_CSn to the approriate pins.
However I get a bunch of warnings from the compile process.
Code:
Warning (13039): The following bidirectional pins have no drivers
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Code:
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "QSPI_CLK" is stuck at GND
Warning (13410): Pin "QSPI_CSn" is stuck at GND
Code:
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_3_" driven by bidirectional pin "QSPI_IO[3]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_3_" driven by bidirectional pin "QSPI_IO[3]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_2_" driven by bidirectional pin "QSPI_IO[2]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_2_" driven by bidirectional pin "QSPI_IO[2]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_1_" driven by bidirectional pin "QSPI_IO[1]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_1_" driven by bidirectional pin "QSPI_IO[1]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_0_" driven by bidirectional pin "QSPI_IO[0]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_0_" driven by bidirectional pin "QSPI_IO[0]" cannot be tri-stated
So what ends up happening is that my state machine runs, and tries to request a read at memory address 240. The state machine sets up the process for reading from memory on the avalon bus, but setting the address and read, while waiting for the readdatavalid that obviously never arrives as the QSPI signals are stuck on GND. Is there anything wrong in my instantiation that I cannot find?
I'm using the component info from the QUAD_SPI_n25q_512_inst.vhd file generated by Qsys.
I've had to remove the state machine code for length, but I'm trying instantiate the module as follows:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLASH_CTRL is
generic(
ADDR_START : unsigned(23 downto 0):= to_unsigned(0,24);
ADDR_END : unsigned(23 downto 0):=to_unsigned(1024,24)
);
port(
i_clk : in std_logic;
i_rst : in std_logic;
i_mode : in std_logic_vector(2 downto 0);
i_data : in std_logic_vector(31 downto 0);
i_addr : in std_logic_vector(23 downto 0);
o_data : out std_logic_vector(31 downto 0);
o_newdata : out std_logic;
QSPI_CLK : out std_logic;
QSPI_IO : inout std_logic_vector(3 downto 0);
QSPI_CSn : out std_logic_vector(0 downto 0)
);
end FLASH_CTRL;
architecture RTL of FLASH_CTRL is
component QUAD_SPI_n25q_512 is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
generic_quad_spi_controller_0_clock_sink_clk : in std_logic := 'X'; -- clk
generic_quad_spi_controller_0_reset_reset_n : in std_logic := 'X'; -- reset_n
generic_quad_spi_controller_0_avl_csr_read : in std_logic := 'X'; -- read
generic_quad_spi_controller_0_avl_csr_waitrequest : out std_logic; -- waitrequest
generic_quad_spi_controller_0_avl_csr_write : in std_logic := 'X'; -- write
generic_quad_spi_controller_0_avl_csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
generic_quad_spi_controller_0_avl_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
generic_quad_spi_controller_0_avl_csr_readdata : out std_logic_vector(31 downto 0); -- readdata
generic_quad_spi_controller_0_avl_csr_readdatavalid : out std_logic; -- readdatavalid
generic_quad_spi_controller_0_avl_mem_write : in std_logic := 'X'; -- write
generic_quad_spi_controller_0_avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
generic_quad_spi_controller_0_avl_mem_waitrequest : out std_logic; -- waitrequest
generic_quad_spi_controller_0_avl_mem_read : in std_logic := 'X'; -- read
generic_quad_spi_controller_0_avl_mem_address : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
generic_quad_spi_controller_0_avl_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
generic_quad_spi_controller_0_avl_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
generic_quad_spi_controller_0_avl_mem_readdatavalid : out std_logic; -- readdatavalid
generic_quad_spi_controller_0_avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
generic_quad_spi_controller_0_interrupt_sender_irq : out std_logic; -- irq
generic_quad_spi_controller_0_flash_dataout_conduit_dataout : inout std_logic_vector(3 downto 0) := (others => 'X'); -- conduit_dataout
generic_quad_spi_controller_0_flash_dclk_out_conduit_dclk_out : out std_logic; -- conduit_dclk_out
generic_quad_spi_controller_0_flash_ncs_conduit_ncs : out std_logic_vector(0 downto 0) -- conduit_ncs
);
end component QUAD_SPI_n25q_512;
type t_state is (IDLE,DATAREAD1,DATAREAD2,DATAWRITE1,DATAWRITE2,CSRREAD,CSRWRITE,HOLD);
signal r_mode : unsigned(3 downto 0);
signal state : t_state;
signal r_addr : unsigned(23 downto 0);
signal r_counter2 : unsigned(31 downto 0);
signal r_datareg : unsigned(15 downto 0);
--QUAD_SPI_n25q_512_bb interface
--signal clk_clk : std_logic;
--signal reset_reset_n : std_logic;
signal gqsc_reset_reset_n : std_logic;
signal gqsc_csr_read : std_logic;
signal gqsc_csr_waitrequest : std_logic;
signal gqsc_csr_write : std_logic;
signal gqsc_csr_address : unsigned(2 downto 0);
signal gqsc_csr_writedata : std_logic_vector(31 downto 0);
signal gqsc_csr_readdata : std_logic_vector(31 downto 0);
signal gqsc_csr_readdatavalid : std_logic;
signal gqsc_mem_write : std_logic;
signal gqsc_mem_burstcount : unsigned(6 downto 0);
signal gqsc_mem_waitrequest : std_logic;
signal gqsc_mem_read : std_logic;
signal gqsc_mem_address : unsigned(23 downto 0);
signal gqsc_mem_writedata : std_logic_vector(31 downto 0);
signal gqsc_mem_readdata : std_logic_vector(31 downto 0);
signal gqsc_mem_readdatavalid : std_logic;
signal gqsc_mem_byteenable : std_logic_vector(3 downto 0);
signal gqsc_clock_sink_clk : std_logic;
signal gqsc_interrupt_sender_irq : std_logic;
signal gqsc_flash_dataout_conduit_dataout : std_logic_vector(3 downto 0);
signal gqsc_flash_dclk_out_conduit_dclk_out : std_logic;
signal gqsc_flash_ncs_conduit_ncs : std_logic;
begin
QUAD_SPI : QUAD_SPI_n25q_512 port map(i_clk,
i_rst,
gqsc_clock_sink_clk,
i_rst,
gqsc_csr_read,
gqsc_csr_waitrequest,
gqsc_csr_write,
std_logic_vector(gqsc_csr_address),
gqsc_csr_writedata,
gqsc_csr_readdata,
gqsc_csr_readdatavalid,
gqsc_mem_write,
std_logic_vector(gqsc_mem_burstcount),
gqsc_mem_waitrequest,gqsc_mem_read,
std_logic_vector(gqsc_mem_address),
gqsc_mem_writedata,gqsc_mem_readdata,
gqsc_mem_readdatavalid,
gqsc_mem_byteenable,
gqsc_interrupt_sender_irq,
QSPI_IO,
QSPI_CLK,
QSPI_CSn);
end architecture;
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September 20, 2017, 6:44 am
How can we infer the following memory module as RAM instead of register array ?
https://github.com/promach/internal_...memory_block.v
I have tried to modify, but some inevitable warnings are shown.
http://quartushelp.altera.com/14.1/mergedProjects/msgs/msgs/wtdb_analyze_comb_latches.htm
Code:
`include "define.v"
module memory_block (clk, write_enable, waddr, raddr, data_write, data_read);
input clk, write_enable;
input [(`ADDR_WIDTH-1) : 0] waddr;
input [(`ADDR_WIDTH-1) : 0] raddr;
input [(`DATA_WIDTH-1) : 0] data_write; // data to be written into memory
output reg [(`DATA_WIDTH-1) : 0] data_read; // data read out from memory
reg [(`DATA_WIDTH-1) : 0] memory [(`MEMORY_SIZE-1) : 0];
always @(*) begin
if (write_enable)
memory[waddr] = data_write;
end
always @(*) begin
if (!write_enable)
data_read = memory[raddr];
end
endmodule
![]()
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↧
September 20, 2017, 11:39 pm
I'm currently trying to make a small module that can read and write custom data to the Flash on the MAX10 Devkit. This fits into a bigger system, and the current state machine is just a simple test.
Now, I'm connecting the QSPI_IO, QSPI_CLK and QSPI_CSn to the approriate pins.
However I get a bunch of warnings from the compile process.
Code:
Warning (13039): The following bidirectional pins have no drivers
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Warning (13040): bidirectional pin "QSPI_IO" has no driver
Code:
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "QSPI_CLK" is stuck at GND
Warning (13410): Pin "QSPI_CSn" is stuck at GND
Code:
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_3_" driven by bidirectional pin "QSPI_IO[3]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_3_" driven by bidirectional pin "QSPI_IO[3]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_2_" driven by bidirectional pin "QSPI_IO[2]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_2_" driven by bidirectional pin "QSPI_IO[2]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_1_" driven by bidirectional pin "QSPI_IO[1]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_1_" driven by bidirectional pin "QSPI_IO[1]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QSPI_IO_0_" driven by bidirectional pin "QSPI_IO[0]" cannot be tri-stated
Warning (14632): Output pin "pre_syn.bp.inst10_QUAD_SPI_generic_quad_spi_controller_0_flash_dataout_conduit_dataout_0_" driven by bidirectional pin "QSPI_IO[0]" cannot be tri-stated
So what ends up happening is that my state machine runs, and tries to request a read at memory address 240. The state machine sets up the process for reading from memory on the avalon bus, but setting the address and read, while waiting for the readdatavalid that obviously never arrives as the QSPI signals are stuck on GND. Is there anything wrong in my instantiation that I cannot find?
I'm using the component info from the QUAD_SPI_n25q_512_inst.vhd file generated by Qsys.
I've had to remove the state machine code for length, but I'm trying instantiate the module as follows:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FLASH_CTRL is
generic(
ADDR_START : unsigned(23 downto 0):= to_unsigned(0,24);
ADDR_END : unsigned(23 downto 0):=to_unsigned(1024,24)
);
port(
i_clk : in std_logic;
i_rst : in std_logic;
i_mode : in std_logic_vector(2 downto 0);
i_data : in std_logic_vector(31 downto 0);
i_addr : in std_logic_vector(23 downto 0);
o_data : out std_logic_vector(31 downto 0);
o_newdata : out std_logic;
QSPI_CLK : out std_logic;
QSPI_IO : inout std_logic_vector(3 downto 0);
QSPI_CSn : out std_logic_vector(0 downto 0)
);
end FLASH_CTRL;
architecture RTL of FLASH_CTRL is
component QUAD_SPI_n25q_512 is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
generic_quad_spi_controller_0_clock_sink_clk : in std_logic := 'X'; -- clk
generic_quad_spi_controller_0_reset_reset_n : in std_logic := 'X'; -- reset_n
generic_quad_spi_controller_0_avl_csr_read : in std_logic := 'X'; -- read
generic_quad_spi_controller_0_avl_csr_waitrequest : out std_logic; -- waitrequest
generic_quad_spi_controller_0_avl_csr_write : in std_logic := 'X'; -- write
generic_quad_spi_controller_0_avl_csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
generic_quad_spi_controller_0_avl_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
generic_quad_spi_controller_0_avl_csr_readdata : out std_logic_vector(31 downto 0); -- readdata
generic_quad_spi_controller_0_avl_csr_readdatavalid : out std_logic; -- readdatavalid
generic_quad_spi_controller_0_avl_mem_write : in std_logic := 'X'; -- write
generic_quad_spi_controller_0_avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
generic_quad_spi_controller_0_avl_mem_waitrequest : out std_logic; -- waitrequest
generic_quad_spi_controller_0_avl_mem_read : in std_logic := 'X'; -- read
generic_quad_spi_controller_0_avl_mem_address : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
generic_quad_spi_controller_0_avl_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
generic_quad_spi_controller_0_avl_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
generic_quad_spi_controller_0_avl_mem_readdatavalid : out std_logic; -- readdatavalid
generic_quad_spi_controller_0_avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
generic_quad_spi_controller_0_interrupt_sender_irq : out std_logic; -- irq
generic_quad_spi_controller_0_flash_dataout_conduit_dataout : inout std_logic_vector(3 downto 0) := (others => 'X'); -- conduit_dataout
generic_quad_spi_controller_0_flash_dclk_out_conduit_dclk_out : out std_logic; -- conduit_dclk_out
generic_quad_spi_controller_0_flash_ncs_conduit_ncs : out std_logic_vector(0 downto 0) -- conduit_ncs
);
end component QUAD_SPI_n25q_512;
type t_state is (IDLE,DATAREAD1,DATAREAD2,DATAWRITE1,DATAWRITE2,CSRREAD,CSRWRITE,HOLD);
signal r_mode : unsigned(3 downto 0);
signal state : t_state;
signal r_addr : unsigned(23 downto 0);
signal r_counter2 : unsigned(31 downto 0);
signal r_datareg : unsigned(15 downto 0);
--QUAD_SPI_n25q_512_bb interface
--signal clk_clk : std_logic;
--signal reset_reset_n : std_logic;
signal gqsc_reset_reset_n : std_logic;
signal gqsc_csr_read : std_logic;
signal gqsc_csr_waitrequest : std_logic;
signal gqsc_csr_write : std_logic;
signal gqsc_csr_address : unsigned(2 downto 0);
signal gqsc_csr_writedata : std_logic_vector(31 downto 0);
signal gqsc_csr_readdata : std_logic_vector(31 downto 0);
signal gqsc_csr_readdatavalid : std_logic;
signal gqsc_mem_write : std_logic;
signal gqsc_mem_burstcount : unsigned(6 downto 0);
signal gqsc_mem_waitrequest : std_logic;
signal gqsc_mem_read : std_logic;
signal gqsc_mem_address : unsigned(23 downto 0);
signal gqsc_mem_writedata : std_logic_vector(31 downto 0);
signal gqsc_mem_readdata : std_logic_vector(31 downto 0);
signal gqsc_mem_readdatavalid : std_logic;
signal gqsc_mem_byteenable : std_logic_vector(3 downto 0);
signal gqsc_clock_sink_clk : std_logic;
signal gqsc_interrupt_sender_irq : std_logic;
signal gqsc_flash_dataout_conduit_dataout : std_logic_vector(3 downto 0);
signal gqsc_flash_dclk_out_conduit_dclk_out : std_logic;
signal gqsc_flash_ncs_conduit_ncs : std_logic;
begin
QUAD_SPI : QUAD_SPI_n25q_512 port map(i_clk,
i_rst,
gqsc_clock_sink_clk,
i_rst,
gqsc_csr_read,
gqsc_csr_waitrequest,
gqsc_csr_write,
std_logic_vector(gqsc_csr_address),
gqsc_csr_writedata,
gqsc_csr_readdata,
gqsc_csr_readdatavalid,
gqsc_mem_write,
std_logic_vector(gqsc_mem_burstcount),
gqsc_mem_waitrequest,gqsc_mem_read,
std_logic_vector(gqsc_mem_address),
gqsc_mem_writedata,gqsc_mem_readdata,
gqsc_mem_readdatavalid,
gqsc_mem_byteenable,
gqsc_interrupt_sender_irq,
QSPI_IO,
QSPI_CLK,
QSPI_CSn);
end architecture;
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September 21, 2017, 12:36 am
Hi.
Is there a way to force the compiler to use registers for a 2-dimensional array?
I am experimenting with an interconnect kernel whose structure is easier to express with array indices.
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September 21, 2017, 2:50 am
Hello,
i have created a design in Qsys and want to boot it through SD card.
I have created the files required for booting and I have put them in SD card. But I get the following error:
U-Boot 2014.10 (Sep 20 2017 - 20:23:08)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
** No partition table - mmc 0 **
Failed to set filesystem to FAT.
Flash probe failed.
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
data abort
pc : [<ffe00cc2>] lr : [<ffe02331>]
sp : ffe3def8 ip : 0000001c fp : 00000001
r10: ffd02078 r9 : ffe3ff38 r8 : ffe00054
r7 : ffe20c94 r6 : ffe20c40 r5 : 00000000 r4 : ffffd000
r3 : ffcfb000 r2 : 00000002 r1 : 00000001 r0 : 00000001
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
U-Boot 2014.10 (Sep 20 2017 - 20:23:08)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
SOCFPGA DWMMC: 0
** No partition table - mmc 0 **
Failed to set filesystem to FAT.
Flash probe failed.
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe386e8
data abort
pc : [<ffe00cc2>] lr : [<ffe02331>]
sp : ffe3def8 ip : 0000001c fp : 00000001
r10: ffd02078 r9 : ffe3ff38 r8 : ffe00054
r7 : ffe20c94 r6 : ffe20c40 r5 : 00000000 r4 : ffffd000
r3 : ffcfb000 r2 : 00000002 r1 : 00000001 r0 : 00000001
Flags: nzcv IRQs off FIQs off Mode SVC_32
Resetting CPU ...
resetting ...
It goes into infinite loop. and I am not able to boot the system. Any idea on this?
** No partition table - mmc 0 **
Failed to set filesystem to FAT.
What does this mean?
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