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altera merlin width adapter parameter setting - PACKING

September 21, 2017, 3:30 am
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Hi All,
In altera merlin width adapter we have one packing parameter .Is this parameter related with burst operation ?
If i un check this will it support for burst operation. What is the use of this packing parameter.

Thanks
Venkat
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MAX10 DDR3 Controller Error (17044): Illegal connection on I/O input buffer primitive

September 21, 2017, 10:26 am
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I purchased the Altera MAX10 FPGA Development Kit with the intent of experimenting with the DDR3 controller. After instantiating the IP and compiling the project I get the dreaded "Error (17044): Illegal connection on I/O input buffer primitive". This happens with Quartus 15.1 (recommended in the readme file for the kit), Quartus 16.1, whether I build the controller through the IP tool/catalog or through Qsys.

There are a number of posts about this that date back to 2012, but nothing current, or relevant Presumably nobody is having problems with this lately. Any ideas?
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can not run RTL and gate-level simulation using Quartus_prime lite

September 21, 2017, 5:05 pm
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Hi,
“The path to the location of the executables for the ModelSim-Altera software were not specified or the executables were not found at specified path”

I add the "\" and there is no space.
C:\intelFPGA\16.1\modelsim_ase\win32aloem\

can anyone help me to fix this problem？

Thanks
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How do I get the detail area of blackbox memories in design compiler?

September 21, 2017, 6:49 pm
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I use some memories in my FFT code but though the report_area gives memory area, I can't get a break down of the individual instances with -hier flag or report cell/references etc.

Are there any other instructions I could use besides writing my own tcl scripts?
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Erasing MAX-V devices using commandline option.

September 21, 2017, 1:34 pm
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Hello All,
Please help me with this simple task.

I've a PCB with three CPLDs (Altera 5M160Z). I'm using following commands to program these CPLDs:
Quote:
c:
cd\
cd intelFPGA_pro\17.0\quartus\bin64
start quartus_pgm -z --mode=JTAG --operation="p;C:\Test Firmware\CPLD_U1.pof@1"
start quartus_pgm -z --mode=JTAG --operation="p;C:\Test Firmware\CPLD_U2.pof@2"
start quartus_pgm -z --mode=JTAG --operation="p;C:\Test Firmware\CPLD_U3.pof@3"
To give more information, I'm attaching following screenshots:
1> Windows Device Manager (listing the USB Blaster)


2> Quartus Programmer Window (on selecting 'Auto Detect'):


Now my requirement is to create a command line program (BAT file) for erasing all the contents. I've came across 'Erase_All' function, however I failed in my attempt to use the same.

Thank you in advance.
Attached Images
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hold time violation using MAX V

September 21, 2017, 11:41 pm
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Hi,

I saw some hold time violation when I trying to run the STA.
I believe the problem is because the source and destination FFs of this path are on different clock domains, and the tool thinks there is large skew between these domains. skew= 5.42, data delay = 3.17, the slack is around -2.3.
so is there anything I can do to fix this problem?

Thanks!!!!
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EPCS Discontinuation, looking for replacement.

September 22, 2017, 8:42 am
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Hi,
I have been using EPCS flash device in my design, since Altera is discontinuing it, I was looking for replacements, I found EPCQ devices to be a good match but they are not in stock on any suppliers like Digikey/Mouser and also on Altera's website, buyaltera.com. The part that I am looking for is EPCQ4ASI8N (I am actually looking for a part which is pin-pin compatible with EPCS4SI8N).

I tried looking for any non-altera parts which would be pin-pin compatible and found some like MX25R4035F, but they seem to have subtle variations in the protocol, moreover, I don't know if they will work with Altera's FPGA. I am using an Altera Cyclone 3 FPGA(EP3C10E144I7).

1. Is there a way that I can get a couple of samples of EPCQ devices(EPCQ4ASI8N specifically), the lead time is 14 weeks?
2. Are there any non-altera alternatives that I can use?

Thanks
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Fatal ERROR on Quartus II

September 22, 2017, 11:32 am
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i'm having a problem when a try to compile some vhdl codes in Quartus, Someone here knows how to fix it?

The message that i see when i try is:



*** Fatal Error: Access Violation at 0X000007FED0F2802F
Module: quartus_map.exe
Lock in use: 54
Stack Trace:
0x20802e: VRFX_ELABORATOR::operator= + 0x4b94e
0x21982d: VRFX_ELABORATOR::operator= + 0x5d14d
0x214182: VRFX_ELABORATOR::operator= + 0x57aa2
0x2143c1: VRFX_ELABORATOR::operator= + 0x57ce1
0x221acb: VRFX_ELABORATOR::operator= + 0x653eb
0x21c470: VRFX_ELABORATOR::operator= + 0x5fd90
0x2265c3: VRFX_ELABORATOR::operator= + 0x69ee3
0x22209f: VRFX_ELABORATOR::operator= + 0x659bf
0x18c1cf: VRFX_ELABORATOR::elaborate + 0x13281f
0x190418: VRFX_ELABORATOR::elaborate + 0x136a68
0x190b2c: VRFX_ELABORATOR::elaborate + 0x13717c
0x605b6: VRFX_ELABORATOR::elaborate + 0x6c06
0x59b9c: VRFX_ELABORATOR::elaborate + 0x1ec
0xc50b3: sgn_clear_check_ip_functor + 0x3aeb3
0xc8d7f: sgn_clear_check_ip_functor + 0x3eb7f
0xca666: sgn_clear_check_ip_functor + 0x40466
0x92834: sgn_clear_check_ip_functor + 0x8634
0xa37fc: sgn_clear_check_ip_functor + 0x195fc
0xa01ba: sgn_clear_check_ip_functor + 0x15fba
0xa384c: sgn_clear_check_ip_functor + 0x1964c
0xa79ee: sgn_clear_check_ip_functor + 0x1d7ee
0x10cc2: sgn_qic_full + 0x152






0x11fad: qexe_get_command_line + 0x1b7d
0x14e0e: qexe_process_cmdline_arguments + 0x59e
0x14f21: qexe_standard_main + 0xa1


0x4c78: msg_exe_fini + 0x58
0x53bc: msg_exe_fini + 0x79c
0x1584: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x194
0x5f9f: msg_exe_main + 0x8f


0x159cc: BaseThreadInitThunk + 0xc
0x2a560: RtlUserThreadStart + 0x20


End-trace


Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SJ Web Edition
Service Pack Installed: 1
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Pin Assignments won't import

September 22, 2017, 3:03 pm
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Hello,

I'm using Cyclone II chip, on Quartus II 12.1 SP1. This is required because my school uses that version. Anyhow, when I try to go to Assignments > Import Assignments..I try to import by selecting the appropriate QSF file, and I've tried a CSV version as well that my school both supplies. Sadly, when I go to Pin planner it just shows the location column as empty.. meaning the only way to do the pin assignments would be manually to edit one by one. Is there any fix for this issue? I've tried using different computers, my verilog code compiles no problem, I just don't understand what the issue is.

Regards,

Nisha
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Fails to compile when using the hard DDR controller in Cyclone V part.

September 22, 2017, 4:36 pm
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HI,

I am using the Altera Cyclone V GT development kit. I have been working with this board for about 2 years.

The card has 2 banks of DDR memory. One bank is 64-bits wide, and uses a soft core. The other bank is 32-bits wide and uses a hard core.
I have been using the 64-bit memory.

I have a need to add the 32-bit memory to the mix. I added the 32-bit core to my design.
I am getting a fail at compile time. The failure message is shown below. Does anyone know what this message means, and how I can fix it?

Error (17044): Illegal connection on I/O input buffer primitive ADC_Block
:U1|q_sys_all
:b2v_inst10|q_sys_all_DDR3_VRB
:ddr3_vrb|q_sys_all_DDR3_VRB_p0
:p0|q_sys_all_DDR3_VRB_p0_acv_hard_memphy:umemphy| q_sys_all_DDR3_VRB_p0_acv_hard_io_pads
:uio_pads|q_sys_all_DDR3_VRB_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev
:altdq_dqs2_inst|strobe_in.
Source I/O pin ADC_Block:U1|q_sys_all:b2v_inst10|q_sys_all_DDR3_V RB:ddr3_vrb|q_sys_all_DDR3_VRB_p0
:p0|q_sys_all_DDR3_VRB_p0_acv_hard_memphy:umemphy| q_sys_all_DDR3_VRB_p0_acv_hard_io_pads
:uio_pads|q_sys_all_DDR3_VRB_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_ cyclonev
:altdq_dqs2_inst|obuf_os_0 drives out to destinations other than the specified I/O input buffer primitive.
Modify your design so the specified source I/O pin drives only the specified I/O input buffer primitive.
File: C:/Echodyne/FPGA_Files/A_Current_Files/ADC_Card5_S8_Vector_LB/Q_SYS_ALL/Q_SYS_ALL/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv Line: 954
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TRDB-D5M vga project

September 23, 2017, 4:51 am
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Hello, I am using DE1-soc board and try to output VGA Image after image processing.
The camera I use is TRDB-D5M and I want to modify the vga resolution from 640x480 to 1024x768 in the example code for the de1soc board. I just want to fix the resolution but I have a difficulty with this process. I am not modifying VGA_Controller.v and PLL, but I am trying to modify the CMOS Sensor register setting(LUT Table) in I2C_CCD_Config.v
Is it necessary to make such a lot of modifications to change only the resolution? If I print it out in vga, the timing is of course strange.

Please help me if you have used TRDB-D5M Camera.
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Adjustable frequency generator

September 23, 2017, 4:59 am
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Hi,

I am trying to implement adjustable rectangular wave generator in MAX10. The code below:

Code:
library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity    DIVIDER_2 is


port(
clk:      in STD_LOGIC;
O    :      out STD_LOGIC
);


end DIVIDER_2;


   
architecture DIVIDER_2 of DIVIDER_2 is   
   
    signal divider: integer range 0 to 20000:=666;        -- USTAWIAMY DZIELNIK
    signal counter: integer range 0 to 2000:=0;   
    signal OI : STD_LOGIC;
   
    begin
    O <= OI;
   
    process (clk) is 
   
        begin
        if rising_edge (clk) then
       
            if (counter < divider) then
            counter <= counter + 1;
            else
            OI <= not OI;
            counter <= 0;
            divider <= divider + 1;
            end if;
       
        end if;
   
    end process;


end DIVIDER_2;
It doesn't work. Without incrementation divider each half cycle, works well.
Does anyone have any idea what is wrong?
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Quartus 17 and older FPGA boards

September 23, 2017, 7:45 am
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Hi, I am a student studying EEE and have chosen a module that requires the use of Quartus Prime 17 Lite. I have no real experience of the software/hardware but with limited lab time in university I want to augment my learning from home. I have downloaded and installed Quartus Prime 17 Lite and successfully compiled my project for the DE10-Lite by Terasic, but the target board I have at home is the Cyclone II EP2C5. Is it possible to add support for my target board, or do I have to download a legacy version of Quartus Prime? If so, how different is the software from a beginners perspective? Ideally I would buy a DE10-Lite to use at home, but I am sure you understand that being a broke student I have to be very frugal with my purchases.

Thanks :)
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I can't install devices (Quartus 17.0 prime lite edition)

September 23, 2017, 1:11 pm
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Hello everyone, I've just installed Quartus 17.0 ;
I downloaded at the oficial altera web site, I selected the option download Quartus,Model sim and Cyclone V devices.
Though I downloaded everything necessary, when I try to create a new wizard project, the System says: "You must have device support installed before you can opean a project. To download device supoort, go to the Download Center section of the intel FPGA".

I got a solution in the internet to install it but it dind't work. The solution was: TOOLS > INSTALL DEVICE, when I tried a messege dialog appeared : "The Quartus Prime software cannot launch the Device installer for some Windowns operating systems. You can launch the device installer directly from Windowns Start menu"

But I have the device (Cyclone V series) installed. The file's name is "cyclonev-17.0.0.595.qdz" . Anyone knows how I can fix this issue?
Thanks, Adriel
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Quartus Prime Lite ( Editor cuts off my text..help!?)

September 23, 2017, 8:29 pm
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I"m running Quartus Prime Lite 16.1 and when I create a ".vhd" file and start typing in it parts of my text disappear. It's like only the first 10 or so characters are displayed and some invisible barrier or pane is keeping me from seeing my text. How can I fix this? See the image below.
Attached Images
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ModelSim-Altera not working on Ubuntu 17.04(Kernel 4.10)

September 24, 2017, 9:54 am
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I have the next problem with ModelSim-Altera I couldn't simulate any project, after making some research I get to the point that the problem is the Kernel version of Ubuntu 17.04. The solution for Kernel 3.x was adding what we see in text editor aside but if I tried adding kernel 4 get me an different error if vsim was damaged.
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Altera FPGA stream (de)compression - How to do it

September 24, 2017, 11:42 am
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Modelsim-Altra @ Quartus Prime Lite Edition

September 24, 2017, 10:37 pm
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Hello All,

I just installed Quartus Prime Lite (V17.0) and I am trying to simulate my design, first. But, I got a message below, even I am thinking that I set up the suitable path. I attach the messages. Could you comment me what I miss ? Thanks.

BRianK.
Attached Files
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Linux Console with framebuffer on DE10-nano SOC

September 25, 2017, 12:39 am
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Terasic support provided Linux Console with "framebuffer" on DE1-SOC board (https://www.terasic.com.tw/cgi-bin/p...o=836&PartNo=4), I succeeded to deal with it. now, I am working on DE10-nano SOC, but there isn't Linux Console with framebuffer image with DE10-nano SOC and I can't use DE1-soc framebuffer image with DE10-nano.
How can I get this image ?
can I configure Linux console and add framebuffer driver ?
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JTAG timing constraints

September 25, 2017, 3:48 am
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Hi,

Over the years my company has made many Altera FPGA designs, and for a long time the way-of-work for JTAG constraints remained undefined and of little consequence. Then for a couple Arria V designs, JTAG instability became a hot issue (e.g. random failures when discovering the JTAG chain, using SignalTap, using SystemConsole). Our initial strategy probably was to not constrain JTAG at all (as JTAG is 'slow' and its logic is fixed), but then we would get Quartus errors regarding unconstrained ports/clocks. We then tried to find constraints recommended directly by Altera, but never could find a conclusive, complete, satisfactory answer. Based on experience we do feel that the constraints actually affect JTAG stability, and so we're still keeping an eye out for a good solution. Note that the JTAG hardware part for our designs was always rather basic, so we don't think the instability originates from there.

A selection of the examples and best practices we have found and tried over the years:
- Old TimeQuest cookbook: can't find it anymore
- Recent TimeQuest cookbook: https://www.altera.com/content/dam/a...t_cookbook.pdf
- Knowledge base item 1: https://www.altera.com/support/suppo...82016_788.html
- Knowledge base item 2: https://www.altera.com/support/suppo...82008_867.html
- Forum post: https://www.alteraforum.com/forum/sh...ad.php?t=56328

Some of these examples seem to contradict each other, adding to the confusion.

My specific questions for Altera are:
1) What are the JTAG constraints recommended by Altera?
2) Are there any plans regarding JTAG constraints? E.g. having Quartus automatically implement them?
3) Are there any known JTAG issues for the Arria V family? If there are, are these fixed in the 10 series?

Best regards,

Daniel
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