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UFM Status Register Read Successful for burst reads?

September 27, 2017, 5:04 pm
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I am doing burst reads to the UFM and I was wondering if (bit 2) in the UFM status register reports when a burst read is finished or if this after each read.

I am programming a MAX10.

-Chuck
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Port number limitation prevents my codes from compiling

September 27, 2017, 6:10 pm
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I have two questions.

What I want to do is :

I want to send 144 8bit numbers from my computer to FPGA, and let the FPGA store the numbers in memory in the FPGA.
And let the verilog block I have coded receive the numbers as input.

Question 1 : I got the error message when I compile the code, which says "Error (169281): There are 1252 IO input pads in the design, but only 458 IO input pad locations available on the device." I think the port number limitation prevents my codes from compiling. Can't I receive 144 8bit numbers from the memory in the FPGA?
Question 2 : Can you give me information or tips how to make the code to transfer 144 8bit numbers from my computer to FPGA?
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Data writed into the on-chip-flash IP Core of MAX10 lost after power down!!!!

September 28, 2017, 1:20 am
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Data writed into the on-chip-flash IP Core of MAX10 lost after power down!

hello，
i use the on-chip-flash ip core of max10 to store data of my project. the on-chip flash IP Core can read and write data in normal,but the data that i writed into ip core lost after power down.

when powerd up, the data read is not that writed into the ip core before power down,but FFFFFFFFH.The parameters of ip core and the part result of ip core are as followes.

how can to keep the data into the flash ip core after power down ?(the initiation file was not into ip core). look forward to your reply ,thanks !

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How to can Qsys read from a memory used by a non-Qsys block?

September 28, 2017, 3:53 am
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I am writing an JPEG image encoder, the basic idea is
1. Data comes from camera, is debayered and stored in memory
2. This pixel data is then read in 8x8 blocks, processed and result stored back into the same memory at an offset from the pixel data
3. Data is read by Nios II and stored in an SD card



The logic for steps 1 and 2 is autonomous i.e the processor does not play any significant role in it. The reason I even need a processor is that in order to store data in SD card, one needs a file system and thus a processor is indispensible.
The basic question here is that, once I have stored the data in memory i.e SRAM or SDRAM by the main part of the design, how do I go about accessing it and storing it in SD card? i.e how to link the two parts of the design? Should the logic in 1 and 2 be in the Qsys system or it is ok for it to be outside it?


I have considered a DMA but that is more difficult at this stage i.e using DMA to transfer for data write to SD card
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Unable to communicate through SPI slave to Avalon Master IP

September 28, 2017, 7:32 am
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Unable to communicate through SPI slave to Avalon Master IP

September 28, 2017, 8:21 am
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Hello, I'm using Altera's SPI slave to Avalon Master Bridge IP to interface with a SPI master on a BeagleBone Black. Both sides are working with 3.3V CMOS logic levels. I'm using Qsys to connect the IP with the FPGA Avalon MM (please see attached qsys file) and exporting the SPI slave bus to the top level of the FPGA and routing the signals to pins connected to the BBB SPI master. On the BBB side I'm using the source code provided by Altera to interface with the IP Core using an external processor and replaced alt_avalon_spi_command with a SPIdev function (please see attached source code).


So far I've been able to probe the MOSI pin when writing a 0x00000001 to address 0x3c (this address is mapped to an LED on my SoC board and I have tested it's working before using Altera's LW Axi Master), here's the pattern:


0x7A 0x7C 0x00 0x00 0x00 0x00 0x04 0x00 0x00 0x00 0x3C 0x00 0x00 0x00 0x7B 0x01
SOP CH ID Trans type Size Address Data & EOP before last data byte


Which is consistent with the protocol on Altera's software library, but I haven't been able to read or write to any Address on the FPGA MM. I do get some activity on the MISO pin (below in hex), but it doesn't match with the protocol:


20 48 94 94 94 94
94 94 94 94 89 49
49 49 49 29 00 00
00 00 00 00 00 00


I verified that the SPI signals from the BBB are received on the FPGA SPI pins by putting then in output pins and probe them, the pattern is working fine, the CS signal is being asserted (active low), SCLK and MOSI are received properly.
Attached Files
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Need help using transceivers on Stratix II Gx with alt2gxb megafunction

September 29, 2017, 12:53 am
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Hey everyone,

I am trying to get a very simple design to work: I have a 16-Bit counter and want to send and receive the 16 Bit number via the transmitter and receiver of the same channel.
I found a thread in this Forum for exactly the same project, but there was not enough information for me and the most recent post in it was from 2009.

In the best case I would like to have working example files if anyone could provide them.
But Tips or directions to a good tutorial would also be highly appreciated.

So let me tell you what i did up till now:
The Parameters of the alt2gxb in the most recent version of my project look like this:
Basic Protocol, no loopback
Receiver and Transmitter, one channel, width: 16 Bit

frequency 100 MHz data rate 1000 (maybe this is one of my problems, but low datarate shouldn't be problem, should it? The post i was referring to said that you ought to use the sfp_refclk with 155.56 MHz. I tried it, but then the project wouldn't compile because somehow it wouldn't accept any standard (LVDS or otherwise) in the pinplanner so now I simply use what is called "CLK 1").

I train the receiveer PLL from pll inclk

For Reset I use gxb powerdown, rx digital, rx analogue tx digital, pll locked and rx freqlocked with an initialization sequence like advised in the Stratix II gx transceiver architecture overview on page 217.

On the Ports/callibration page i just checked "use calibration block" and connected the resulting input with my 100 MHz clock

8b/10b encoding is enabled and word alignment is manual (I don't really use word alignment, I know that I should, but i was under the impression, that for the first few numbers sent after the initialization sequence there shouldn't be alignment issues? Is that kind of thinking wrong?).

The initialization sequence that i mentioned above starts when I push a button on the dev board.
This way I can programm the FPGA via signaltap, start data aquisition and THEN get the design going (so I really se the very first events on the output of my transceiver).
I record the rx_out_wires of the alt2gxb function, what comes out looks like what i attached. There are a lot of FEFEs (i guess they are some kind of controll signals, but they are not the standard word alignment pattern) and the data that is not FE is just random and doesn't look like a counter to me.

So yeah thats it, any help would be appreciated.

Thanks a lot in advance.
Cheers
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Please teach me pin assignment of a connector of [PLMJ1213]

September 29, 2017, 2:18 am
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Hello, I have a [PLMJ1213].
But I dont know pin assignment of a connector of [PLMJ1213]
Please teach me...
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simple SPI on MAX V - what's wrong here?

September 29, 2017, 2:26 am
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Hi,

in a project I want to use MAX V (precisely: 5M40ZE64I5N) operating as a slave on SPI bus, so I've started to prepare a very simple module for communication over SPI bus. My device uses 5 lines:

nrst - reset, negative logic,
ncs - chip select, negative logic,
sck - clock,
mosi - input of data to MAX V,
miso - output of data from MAX V.

I have a strange problem with outputting data on the miso line. I'd appreciate any hint on what's the cause, please.

I'm using Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition.

The code is attached. As you can see, the module gets ready for work once nrst is high and ncs gets low, then it should output data on the miso line, the data change on falling edge of clock sck. The data should be an sequence of alternating '1's and '0's, starting with a '1'. The input line mosi is ignored.

Quartus shows the RTL diagram that I'd expect to see:


The simulator (gate level simulation in ModelSim AE) says it should work as assumed:


however the oscilloscope shows something different:

yellow - sck (2V/div)
green - miso (2V/div)
time scale 20us/div (so it's ca. 120kbit/s)

The first bit is set correctly as '1', then the first falling edge triggers transition to '0', and the next falling edges are ignored. Why?

Best regards,
Adam
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Attached Files
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Is there a standard way for an FPGA Qsys system (Nios II) to access HPS pins?

September 29, 2017, 4:21 am
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Is there a standard method to connect FPGA side Qsys system Nios II to HPS pins and disable the HPS access to them? This needs to be done for UART, GPIO and Pushbuttons for Cyclone V SoC on the DE10-Nano board for experimental purpose at this time.
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Sorry! The Quartus Prime software quit unexpectedly.

September 29, 2017, 5:53 am
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When you have vhdl with an error like:
data(to_integer(index) to to_integer(index)+15)<="101010101010101";
(the right side is one bit short)
Quartus stops but does not tell you why.
I contacted Altera technical support, but as this problem only appears in the Lite version they won't fix it.
So on your own trying to understand what crashed Quartus.:(

Well... at least an internet search may help you now with this problem.
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SIgnaltap Export All Datalogs

September 29, 2017, 9:32 am
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Hi,

I have a bunch of datalogs in a signaltap file that I'm trying to export in bulk. I can select the individual logs and export as csv, but I can't seem to find a way to export all into csv or multiple csv's. Is there an easy way to get all of this data into excel?

TIA!
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HPS Freeze when Writing DDR4

September 29, 2017, 10:02 am
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Hi,
I am using a ReFLEX Achilles Dev Kit that has two DDR4 memories. I have them both connected to the HPS. The first one is connected to the emif port of the HPS and the second one is connected to the HPS2FPGA bridge with an address span extender in QSYS. I am running Linux on the HPS and I am using mmap to write and read from memory mapped locations. It seems to work correctly... I read whatever I write into the memory location and if I write the address span extender control register and read, it is a different value. However, after I was satisfied with this, I tried to add various parallel I/O to connect to my FX3 USB and LCD screen that is connected to the lightweight HPS 2 FPGA bridge. When I added these, the HPS will usually freeze when I try to read the HPS2FPGA bridge connected DDR4 memory. Usually the read works, but sometimes the system will freeze up too. By freeze I mean it is no longer echoing my serial inputs back to my console and also if I have an SSH connection up, it usually disconnects. I assume from these occurrences that the HPS is frozen. Writes always make the HPS freeze.
I am fairly new to developing on a SoC system and Linux in general. Any feedback or tips would be helpful to me. Currently, I am trying to debug with DS-5, but I need to get an ultimate license for it I believe. One other thing is that I receive a "DDR timing not met" in my Quartus messages. Would timing cause the HPS to freeze if it cannot access the DDR4 through the bridge? I am still learning about timing quest and still not sure how to fix timing problems or find timing problems.

Thank you
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Can not reprogram the FPGA/JTAG does not respond

September 29, 2017, 12:31 pm
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Hello everyone,
I have several custom pcb board with MAX 10 Fpga inside. I programmed the FPGAs with a .pof file that gets stored on to the flash. After that I am unable to reprogram the boards again! The altera device programmer is unable to communicate with the FPGA through JTAG.

Is there a way to reset the FPGA, like clearing the flash content ? I hope that would allow me to reprogram. Because the assumption is that the existing stored design that gets mapped from flash somehow contradicts with the JTAG.
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How can I figure out what made my Fitter (Place and Route) time balloon?

September 29, 2017, 2:16 pm
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I have a design that was rather small and was only taking 10 minutes to complete from start to finish and was only taking a small fraction of the space on an Arria10. I added a portion of code (three components) and a few custom components to the NIOSII and now the fitter time has ballooned to over two hours. When it finally finishes, is there any good way to look at the report and see what took so long? I can go through the design and take pieces out until I find the one that is taking all the time, but I'm hoping there's a more efficient way to zero in on the offending logic.
Quartus Prime Standard Edition 16.1.2 on Windows 7.
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Booting from the QSPI flash

September 29, 2017, 4:53 pm
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Hi,

I've been working on the Cyclone V SOC for the past month or so, and now I've completed my application. The final task is to boot this application VIA the NOR flash every time the system powers up. This has been done, and my application runs every time.

Now, the NOR flash has a size of 64MB, and my application is only 1MB in size, and I was hoping to use the remaining 63MB for data storage, and stuff like that. Therefore, my application performs R/W transfers on the NOR flash as well. The read transfers work fine, and I get to see the data stored in the flash, but the write transfers fail, specifically I post a write command to the flash, and the QSPI controller simply waits for the flash to respond but it never does. The flash is a Spansion S25FL512S.

Actually, when running my application via JTAG or booting from the SD card, the R/W to the flash work okay, and I'm able to write whatever I want to write, but this stops working when I boot from NOR flash. Thus I came to the conclusion that this might be caused because of the booting from the flash, and when we're booting from it, its write protected. Is this generally true ? Is there any way to bypass this because this is the only storage medium I want to use.


Regards,
Bilal
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Minimum pulse width error

October 2, 2017, 1:11 am
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Hi, I am geting a minimum pulse width error when I am trying to send a clock signal throw my fpga.

verilog code:
module top (
input CLK_125,
output TX_CLK
);

always TX_CLK = CLK_125;
endmodule

.sdc file:
create_clock -name clk125 -period 8.000 [get_ports {CLK_125}]
create_generated_clock -name gtx_clk -source [get_ports {CLK_125}] [get_ports {TX_CLK}]
derive_clock_uncertainty

timequest report:
slow 1200mV 100C Model :
slack: -5.445 , actual widht: 8.00 , required width: 13.445 , Type: Port Rate
fast 1200mV -40C Model:
slack: -12.00 , actual widht: 8.00 , required width: 20.00 , Type: Port Rate

in Pin Planer:
CLK_125 has location PIN26 and i/o standard 3.3V LVCMOS with current strength 2mA
TX_CLK has location PIN30 and i/o standard 3.3V LVCMOS with current strength 2mA

I am using a Max 10 fpga with speed rating I7 (10M50SC144I7G) as, if i have undrstood the datasheet corectly, has a ouput data rate of 310 MHz.

Why does timequest report an error?
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Arria 10 SX Dev Brd. How to program LMK04828? UG says "TI GUI" but no additional info

October 2, 2017, 10:52 am
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Arria 10 SX Dev Brd. How to program LMK04828? UG says "TI GUI" but no additional info. It seems like the board is designed so that LMK clock chip is programmed via J47 microUSB using some TI GUI tool. However, I'm not able to connect when I tried TI's TICS Pro or Code Loader. Any idea how the LMK chip can be programmed on this board? Thanks.
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Question on "SW-OPENCL-SDK". Does it include license for "QUARTUS"

October 2, 2017, 12:37 pm
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Hi

I have placed order for OPENCL package "SW-OPENCL-SDK". Does this include QURTUS Plus License to evaluate full tool flow?
That would help evaluate the flow before ordering boards. There is no clear documentation on the altera site, hence this question

Regards
Prasad
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Modelsim FLI/DPI license from Intel

October 2, 2017, 12:44 pm
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Hi,

Does regular ModelSim-Intel FPGA Edition license for 1995$ (alteramtivsim) enables FLI / DPI?

Thanks.
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