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H2F Bridge EMIF Access

October 2, 2017, 2:33 pm
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Hi,
I am using an Arria 10 ReFLEX Achilles dev kit that includes 2 DDR4 memories. The first DDR4 is used by the HPS and the second one I am trying to access from the HPS as well. To do this, I am using the HPS2FPGA bridge and an address span extender. The address span extender is a window of 512MB with 1 subwindow and the control register for the span extender is connected to the lightweight h2f bridge. I previously posted in SoC Dev Kits I believe and my problem was that the HPS was freezing when I was trying to write to the memory via hps2fpga bridge. I had some other peripherals connected so I have removed those to eliminate some elements that could possibly contribute to my problem. Now after compiling a few times and removing the other elements, it does not freeze when writing. However, my problem now is that when I write values, some values read back are incorrect. I have a little test program that writes X amount of values sequentially, then reads them, changes the window via the lw h2f bridge and writes X values and reads them through all 8 of my defined windows of 512MB. Then, it also does another read afterward that only reads the values and checks if they are the expected values. The values that are wrong seem to be the first 32 bytes. However, in different compiles where I slightly change something (for example, I added an LED that is assigned to the DDR4 calibration success / fail signal) the values that do not change are different. In this particular build, I cannot write the first 32 bytes as mentioned before, but in the past, I have had some compiles where everything seemed to work properly (even with all of my peripherals connected, these are usually just PIOs). However, if I changed something such as adding another PIO, it may or may not work. This problem has been really puzzling for me. I am fairly new to FPGAs and Linux in general and I tried to troubleshoot this issue. Any tips would be helpful.

At first, I thought it was a DDR4 timing problem because I was not meeting the timing requirements set by the ReFLEX reference design project that I based mine off of. Because of this, I changed it to be as simple as possible with only the address span extender and 2 memories connected to the HPS. When doing this, I do not receive a timing requirement not met message, but as mentioned before it still does not work as expected.

Between the freezing and the incorrect values, I cannot figure out what the problem is. As a note, I did not write a kernel module to write to the bridges; I am using mmap() and /dev/mem file descriptor to access the location.

Any tips, push in any direction (pretty lost right now), or help would be greatly appreciated.

Thank you!
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How to reduce M20K usage ?

October 3, 2017, 1:35 am
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Hi, I have problem when read some data from global memory.

Code:

typdef struct{
  float  data[8]
} vector_line;
typdef struct{
  vector_line lane[16]
} channel_vec;


__kernel
void ReadBlock(
__global const vector_line *restrict img,
__global channel_vec *restrict coef
)
{
vector_line img_vec;
channel_vec img_ch_vec;
channel_vec coef_ch_vec;

img_vec = img[some addr];
coef_ch_vec = coef[some addr];


}
This line
coef_ch_vec = coef[some addr]
on preliminary report consume 600+ M20K blocks
After compilation I saw 310 M20K blocks.
It is too much for storage array 16*8*4 = 512 bytes.
How can I reduce this quantity of M20K blocks.
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Transceiver PHY IP Core questions

October 3, 2017, 8:00 am
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I everyone,
I have some issues when implementing Transceiver on an Arria10 FPGA
Here is a recap :
Attila board (RXCA10X115PF40-IDK00A) with Arria10 GX Device
IP instanciate with QSys :
  • fPLL generating a 125MHz clock with the 100MHz from a SI53306 on board oscillator
  • ATXPLL generating a 625MHz clock (for TX serialization) with the 125MHz from fPLL
  • Transceiver Native PHY with one RX/TX channel, PCS direct, 1250Mbps datarate, clock division factor of 1, CDR clock fed with the 125MHz clock
  • 50MHz NIOS II (clock from IOPLL)
  • 3 PIO IP named "control", "data_in", "data_out"


Principle
  • parrallel data are registered with NIOS II using the PIO "data_out" (only one time, to avoid clock timing issues)
  • data are serialized with TX part of Transceiver, then go on FPGA pin AJ36/AJ37
  • We create a physical loopback on a 400 point FMC connector with a second card
  • data arrive on FPGA pin AF30/AF31 and then deserialized with RX part of transceiver
  • a change on the value of PIO "control" create a pulse signal (clock 50MHz) which is converted into an other pulse signal (clock rx_clkout from transceiver)
  • parrallel data are registered on the second pulse signal on PIO "data_in"


Here is the problem :
The transmission part seems good, we see the data serialized at a good frequency
But on the receiver side, the PMA seems not locked (signal lockedtodata and lockedtoref at 0, and rx_pma_clock frequency is not good), moreover the data on PIO "data_in" are not what we want.
We are on this problem since a long time and did not see where is the bug, is anyone has tried this kind of configuration ? Is the frequency too low for the transceiver PHY ?

Best regards
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Combinational Loop In VHDL synthesis

October 3, 2017, 7:22 am
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Dear all
I've been working on a project in which I build an interconnection network with similar modules. Each module has 4 inout dataports. Also they have two control ports, one for R/W (Read or Write) and one for switching (like a crossbar switch). To build up the network I need to connect these modules together via their inout data ports. I want to be able to transfer data bidirectionally. I have included my code at the end. This code just has two modules connected to each other.
- After synthesis in Quartus, ISE, or Synopsys Design Compiler or Synplify Pro, I get warnings which says there are a lot of nodes with combinational loop. But Why? Have I done anything wrong?
- The .vho netlist I get from Quartus, has inout ports with std_logic_vector type while my original design signed inout ports. Is this resulting from the combinational loops the synthesizer detects?

I would be grateful if anyone can help me with this.

The Module
Code:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;


    entity Inter_Con_Mod is
        generic(WL: integer:= 8);
        port(PortL0,PortL1,PortR0,PortR1: inout signed(WL-1 downto 0);
              RW: in std_logic;
                SW: in std_logic);
             
    end Inter_Con_Mod;
   
    architecture Behav of Inter_Con_Mod is
   
    begin


   
    PortR0 <= PortL0 when (SW = '0' and RW = '0') else
                  PortL1 when (SW = '1' and RW = '0') else
                (others => 'Z');
    PortR1 <= PortL1 when (SW = '0' and RW = '0') else
                  PortL0 when (SW = '1' and RW = '0') else
                (others => 'Z');
   
    PortL0 <= PortR0 when (SW = '0' and RW = '1') else
                  PortR1 when (SW = '1' and RW = '1') else
                (others => 'Z');
    PortL1 <= PortR1 when (SW = '0' and RW = '1') else
                  PortR0 when (SW = '1' and RW = '1') else
                (others => 'Z');



The Interconnection Example (Top Module)
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;




entity Datapath is
    generic(WL: integer:=8);
    port(DL0,DL1: inout signed(WL-1 downto 0);
          DR0,DR1: inout signed(WL-1 downto 0);
          C0,C1: in std_logic;
          RW: in std_logic);
         
end Datapath;


architecture Behavioral of Datapath is
      component Inter_Con_Mod is
            generic(WL: integer);
            port(PortL0,PortL1,PortR0,PortR1: inout signed(WL-1 downto 0);
                    RW: in std_logic;
                    SW: in std_logic);
        end component;


        signal M0_L0,M0_L1,M0_R0,M0_R1: signed(WL-1 downto 0);
        signal M1_L0,M1_L1,M1_R0,M1_R1: signed(WL-1 downto 0);
       
begin
   
    M0: Inter_Con_Mod
            generic map(WL => WL)
            port map (M0_L0,M0_L1,M0_R0,M0_R1,RW,C0);
    M1: Inter_Con_Mod
            generic map(WL => WL)
            port map (M1_L0,M1_L1,M1_R0,M1_R1,RW,C1);
   
    DL0 <= M0_L0 when RW = '1' else
              (others => 'Z');
    DL1 <= M0_L1 when RW = '1' else
              (others => 'Z');
   
    M0_L0 <= DL0 when RW = '0' else
                (others => 'Z');
    M0_L1 <= DL1 when RW = '0' else
                (others => 'Z');
    M1_L0 <= M0_R0 when RW = '0' else
                (others => 'Z');
    M1_L1 <= M0_R1 when RW = '0' else
                (others => 'Z');
                 
               
    M0_R0 <= M1_L0 when RW = '1' else
                (others => 'Z');
    M0_R1 <= M1_L1 when RW = '1' else
                (others => 'Z');
    M1_R0 <= DR0 when RW = '1' else
                (others => 'Z');
    M1_R1 <= DR1 when RW = '1' else
                (others => 'Z');
   
    DR0 <= M1_R0 when RW = '0' else
                (others => 'Z');
    DR1 <= M1_R1 when RW = '0' else
                (others => 'Z');               
                             
                             
end Behavioral;
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Routing a 5V signal through a 3,3V Cpld. Is the output 5V or 3,3V?

October 3, 2017, 3:19 pm
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Hi, I'm using an old Altera Cpld in a project, a Max 7000 series, which needs a 3,3V Vcc but the IOs are 5V compatible.

So, if I put a 5V input IO and route it to other output IO, this output will be 3,3V or 5V? By routing I mean a direct connection in my vhdl code.

I have some 5V inputs, and I want to put a 3,3V chip behind the Cpld, so I'm expecting that the output would be 3,3V, otherwise I can't use this approach.

Sorry if it's a newbie question.

Thanks...
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"The design unit was not found"

October 3, 2017, 4:38 pm
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Hi!

I am a complete noobie and have been directed to use this software for a class. I keep getting this error and the professor and IT department have been zero help and just tell me they do not know and to figure it out. I've seen a lot of similar posts with the same error but to be honest I have no idea what they are talking about for solutions. Can anyone please tell me how to fix this and what a design unit is?

# Reading C:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl
# do myFullAdder01_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
# vmap work rtl_work
# Copying C:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
#
# vlog -sv -work work +incdir+//Mac/Home/Desktop/EGR-2440/Altera {//Mac/Home/Desktop/EGR-2440/Altera/myFullAdder01.sv}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 18:56:03 on Oct 03,2017
# vlog -reportprogress 300 -sv -work work "+incdir+//Mac/Home/Desktop/EGR-2440/Altera" //Mac/Home/Desktop/EGR-2440/Altera/myFullAdder01.sv
# -- Compiling module myFullAdder01
#
# Top level modules:
# myFullAdder01
# End time: 18:56:03 on Oct 03,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
#
vlog -reportprogress 300 -work work //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
# Start time: 18:56:29 on Oct 03,2017
# vlog -reportprogress 300 -work work //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv
# -- Compiling module testMyFullAdder
#
# Top level modules:
# testMyFullAdder
# End time: 18:56:29 on Oct 03,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim work.testMyFullAdder
# vsim work.testMyFullAdder
# Start time: 18:56:42 on Oct 03,2017
# Loading sv_std.std
# Loading work.testMyFullAdder
# ** Error: (vsim-3033) //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv(6): Instantiation of 'myFullAdder' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /testMyFullAdder File: //Mac/Home/Desktop/EGR-2440/Altera/testMyFullAdder01.sv
# Searched libraries:
# //Mac/Home/Desktop/EGR-2440/Altera/simulation/modelsim/rtl_work
# Error loading design
# End time: 18:56:43 on Oct 03,2017, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
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Transciver phy IP Core problem

October 4, 2017, 12:33 am
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Hii

In my projet I am using Cylone V GX and I work with Phy nativ transciver for transmit a data at speed 1Gbit on fabric with sfp.

I use with 100MHz local clock and REFCLK 100MHz differential clock (LVDS)

The transciver work and flag of sync_status is '1' but all 4 secoand my flag that seen if data recieve ok ("data_ok") look that the data received wrrong and it is happend when "ctrl detect" not received and I does not know why it is happend if someone can halp me? (Seen picture of signal tap)
Attached Images
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Problems with ibis model for EP2S60 (Stratix II)

October 4, 2017, 4:27 am
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Hello Altera!

I need to simulate my pcb design in Hyperlynx. I have downloaded IBIS model and I cant understand why in the real world pin names are literal (for example A1, A2, etc) while in IBIS model pin names are numeric (for example 1, 2, etc). How to associate them?
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DE0-CV board control panel

October 4, 2017, 7:51 am
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I need to run control panel of DE0-CV cyclone v board but it give me that it can't find quartus installation file although I setup quartus prime 17.0 and I program the fpga on the board using my design through USB-Blaster but when I want to run the control panel it give me this error. I try to download the .sof file that come with control panel first the run .exe but it although give me the same error.

Thanks
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MAX10 CONFIG_SEL Problem

October 4, 2017, 8:35 am
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We have a 1kOhm Pull-Down resistor and an external logic at MAX10 CONFIG_SEL pin to boot two different images dependent of the logical state of CONFIG_SEL. Usually the external logic is tri-stated and the 1kOhm Pull-Down holds the pin low at about 0.1V (knowing that an MAX10 internal pull-up is connected to this pin). Anyway some times Image 1 is booted instead of Image 0. This occurs very seldom, about 1 of 100 power up sequencies.
As it is a battery powered equipment we have an "emergency reset" function which switches off the battery for 400ms (we see that all power rails go down to 0V). In this case the wrong Image is booted very often.
Any idea?
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Use RTL code as library in OpenCL?

October 4, 2017, 9:25 am
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Hi

Altera mentioned that it's possible to include RTL design into OpenCL code as a compiled library.
I can't find documentation about it, I tried looking at the design examples "library1 & 2" and still have no clue on how to do this.
The xml file looks complicated, like the INTERFACE part and what goes to the REQUIREMENTS. And why does it need a CL file that writes the function again if it's including from RTL?

Thank you.
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Quartus main window is blank (Linux)

October 4, 2017, 12:24 pm
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Hi, I attached PNG file of a problem I'm having, I just installed Quartus on my Linux CentOS 7 machine and when I start it, I get just a blank window frame with the title "Quartus Prime Standard Edition". I'm running this on a remote server, using VNC server and Gnome.


System information:
CentOs 7.4.1708
kernel 3.10.0-693.2.2.el7.x86_64

Anyone see anything like this before? I'm new to Quartus and never encountered anything like this before.
Attached Images
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How to compile RTL Module with OpenCL kernel ?

October 4, 2017, 12:44 pm
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Hi,
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ?
The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ?
How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ?
Do you have, please, any documentation about it ?
Thank you.
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Cyclone V Transceiver Backplane Support

October 4, 2017, 3:11 pm
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Hello, my co-worker is designing three boards and a backplane to transfer the data between the three boards. I mentioned that he could use the Cyclone V's embedded transceivers to communicate over the backplane. The backplane will have a length of 8-inches or less. I have not done any designs such as this and wanted to ask the community for help in finding documentation or any comments on backplane support for the Cyclone V. The data rate is very low, we could use something like 1280 Mbps or around that area. If anyone has some experience please share them.

Respectfully,
Joe
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Nios II and Python

October 4, 2017, 8:01 pm
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I am trying to send char bytes from my fpga to a python program, the data bytes are hexadecimal data, and those values will be plotted in a GUI table. The nios code is


unsigned char temp =0xa;
unsigned char temp1 =0xb;
unsigned char temp2 =0xc;
while(1)
{
sendFloat(temp);
sendFloat(temp1);
sendFloat(temp2);
}
return0;
}
void sendFloat( unsigned char n)
{
 char number[20];
 int i=0;
snprintf(number, sizeof(number),"%u", n);
while(i<20){
 IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,number[i]);
delay();
 i++;
}
 IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,'\n');}

The Python code is

import serial
ser= serial.Serial('COM5',baudrate =115200, timeout=1)
while 1:
fpgadata=ser.readline()
print(fpgadata)
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Problem with download

October 5, 2017, 1:34 am
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Hi,

For two days I try to download Intel FPGA SDK for OpenCL from this page:
http://dl.altera.com/opencl/?edition=standard
and I can't do that.

When using Akamai DLM, the downloading always crashes after about 5-20%, goes back to 0%, and I can't do anything. Akamai reinstalling doesn't help. When I try to download file from direct link every browser I try to use gives info, that page cannot be displayed. Developer tools in Chrome can download the .tar file, but after downloading it's 5KB and the archive is broken.

Can anyone help me?
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Verilog coding

October 5, 2017, 6:46 am
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Hi all,

I am just start to learn Verilog and immediately had a problem - please take a look at code - why "repeat (10) does not working?
I was expected a 5 pulse train at every oop pulse - but in simulation the is no changes of pls output at all.
I tried to use for and while condition - same result - no pulse train.

///////////////////////////////////////////////////////////////////////////////////////////////////

module buff_gen (oop,pls);
input oop;
wire oop;

output pls;
reg pls;

initial begin pls = 0; end


always @ (posedge oop)
begin

repeat (10)
begin
#5 pls = ~pls;
end

end

endmodule

////////////////////////////////////////

please tell me what I am doing wrong.

thanks
cicga
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Pin assignment does not show in graphic editor of Quartus II 16.1

October 5, 2017, 8:58 am
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Hello !

I have a strange problem: when I assign pin location to an input or output pin, it works but the assignment does not show in graphic editor. I can swithch on or off in (right click) Show menu but it does not matter.

The same project, opened from a flash drive on another computer shows pin locations (Quartus 13.1). I have lost 2 days of time and tons of nerves but this problem persists. Is there a big in Quartus ii 16.1 ?

I have projects on the same computer that behave normally in Quartus II, but whenever I start a project from anew I am unable to see pin assignments in the Graphic editor.

How to solve this?
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Internal Error : Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_alt

October 5, 2017, 10:13 am
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My design contains several PLL's :
- a PLL to generate the main system clock.
- a PLL for the DDR controller.
- a PLL in a PCIe interface IP.

Recently my builds have been crashing with an internal error :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy

After I do Project->Clean project, the build succeeds.

PLL Usage Summary in the .fit.rpt lists :



DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate_1
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst
CLK_GEN_NETWORK:PLL_CLK_GEN|CLK_GEN_NETWORK_altera _iopll_161_octysbi:iopll_0|altera_iopll:altera_iop ll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst
PCIE_XL_INTERFACE:PCIE_TREETOP|xillybus:xillybus_i ns|pcie_a10_8x: pcie|pcie_reconfig: pcie_reconfig|pcie_reconfig_altera_pcie_a10_hip_16 1_5uv7uhy: pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10 _hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpci e_a10_hip_pllnphy|fpll_g1g2xn:g_pll.g_pll_g12n.fpl l_g1g2xn|altera_xcvr_fpll_a10:fpll_g1g2xn|fpll_ins t


Whats up with the the duplicate PLL's?
Do they cause the internal error?

The target device is Arria 10/10AX115N3F45E2SG
I currently use Quartus 17.02, but the same error occurred in 16.1.2 and 16.0.2.

Full error report :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy
Stack Trace:
0xaccff: EMIF_GEN6_EMIF_SYSTEM::create_emif_phylite_group_c ell() + 0x481 (periph_emif)
0xb3b8b: EMIF_GEN6_EMIF_SYSTEM::create_emif_cells(CDB_ATOM_ NODE*, std::unordered_map<unsigned int, CDB_ATOM_NODE*, STL_HASH_FUNCTOR<unsigned int>, std::equal_to<unsigned int>, std::allocator<std:: pair<unsigned int const, CDB_ATOM_NODE*> > >&) + 0x1ab (periph_emif)
0x833c1: EMIF_GEN6::create_design() + 0x107 (periph_emif)
0x68496: PCC_ENV_IMPL:: perform_op(PCC_ENV::OP) + 0x1f6 (periph_pcc)
0x695a5: PCC_ENV_IMPL::create_design() + 0x1b5 (periph_pcc)
0x698ea: PCC_ENV_IMPL::refresh_design_until_converged(bool) + 0x18a (periph_pcc)
0x69ac1: PCC_ENV_IMPL::refresh(PCC_ENV::CONTEXT, std::string const&, bool, bool) + 0xd1 (periph_pcc)
0x6a485: PCC_ENV_IMPL::load_design() + 0x105 (periph_pcc)
0x955a1: pcc_load_periph_design + 0x71 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x40131: pcc_load_periph_placer + 0x102 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0x539d6: Tcl_EvalEx + 0x16 (tcl8.6)
0x539fd: Tcl_Eval + 0x1d (tcl8.6)
0x1aeb5: atcl_tcl_eval(Tcl_Interp*, std::string const&) + 0x12d (ccl_atcl)
0x34c49: atcl_run_internal_tcl_cmd(Tcl_Interp*, std::string const&, bool) + 0x59 (ccl_atcl)
0x2354c: fit2_fit_plan_init + 0x23c (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x13086: fit2_fit_plan + 0x2ec (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6)
0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6)
0x11ebc: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe)
0x18dcf: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list<std::string, std::allocator<std::string> > const&, bool, bool) + 0x597 (comp_qexe)
0x19d7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x57e (comp_qexe)
0x3e06a: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x1065 (comp_qcu)
0x1c586: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe)
0x3b75: qfit2_main(int, char const**) + 0xc5 (quartus_fit)
0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
0x602c: thr_final_wrapper + 0xc (ccl_thr)
0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
0x1ed1d: __libc_start_main + 0xfd (c.so.6)




End-trace




Executable: quartus
Comment:
None


System Information
Platform: linux64
OS name: CentOS release
OS version: 6


Quartus Prime Information
Address bits: 64
Version: 17.0.2
Build: 602
Edition: Standard Edition
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Install hangs on Fedora 17.0.0.595

October 5, 2017, 8:12 pm
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Quartus Prime Standard Edition Software (Device support not included)2. Quartus Prime Help
3. Intel FPGA SDK for OpenCL
4. DSP Builder
5. ModelSim - Intel FPGA Edition
6. ModelSim - Intel FPGA Starter Edition (Free)
7. Quartus Prime Programmer and Tools
8. FLEXlm License Server Software
" width="15px" height="15px" style="box-sizing: border-box; font-family: IntelClear; border: 0px; vertical-align: middle; font-size: 15.4px;">Quartus-17.0.0.595-linux.tar
Size: 5.6 GB MD5: E3A3780FF6F0C1009AAA68B9B7AB4EB5

My check

e3a3780ff6f0c1009aaa68b9b7ab4eb5 Quartus-17.0.0.595-linux.tar





What happens is when i click on install everything goes good until the end of the help then it just hangs. In the dialog that fires off the for the help and just sits there. See the attached image. I'm not sure what isn't getting triggered.

Looking in journalctl this is at about the same time.

Oct 05 22:44:30 efa-puter zenity[12553]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:44:38 efa-puter zenity[12584]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:45:04 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00d8c (Question).
Oct 05 22:45:15 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00e58 (Error).
Oct 05 22:45:42 efa-puter zenity[12839]: GtkDialog mapped without a transient parent. This is discouraged.
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