Is it common to run SDRAM, SRAM and other memory controllers at a higher frequency than the main design, perhaps that is not integer multiple of the system frequency? This shall require use of clock crossing FIFO.
↧
is it common to run memory interface at a higher speed than the design?
↧
Problems with ibis model for EP2S60 (Stratix II)
Hello Altera!
I need to simulate my pcb design in Hyperlynx. I have downloaded IBIS model and I cant understand why in the real world pin names are literal (for example A1, A2, etc) while in IBIS model pin names are numeric (for example 1, 2, etc). How to associate them?
I need to simulate my pcb design in Hyperlynx. I have downloaded IBIS model and I cant understand why in the real world pin names are literal (for example A1, A2, etc) while in IBIS model pin names are numeric (for example 1, 2, etc). How to associate them?
↧
↧
DE0-CV board control panel
I need to run control panel of DE0-CV cyclone v board but it give me that it can't find quartus installation file although I setup quartus prime 17.0 and I program the fpga on the board using my design through USB-Blaster but when I want to run the control panel it give me this error. I try to download the .sof file that come with control panel first the run .exe but it although give me the same error.
Thanks
Thanks
↧
MAX10 CONFIG_SEL Problem
We have a 1kOhm Pull-Down resistor and an external logic at MAX10 CONFIG_SEL pin to boot two different images dependent of the logical state of CONFIG_SEL. Usually the external logic is tri-stated and the 1kOhm Pull-Down holds the pin low at about 0.1V (knowing that an MAX10 internal pull-up is connected to this pin). Anyway some times Image 1 is booted instead of Image 0. This occurs very seldom, about 1 of 100 power up sequencies.
As it is a battery powered equipment we have an "emergency reset" function which switches off the battery for 400ms (we see that all power rails go down to 0V). In this case the wrong Image is booted very often.
Any idea?
As it is a battery powered equipment we have an "emergency reset" function which switches off the battery for 400ms (we see that all power rails go down to 0V). In this case the wrong Image is booted very often.
Any idea?
↧
Use RTL code as library in OpenCL?
Hi
Altera mentioned that it's possible to include RTL design into OpenCL code as a compiled library.
I can't find documentation about it, I tried looking at the design examples "library1 & 2" and still have no clue on how to do this.
The xml file looks complicated, like the INTERFACE part and what goes to the REQUIREMENTS. And why does it need a CL file that writes the function again if it's including from RTL?
Thank you.
Altera mentioned that it's possible to include RTL design into OpenCL code as a compiled library.
I can't find documentation about it, I tried looking at the design examples "library1 & 2" and still have no clue on how to do this.
The xml file looks complicated, like the INTERFACE part and what goes to the REQUIREMENTS. And why does it need a CL file that writes the function again if it's including from RTL?
Thank you.
↧
↧
Quartus main window is blank (Linux)
Hi, I attached PNG file of a problem I'm having, I just installed Quartus on my Linux CentOS 7 machine and when I start it, I get just a blank window frame with the title "Quartus Prime Standard Edition". I'm running this on a remote server, using VNC server and Gnome.
System information:
CentOs 7.4.1708
kernel 3.10.0-693.2.2.el7.x86_64
Anyone see anything like this before? I'm new to Quartus and never encountered anything like this before.
EDIT: I think Gnome is the problem, tried starting up a new vnc display using kde and it worked. If anyone knows how to get this to work with Gnome, please comment!
System information:
CentOs 7.4.1708
kernel 3.10.0-693.2.2.el7.x86_64
Anyone see anything like this before? I'm new to Quartus and never encountered anything like this before.
EDIT: I think Gnome is the problem, tried starting up a new vnc display using kde and it worked. If anyone knows how to get this to work with Gnome, please comment!
↧
How to compile RTL Module with OpenCL kernel ?
Hi,
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ?
The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ?
How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ?
Do you have, please, any documentation about it ?
Thank you.
I'm looking for documentation about codesign RTL module with OpenCL kernel. How to transform my VHDL or verilog to XML ?
The Design example "OpenCL Library" (Advanced kernel code) show an example with RTL module and XML file ?
How to compile RTL module with Kernel Opencl, How to write XML file or how to trnasform xml from verilog ?
Do you have, please, any documentation about it ?
Thank you.
↧
Cyclone V Transceiver Backplane Support
Hello, my co-worker is designing three boards and a backplane to transfer the data between the three boards. I mentioned that he could use the Cyclone V's embedded transceivers to communicate over the backplane. The backplane will have a length of 8-inches or less. I have not done any designs such as this and wanted to ask the community for help in finding documentation or any comments on backplane support for the Cyclone V. The data rate is very low, we could use something like 1280 Mbps or around that area. If anyone has some experience please share them.
Respectfully,
Joe
Respectfully,
Joe
↧
Nios II and Python
I am trying to send char bytes from my fpga to a python program, the data bytes are hexadecimal data, and those values will be plotted in a GUI table. The nios code is
unsigned char temp =0xa;
unsigned char temp1 =0xb;
unsigned char temp2 =0xc;
while(1)
{
sendFloat(temp);
sendFloat(temp1);
sendFloat(temp2);
}
return0;
}
void sendFloat( unsigned char n)
{
char number[20];
int i=0;
snprintf(number, sizeof(number),"%u", n);
while(i<20){
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,number[i]);
delay();
i++;
}
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,'\n');}
The Python code is
import serial
ser= serial.Serial('COM5',baudrate =115200, timeout=1)
while 1:
fpgadata=ser.readline()
print(fpgadata)
unsigned char temp =0xa;
unsigned char temp1 =0xb;
unsigned char temp2 =0xc;
while(1)
{
sendFloat(temp);
sendFloat(temp1);
sendFloat(temp2);
}
return0;
}
void sendFloat( unsigned char n)
{
char number[20];
int i=0;
snprintf(number, sizeof(number),"%u", n);
while(i<20){
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,number[i]);
delay();
i++;
}
IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,'\n');}
The Python code is
import serial
ser= serial.Serial('COM5',baudrate =115200, timeout=1)
while 1:
fpgadata=ser.readline()
print(fpgadata)
↧
↧
Problem with download
Hi,
For two days I try to download Intel FPGA SDK for OpenCL from this page:
http://dl.altera.com/opencl/?edition=standard
and I can't do that.
When using Akamai DLM, the downloading always crashes after about 5-20%, goes back to 0%, and I can't do anything. Akamai reinstalling doesn't help. When I try to download file from direct link every browser I try to use gives info, that page cannot be displayed. Developer tools in Chrome can download the .tar file, but after downloading it's 5KB and the archive is broken.
Can anyone help me?
For two days I try to download Intel FPGA SDK for OpenCL from this page:
http://dl.altera.com/opencl/?edition=standard
and I can't do that.
When using Akamai DLM, the downloading always crashes after about 5-20%, goes back to 0%, and I can't do anything. Akamai reinstalling doesn't help. When I try to download file from direct link every browser I try to use gives info, that page cannot be displayed. Developer tools in Chrome can download the .tar file, but after downloading it's 5KB and the archive is broken.
Can anyone help me?
↧
Verilog coding
Hi all,
I am just start to learn Verilog and immediately had a problem - please take a look at code - why "repeat (10) does not working?
I was expected a 5 pulse train at every oop pulse - but in simulation the is no changes of pls output at all.
I tried to use for and while condition - same result - no pulse train.
///////////////////////////////////////////////////////////////////////////////////////////////////
module buff_gen (oop,pls);
input oop;
wire oop;
output pls;
reg pls;
initial begin pls = 0; end
always @ (posedge oop)
begin
repeat (10)
begin
#5 pls = ~pls;
end
end
endmodule
////////////////////////////////////////
please tell me what I am doing wrong.
thanks
cicga
I am just start to learn Verilog and immediately had a problem - please take a look at code - why "repeat (10) does not working?
I was expected a 5 pulse train at every oop pulse - but in simulation the is no changes of pls output at all.
I tried to use for and while condition - same result - no pulse train.
///////////////////////////////////////////////////////////////////////////////////////////////////
module buff_gen (oop,pls);
input oop;
wire oop;
output pls;
reg pls;
initial begin pls = 0; end
always @ (posedge oop)
begin
repeat (10)
begin
#5 pls = ~pls;
end
end
endmodule
////////////////////////////////////////
please tell me what I am doing wrong.
thanks
cicga
↧
Pin assignment does not show in graphic editor of Quartus II 16.1
Hello !
I have a strange problem: when I assign pin location to an input or output pin, it works but the assignment does not show in graphic editor. I can swithch on or off in (right click) Show menu but it does not matter.
The same project, opened from a flash drive on another computer shows pin locations (Quartus 13.1). I have lost 2 days of time and tons of nerves but this problem persists. Is there a big in Quartus ii 16.1 ?
I have projects on the same computer that behave normally in Quartus II, but whenever I start a project from anew I am unable to see pin assignments in the Graphic editor.
How to solve this?
I have a strange problem: when I assign pin location to an input or output pin, it works but the assignment does not show in graphic editor. I can swithch on or off in (right click) Show menu but it does not matter.
The same project, opened from a flash drive on another computer shows pin locations (Quartus 13.1). I have lost 2 days of time and tons of nerves but this problem persists. Is there a big in Quartus ii 16.1 ?
I have projects on the same computer that behave normally in Quartus II, but whenever I start a project from anew I am unable to see pin assignments in the Graphic editor.
How to solve this?
↧
Internal Error : Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_alt
My design contains several PLL's :
- a PLL to generate the main system clock.
- a PLL for the DDR controller.
- a PLL in a PCIe interface IP.
Recently my builds have been crashing with an internal error :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy
After I do Project->Clean project, the build succeeds.
PLL Usage Summary in the .fit.rpt lists :
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate_1
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst
CLK_GEN_NETWORK:PLL_CLK_GEN|CLK_GEN_NETWORK_altera _iopll_161_octysbi:iopll_0|altera_iopll:altera_iop ll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst
PCIE_XL_INTERFACE:PCIE_TREETOP|xillybus:xillybus_i ns|pcie_a10_8x: pcie|pcie_reconfig: pcie_reconfig|pcie_reconfig_altera_pcie_a10_hip_16 1_5uv7uhy: pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10 _hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpci e_a10_hip_pllnphy|fpll_g1g2xn:g_pll.g_pll_g12n.fpl l_g1g2xn|altera_xcvr_fpll_a10:fpll_g1g2xn|fpll_ins t
Whats up with the the duplicate PLL's?
Do they cause the internal error?
The target device is Arria 10/10AX115N3F45E2SG
I currently use Quartus 17.02, but the same error occurred in 16.1.2 and 16.0.2.
Full error report :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy
Stack Trace:
0xaccff: EMIF_GEN6_EMIF_SYSTEM::create_emif_phylite_group_c ell() + 0x481 (periph_emif)
0xb3b8b: EMIF_GEN6_EMIF_SYSTEM::create_emif_cells(CDB_ATOM_ NODE*, std::unordered_map<unsigned int, CDB_ATOM_NODE*, STL_HASH_FUNCTOR<unsigned int>, std::equal_to<unsigned int>, std::allocator<std:: pair<unsigned int const, CDB_ATOM_NODE*> > >&) + 0x1ab (periph_emif)
0x833c1: EMIF_GEN6::create_design() + 0x107 (periph_emif)
0x68496: PCC_ENV_IMPL:: perform_op(PCC_ENV::OP) + 0x1f6 (periph_pcc)
0x695a5: PCC_ENV_IMPL::create_design() + 0x1b5 (periph_pcc)
0x698ea: PCC_ENV_IMPL::refresh_design_until_converged(bool) + 0x18a (periph_pcc)
0x69ac1: PCC_ENV_IMPL::refresh(PCC_ENV::CONTEXT, std::string const&, bool, bool) + 0xd1 (periph_pcc)
0x6a485: PCC_ENV_IMPL::load_design() + 0x105 (periph_pcc)
0x955a1: pcc_load_periph_design + 0x71 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x40131: pcc_load_periph_placer + 0x102 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0x539d6: Tcl_EvalEx + 0x16 (tcl8.6)
0x539fd: Tcl_Eval + 0x1d (tcl8.6)
0x1aeb5: atcl_tcl_eval(Tcl_Interp*, std::string const&) + 0x12d (ccl_atcl)
0x34c49: atcl_run_internal_tcl_cmd(Tcl_Interp*, std::string const&, bool) + 0x59 (ccl_atcl)
0x2354c: fit2_fit_plan_init + 0x23c (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x13086: fit2_fit_plan + 0x2ec (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6)
0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6)
0x11ebc: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe)
0x18dcf: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list<std::string, std::allocator<std::string> > const&, bool, bool) + 0x597 (comp_qexe)
0x19d7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x57e (comp_qexe)
0x3e06a: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x1065 (comp_qcu)
0x1c586: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe)
0x3b75: qfit2_main(int, char const**) + 0xc5 (quartus_fit)
0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
0x602c: thr_final_wrapper + 0xc (ccl_thr)
0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
0x1ed1d: __libc_start_main + 0xfd (c.so.6)
End-trace
Executable: quartus
Comment:
None
System Information
Platform: linux64
OS name: CentOS release
OS version: 6
Quartus Prime Information
Address bits: 64
Version: 17.0.2
Build: 602
Edition: Standard Edition
- a PLL to generate the main system clock.
- a PLL for the DDR controller.
- a PLL in a PCIe interface IP.
Recently my builds have been crashing with an internal error :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy
After I do Project->Clean project, the build succeeds.
PLL Usage Summary in the .fit.rpt lists :
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate_1
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate
DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_ emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_ nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_1 61_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst
CLK_GEN_NETWORK:PLL_CLK_GEN|CLK_GEN_NETWORK_altera _iopll_161_octysbi:iopll_0|altera_iopll:altera_iop ll_i|twentynm_iopll_ip:twentynm_pll|iopll_inst
PCIE_XL_INTERFACE:PCIE_TREETOP|xillybus:xillybus_i ns|pcie_a10_8x: pcie|pcie_reconfig: pcie_reconfig|pcie_reconfig_altera_pcie_a10_hip_16 1_5uv7uhy: pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10 _hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpci e_a10_hip_pllnphy|fpll_g1g2xn:g_pll.g_pll_g12n.fpl l_g1g2xn|altera_xcvr_fpll_a10:fpll_g1g2xn|fpll_ins t
Whats up with the the duplicate PLL's?
Do they cause the internal error?
The target device is Arria 10/10AX115N3F45E2SG
I currently use Quartus 17.02, but the same error occurred in 16.1.2 and 16.0.2.
Full error report :
Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645
Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy
Stack Trace:
0xaccff: EMIF_GEN6_EMIF_SYSTEM::create_emif_phylite_group_c ell() + 0x481 (periph_emif)
0xb3b8b: EMIF_GEN6_EMIF_SYSTEM::create_emif_cells(CDB_ATOM_ NODE*, std::unordered_map<unsigned int, CDB_ATOM_NODE*, STL_HASH_FUNCTOR<unsigned int>, std::equal_to<unsigned int>, std::allocator<std:: pair<unsigned int const, CDB_ATOM_NODE*> > >&) + 0x1ab (periph_emif)
0x833c1: EMIF_GEN6::create_design() + 0x107 (periph_emif)
0x68496: PCC_ENV_IMPL:: perform_op(PCC_ENV::OP) + 0x1f6 (periph_pcc)
0x695a5: PCC_ENV_IMPL::create_design() + 0x1b5 (periph_pcc)
0x698ea: PCC_ENV_IMPL::refresh_design_until_converged(bool) + 0x18a (periph_pcc)
0x69ac1: PCC_ENV_IMPL::refresh(PCC_ENV::CONTEXT, std::string const&, bool, bool) + 0xd1 (periph_pcc)
0x6a485: PCC_ENV_IMPL::load_design() + 0x105 (periph_pcc)
0x955a1: pcc_load_periph_design + 0x71 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x40131: pcc_load_periph_placer + 0x102 (periph_pcc)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0x539d6: Tcl_EvalEx + 0x16 (tcl8.6)
0x539fd: Tcl_Eval + 0x1d (tcl8.6)
0x1aeb5: atcl_tcl_eval(Tcl_Interp*, std::string const&) + 0x12d (ccl_atcl)
0x34c49: atcl_run_internal_tcl_cmd(Tcl_Interp*, std::string const&, bool) + 0x59 (ccl_atcl)
0x2354c: fit2_fit_plan_init + 0x23c (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x13086: fit2_fit_plan + 0x2ec (comp_fit2)
0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
0x536e7: TclEvalEx + 0x947 (tcl8.6)
0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6)
0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6)
0x11ebc: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe)
0x18dcf: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list<std::string, std::allocator<std::string> > const&, bool, bool) + 0x597 (comp_qexe)
0x19d7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x57e (comp_qexe)
0x3e06a: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x1065 (comp_qcu)
0x1c586: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe)
0x3b75: qfit2_main(int, char const**) + 0xc5 (quartus_fit)
0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
0x602c: thr_final_wrapper + 0xc (ccl_thr)
0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
0x1ed1d: __libc_start_main + 0xfd (c.so.6)
End-trace
Executable: quartus
Comment:
None
System Information
Platform: linux64
OS name: CentOS release
OS version: 6
Quartus Prime Information
Address bits: 64
Version: 17.0.2
Build: 602
Edition: Standard Edition
↧
↧
Install hangs on Fedora 17.0.0.595
Quartus Prime Standard Edition Software (Device support not included)![]()
2. Quartus Prime Help
3. Intel FPGA SDK for OpenCL
4. DSP Builder
5. ModelSim - Intel FPGA Edition
6. ModelSim - Intel FPGA Starter Edition (Free)
7. Quartus Prime Programmer and Tools
8. FLEXlm License Server Software
" width="15px" height="15px" style="box-sizing: border-box; font-family: IntelClear; border: 0px; vertical-align: middle; font-size: 15.4px;">Quartus-17.0.0.595-linux.tar
Size: 5.6 GB MD5: E3A3780FF6F0C1009AAA68B9B7AB4EB5
My check
e3a3780ff6f0c1009aaa68b9b7ab4eb5 Quartus-17.0.0.595-linux.tar
What happens is when i click on install everything goes good until the end of the help then it just hangs. In the dialog that fires off the for the help and just sits there. See the attached image. I'm not sure what isn't getting triggered.
Looking in journalctl this is at about the same time.
Oct 05 22:44:30 efa-puter zenity[12553]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:44:38 efa-puter zenity[12584]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:45:04 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00d8c (Question).
Oct 05 22:45:15 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00e58 (Error).
Oct 05 22:45:42 efa-puter zenity[12839]: GtkDialog mapped without a transient parent. This is discouraged.
2. Quartus Prime Help3. Intel FPGA SDK for OpenCL
4. DSP Builder
5. ModelSim - Intel FPGA Edition
6. ModelSim - Intel FPGA Starter Edition (Free)
7. Quartus Prime Programmer and Tools
8. FLEXlm License Server Software
" width="15px" height="15px" style="box-sizing: border-box; font-family: IntelClear; border: 0px; vertical-align: middle; font-size: 15.4px;">Quartus-17.0.0.595-linux.tar
Size: 5.6 GB MD5: E3A3780FF6F0C1009AAA68B9B7AB4EB5
My check
e3a3780ff6f0c1009aaa68b9b7ab4eb5 Quartus-17.0.0.595-linux.tar
What happens is when i click on install everything goes good until the end of the help then it just hangs. In the dialog that fires off the for the help and just sits there. See the attached image. I'm not sure what isn't getting triggered.
Looking in journalctl this is at about the same time.
Oct 05 22:44:30 efa-puter zenity[12553]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:44:38 efa-puter zenity[12584]: GtkDialog mapped without a transient parent. This is discouraged.
Oct 05 22:45:04 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00d8c (Question).
Oct 05 22:45:15 efa-puter org.gnome.Shell.desktop[1763]: Window manager warning: Invalid WM_TRANSIENT_FOR window 0x2c00004 specified for 0x2c00e58 (Error).
Oct 05 22:45:42 efa-puter zenity[12839]: GtkDialog mapped without a transient parent. This is discouraged.
↧
Strange effects with NIOS in design
Hi everyone,
For the first time I am using a NIOS soft core in one of my designs. Generating the core was relatively easy but now I'm facing some strange effects when I integrate the core into my design.
In my design, I'm using four bidirectional pins for two separate I2C buses. Without the NIOS in the design everything works fine and I'm able to communicate with the devices on I2C bus, but as soon as I add the core to the design, two out of four I2C pins are not usable anymore. They remain on high state even if I try to drive them low. So far, the NIOS was only added to the design, it was not yet connected to one of these I2C pins.
Does anyone have an idea what could cause this problem and how to resolve it?
For the first time I am using a NIOS soft core in one of my designs. Generating the core was relatively easy but now I'm facing some strange effects when I integrate the core into my design.
In my design, I'm using four bidirectional pins for two separate I2C buses. Without the NIOS in the design everything works fine and I'm able to communicate with the devices on I2C bus, but as soon as I add the core to the design, two out of four I2C pins are not usable anymore. They remain on high state even if I try to drive them low. So far, the NIOS was only added to the design, it was not yet connected to one of these I2C pins.
Does anyone have an idea what could cause this problem and how to resolve it?
↧
Asynchronous FIFO
Hi Experts
Can someone help me understand how this Asynchronous FIFO operates..
Thanks in advanced! :)
Can someone help me understand how this Asynchronous FIFO operates..
Thanks in advanced! :)
↧
is it common to run memory interface at a higher speed than the design?
Is it common to run SDRAM, SRAM and other memory controllers at a higher frequency than the main design, perhaps that is not integer multiple of the system frequency? This shall require use of clock crossing FIFO.
↧
↧
Timing violations on internal nodes - how to fix them ?
Hello,
TimeQuest Analyzer reported 63 "Setup" violations, and all of them are located on internal nodes.
Does exist some strategy to fix internal nodes timing violations, e.g. add some constraints in .sdc file ?
Thanks.
TimeQuest Analyzer reported 63 "Setup" violations, and all of them are located on internal nodes.
Does exist some strategy to fix internal nodes timing violations, e.g. add some constraints in .sdc file ?
Thanks.
↧
Quartus Prime 17 not launching.
I want to put QP17 on a linux machine.
I installed QP17 lite linux version on a linux machine running Ubuntu.
There is a Quartus Prime 17.0 lite icon on the screen.
When I click on the icon, the program starts to load for about 10s and stops.
I installed QP17 lite linux version on a linux machine running Ubuntu.
There is a Quartus Prime 17.0 lite icon on the screen.
When I click on the icon, the program starts to load for about 10s and stops.
↧
FPGA to SDRAM AXI Transfer
Hello,
I'm doing a project with Arria V SoC using the HPS and FPGA parts. In the FPGA, I have a custom IP with AXI Master interface on it.
This IP should read and write from/to the SDRAM directly. However, I can only do read operation! The write operation does not work.
The data in SDRAM is provided by HPS (running Linux). For now, I'm using /dev/mem to write the data to the SDRAM.
Using the same method, I found that the data is never written from FPGA.
1. Can you help me with this issue? Anyone has already done a work using AXI and SDRAM?
2. In Qsys, my AXI master should be connected to the SDRAM, right? Did I do some mistake? I connect it to f2h_sdram0_data, not f2h_axi_slave on hps_0.
3. Is there any configuration that I need to do in the AXI to perform read and write?
Thank you so much for your help.
I'm doing a project with Arria V SoC using the HPS and FPGA parts. In the FPGA, I have a custom IP with AXI Master interface on it.
This IP should read and write from/to the SDRAM directly. However, I can only do read operation! The write operation does not work.
The data in SDRAM is provided by HPS (running Linux). For now, I'm using /dev/mem to write the data to the SDRAM.
Using the same method, I found that the data is never written from FPGA.
1. Can you help me with this issue? Anyone has already done a work using AXI and SDRAM?
2. In Qsys, my AXI master should be connected to the SDRAM, right? Did I do some mistake? I connect it to f2h_sdram0_data, not f2h_axi_slave on hps_0.
3. Is there any configuration that I need to do in the AXI to perform read and write?
Thank you so much for your help.
↧