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Video memory scheme?

October 6, 2017, 10:27 am
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Please tell me where I can find more on this scheme. I tried to copy it using MaxPlusII program, but the only counter I found in libraries was LPM_COUNTER, not containing "cout" output, which could give a signal when the counter overflows (I could change LPM_MODULUS for this goal).
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Implementing parallel reduction/ finding maximum algorithm on FPGA?

October 6, 2017, 3:15 pm
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Hi
I'm trying to implement parallel algorithms from GPU to FPGA,
one kernel is finding maximum using parallel reduction but obviously deploying it on FPGA will be resource wasting since half of the hardware would be idle after the first stage.
I'm using multiple linear search and it runs at a reasonable speed and doesn't take tons of resource. But one would think people have came up with cleaver algorithm for finding maximum/minimum on FPGA since it's such a common needed function.
I did some searching but most documents I found are about implementing linear search in RTL.
Anyone have idea on how this can be done efficiently? Thanks!
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Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

October 7, 2017, 7:59 am
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I am attempting to instantiate a signal tap core using the megafunction flow. Quartus generates the IP but when I instantiate it in my project and compile I get the following error.

Error(13785): VHDL Use Clause error at signal_tap.vhd(47): design library "altera_signaltap_ii_logic_analyzer_170" does not contain primary unit "sld_signaltap"

It works fine using .stp files but this approach doesn't fit into the flow that I'm attempting to use.
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DE0-CV programming error

October 7, 2017, 8:19 am
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I am using the DE0_CV_PS2_DEMO project from Terasic. I try to program the device and I get:
Info (209060): Started Programmer operation at Sat Oct 07 07:59:38 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 07:59:38 2017
Info (209060): Started Programmer operation at Sat Oct 07 08:08:05 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 08:08:05 2017
Info (209060): Started Programmer operation at Sat Oct 07 08:10:11 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 08:10:11 2017

Does anyone know how I can fix this?

Y-
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Adding signal tap to OpenCL RTL library

October 7, 2017, 9:38 am
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I've been attempting to add signal tap to an RTL library module for debugging. So far I've been unsuccessful in doing so. My approach has been to generate synthesis files for signal tap using the megafunction tool. The aoc compile ultimately fails due to accompanying modules not being brought into the project. Is there some way to do this?
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Cannot login properly to myAltera

October 7, 2017, 3:21 pm
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Hi,

I had a myAltera account for a few years but I can no longer log in with it. Is this a temporary issue? I had a variety of outcomes, including:

* Basic "Authentication failed" messages
* Then after clearing cookies and retrying on Mac, eventually got a login that took me to "myAltera Home" but clicking "Manage profile" link went nowhere (was my account not properly migrated to SSO or something?)
* In this crippled login I also could not download Quartus, getting an Authentication failed JSON message
* I could not reset password (nothing appeared to happen, it left me on the form).

Basically every single feature and page related to login and authentication failed to work.

There is also a broken link to password reset, on an account help page.

--Toby
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Quartus II and Altera Usb Blaster

October 8, 2017, 10:50 am
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Hi,

I'm using EPM3064 device and Altera Usb Blaster.

I'm looking free licence and minimum installation size Quartus II. (maybe old versions)

Which version can I download?
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Teraisc DE0-CV (Cyclone V) programming error

October 8, 2017, 11:25 am
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I am using the DE0_CV_PS2_DEMO project from Terasic. I try to program the device and I get:
Info (209060): Started Programmer operation at Sat Oct 07 07:59:38 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 07:59:38 2017
Info (209060): Started Programmer operation at Sat Oct 07 08:08:05 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 08:08:05 2017
Info (209060): Started Programmer operation at Sat Oct 07 08:10:11 2017
Error (209015): Can't configure device. Expected JTAG ID code 0x02B050DD for device 1, but found JTAG ID code 0x020F20DD. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Sat Oct 07 08:10:11 2017

Does anyone know how I can fix this?

Y-
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MSGDMA transfer irregularities - Cyclone 5

October 8, 2017, 2:32 pm
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Hi,

I have a hybrid system where an MSGDMA MM-ST reads data from DDR3 SDRAM to a custom made component on the FPGA that filters the data.
Simultaneously another MSGDMA ST-MM reads the output back to the DDR3 SDRAM.
They each use a port of the fpga2SDRam bridge. The whole system (including bridges) works at 100 MHz.

My problem is with the DMA writing back the data to SDRAM. If the quantity to transfer is large, it sometimes truncates or even reorders data as
it is writing it back !

Is this normal ? Are there any solutions to this ?

Thank you in advance
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project compilation is taking forever to finish

October 8, 2017, 6:45 pm
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Currently I am working on an openCL project. It works in simulation, but when I compiled for hardware using Quartus, it could not finish even with a whole weekend! (it's estimated to consume 76% DSP and 78% BRAM) Could the reason be that the generated verilog file is not synthesizable?
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OpenCL project compilation is taking forever to finish

October 8, 2017, 6:48 pm
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Currently I am working on an openCL project. It works in simulation, but when I compiled for hardware using Quartus II on Arria 10 soc, it could not finish even with a whole weekend! (it's estimated to consume 76% DSP and 78% BRAM) Could the reason be that the generated verilog file is not synthesizable?
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Altera DE2 and OpenCL

October 8, 2017, 8:00 pm
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HI, I am a beginner to OpenCL on FPGAs. I got a DE2 development and Education Board from my friend.
As far as i know, this board is not the preferred board for OpenCL development.
Could anyone please tell me whether the board supports OpenCL SDK ?
And where can i get the list of board which support OpenCL?
Thank You
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Behaviour of MAX10 PLL output during reset, PFD disable and lock-loss

October 9, 2017, 12:59 am
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As the title suggests I am interested in the behaviour of the PLL output clock of the Altera/Intel MAX10 during the following edge cases:

  • reset (areset = '1')
  • phase-frequency-detector disable (pfdena = '0')
  • lock-loss (areset = '0', pfdena = '1', locked = '0')


The simulation model generated by the Quartus MegaWizard simply outputs 'X' immediately (reset and PFD dsiable) or after some clock cycles (lock-loss).

However, at least when the PFD is disabled, the sparse documentation suggests that the output clock should continue toggling with the last locked frequency while slowly drifting away towards lower frequencies. Moreover, since the documentation explcitly states that the PLL output clocks have no enable, my understanding is that the output clock is in fact toggling all the time, except when the PLL (and its output counter) is held in reset.

Can someone comment on this or possibly check this out on some development board? (my board is still in shipment...)
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Altera MAX10 enable clock-buffer primitives without synchronization?

October 9, 2017, 1:02 am
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Irrespective of the relative evil of gating clocks in FPGAs my understanding was that one should synchronize the enable signal to the clock being gated by means of a flip-flop chain.


However, while studying the documentation for the MAX10 device I stumbled over the following section: Clock Enable Signals where the figures 5 and 6 seem to indicate that no synchronization seems to be necessary.









Do I miss something?

Moreover, how should I constrain a gated clock?
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Is "phase shift" or "delay" a constant whatever the frequency is?

October 9, 2017, 2:35 am
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Hello,

I'm working on a DE0-Nano and I'm trying to control the SDRAM chip located one DE0 board.
After reading a few tutorial, it seems DRAM_CLK signal needs to be delayed by 3 ns.
It is said that "the clock skew depends on physical characteristics of the DE0-Nano board" and that "it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds". (source -> ftp://ftp.altera.com/up/pub/Altera_M..._the_SDRAM.pdf, chapter 7 - p11)

My question is:
Is that delay a constant whatever clock frequency is?
Othewrwise, I guess the phase shift needs to be kept as a constant.

So in the control of my PLL should I specify:
-> phase shift = -54 deg (then delay = 3ns@50MHz, 1.5ns@100MHz, 1.05ns@143MHz)
OR
-> clock delay = 3 ns (then phase shift = -54deg@50MHz, -108deg@100MHz, -154.4deg@143MHz)
?

If anyone also know the physical reasons, I would be please to hear it.

Thanks for you help,

Jean
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Building Quartus16.1 files on Quartus 16.0

October 9, 2017, 3:30 am
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Hi,

So, I m working on top of a third party HDL framework, which is written specifically to be build on Quartus 16.1. It uses some of quartus IPs, (AlteraNative PHY just to name one, generated with Quartus 16.1). The build script organizes all these IPs and other design files, to make necessary quartus files(including qsf file and qpf files) and builds the same.

So my question specifically is,

1) Does building a project with QIPs generated and constrained for Quartus 16.1, cause timing closure to be difficult, building with 16.0?.

The reason for the question, is lack of license support for 16.1, and hence I m evaluating the need for license upgrade, and to conclude that the difference in the quartus versions could be a reason for the timing violation(The same design had easy timing closure with previous version of framework which was constrained for a previous version of Quartus).

Thanks in advance
Jeebu
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autorun kernels not starting in 16.x

October 9, 2017, 3:51 am
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Hi.

When compiling a project with several autorun kernels on a 16.x version of the SDK the emulation will only start some them.
On a 17.x SDK version all of them are started in emulation.

All of them are single work items and declared as follows:
Code:
__attribute__((max_global_work_dim(0)))
__attribute__((autorun))
__kernel void ${NAME}() {...}
Are there some constraints about the number or order of kernels I am not aware of?

I have to use the 16.x SDK for the hardware platform my project runs on and I'm not sure if testing emulation on 17.x and then creating hardware with 16.x is the best way to handle this.

Regards
Julius Roob
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How To do 90' shift alignment with Data and wrt out_Clock in ALT_LVDS TX ip.

October 9, 2017, 5:12 am
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Hi all,

I'm Lalith , Im using ALT lvds TX Ip (7 bit serialisation , 329 Mbps line rate ) in my design with cyclone 4 device. integration of IP is done but as per my other side device . I need total 90 degree shift with output data and out clock . but Ip o/p is at 45 degree shift only .

how to shift my Tx_Out data by 45' extra (total I need 90') with respective Tx_out_clk (from +'ve edge) . ??

attachments : simulation window Screen shot.

Thanks in advance
Lalith
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sof file not updated

October 9, 2017, 6:58 am
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Hello everyone,
I have a custom pcb board with MAX 10 fpga inside. I tried to include basic nios program using hello world template into the system and compile the design. The compilation was done successfully, but the sof file was not updated. It seems to happen whenever I include the nios program into the system, because when I tried to compile the design without the nios program the sof file seems to be updated just fine. For information, I used Quartus Prime Lite Edition as my software.

Any reason as to why this might happen?
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Altera Avalon I2C(Master) Core not working for Cyclone V?

October 9, 2017, 9:06 am
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I am working on a Cyclone V FPGA project. I put the Altera Avalon I2C(Master) Core in my design (as a Qsys component). However, I just noticed that Cyclone V is not listed as supported devices in the IP core datasheet (G-01085,Re 201.05.08).


Supported Devices:

• Arria 10 GX

• Cyclone IV E

• Cyclone 10 LP

• Cyclone 10 GX

Anybody know if the document is right on the supported devices?

Thanks
Q Xiang



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