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msgdma st to MM nios code implementation

October 9, 2017, 12:36 pm
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Hi all-

I am having an issues getting a stream to memory msgdma working. I posted the code below. Can anyone point out where a problem may exist. Thanks!

#include <stdio.h>

// DMA transfer definitions
#include <altera_msgdma_descriptor_regs.h>
#include <altera_msgdma_csr_regs.h>
#include <altera_msgdma.h>

#define BUFFER_A 0x40000000 // SDRAM Buffer A address

// Modular Scatter-Gather DMA Globals
alt_msgdma_dev *DATA_DMA_A;
alt_msgdma_standard_descriptor *DATA_DMA_A_desc = &DATA_DMA_A_desc;

// DMA variables
alt_u32 *DMA_write_addr_ptr_A; // Pointer for DMA A transfer write address
alt_u32 DMA_write_addr_A; // DMA A transfer write address

// Declare functions
void DATA_DMA_A_callback_function(void* context);

// Configure DMA A for next transfer
void DATA_DMA_A_callback_function(void* context) {
alt_msgdma_construct_standard_st_to_mm_descriptor ( DATA_DMA_A,
DATA_DMA_A_desc, DMA_write_addr_ptr_A, dma_len_bytes,
ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE _IRQ_MASK);
alt_msgdma_standard_descriptor_async_transfer(DATA _DMA_A, DATA_DMA_A_desc);

IOWR_ALTERA_AVALON_PIO_DATA(NIOS_DATA1_READY_BASE, 1);
IOWR_ALTERA_AVALON_PIO_DATA(NIOS_DATA1_READY_BASE, 0);
}

int main() {

// Open the streaming scatter-gather DMA controllers
DATA_DMA_A = alt_msgdma_open("/dev/data1_msgdma_csr");
if(DATA_DMA_A == NULL)
printf("Could not open the mSG-DMA1\n");

// Configure DMA callback functions
alt_msgdma_register_callback(DATA_DMA_A, DATA_DMA_A_callback_function, ALTERA_MSGDMA_CSR_GLOBAL_INTERRUPT_MASK, NULL);

// Configure the DMA write address
DMA_write_addr_A = (alt_u32) BUFFER_A ;
DMA_write_addr_ptr_A = (alt_u32*)(DMA_write_addr_A);

// Construct the DMA descriptors
alt_msgdma_construct_standard_st_to_mm_descriptor ( DATA_DMA_A,
DATA_DMA_A_desc, DMA_write_addr_ptr_A, dma_len_bytes,
ALTERA_MSGDMA_DESCRIPTOR_CONTROL_TRANSFER_COMPLETE _IRQ_MASK);

// Start DMA transfers
alt_msgdma_standard_descriptor_async_transfer(DATA _DMA_A, DATA_DMA_A_desc);


return 0;
}
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Cannot generate cof file - Quartus Prime Lite V17 (595)

October 9, 2017, 10:35 pm
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My project compiles correctly but does not output a .cof file which I need to generate a .jic file for downloading.

I looked into the licensing section and found that it has the lattice license file tagged but I cannot seem to be able to delete the entry in Quartus. Perhaps this is the problem.

Also, about a week ago I was seeing messages saying the license will expire in December. But I am using the free lite version for a Cyclone IV device.

Any ideas? (please don't suggest a new download/install as I have used this months download quota)
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OpenCL project works fine in emulation but weirdly in fpga run

October 9, 2017, 10:37 pm
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I am currently working on an OpenCL project. The output matrix is correct on emulation, but all 0 in hardware run.
I used channels for my kernels' communication (some of them are conditional, which mean I don't read or write to some certain channel in every loop iteration). To debug, I added printf functions and counter after my channel read/write and ran on FPGA again. The code is below (memRd kernel is a kernel I use to read data from global memory and put it in altera channel):

--------------------------------------------------------------------------------------------------------------------
__kernel
__attribute__((task))
void memRd ( float *data, ......) {

......

for (......) {

data = data [index];

if (......) {
write_channel_altera(data_in_ch, data_in);
printf("For the %dth write of kernel memRd, write %0.f to channe data_in_chl\n", chn_cnt, data);
cnh_cnt += 1;

}

}

}

-----------------------------------------------------------------------------------------------------------------------------------------
So in my FPGA run, this is what got printed out:

For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
...............

The entire printed text is just a replication of the 0th writing to channel operation!! I don't understand it why the same code is repeatedly executed in the same place?? ( the 1st write is supposed to appear after the 0th write)

I'll appreciate it very much if someone can give me a help!!!!
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OpenCL project works fine in emulation but weirdly in fpga run

October 9, 2017, 10:41 pm
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I am currently working on an OpenCL project. The output matrix is correct on emulation, but all 0 in hardware run.
I used channels for my kernels' communication (some of them are conditional, which mean I don't read or write to some certain channel in every loop iteration). To debug, I added printf functions and counter after my channel read/write and ran on FPGA again. The code is below (memRd kernel is a kernel I use to read data from global memory and put it in altera channel):

--------------------------------------------------------------------------------------------------------------------
__kernel
__attribute__((task))
void memRd ( float *data, ......) {

......

for (......) {

data = data [index];

if (......) {
write_channel_altera(data_in_ch, data_in);
printf("For the %dth write of kernel memRd, write %0.f to channe data_in_chl\n", chn_cnt, data);
cnh_cnt += 1;

}

}

}

-----------------------------------------------------------------------------------------------------------------------------------------
So in my FPGA run, this is what got printed out:

For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
For the 0th write of kernel memRd, write 0 to channel data_in_ch
...............

The entire printed text is just a replication of the 0th writing to channel operation!! I don't understand it why the same code is repeatedly executed in the same place?? ( the 1st write is supposed to appear after the 0th write)

I'll appreciate it very much if someone can give me a help!!!!
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Error while configuring BSP in NIOS2 build software tools

October 10, 2017, 12:58 am
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Im trying to configure the BSP in nios 2(using the sopc file generated by Quartus 2),
after applying changes to bsp properties,when is BSP editor,it is showing error as following






Error executing 'nios2-bsp-editor --settings settings.bsp', unexpected return code 1.


Error message:


'nios2-bsp-editor' is not recognized as an internal or external command,
operable program or batch file.




can anyone help me solve the problem?
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Issue with 245 Fifo sync mode

October 10, 2017, 12:59 am
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Dear All,

I am actually working on a communication chain between a FPGA and a FT2232H chip. So, the goal is to send a file from PC to FPGA, store it in a FIFO memory and then receive the sent data to PC.


I am using the 245 fifo sync mode.

All is working fine, expect that I rarely have a lose of one byte that appears randomly.

So for example, when I send a packet of 512byte, i received well the 512byte but when I repeat this operations 200 times, I noticed that sometimes I only receive 511 byte and when I check where happens the lost byte, it happens randomly. And when I send a packet of 65.536 byte, again sometimes, I only received 65 535 byte.

The strange thing is that when a lose occurs, this is always one byte.

Can anyone help out me there to solve this problem ?

Attached you will find my VHDL code.

Thank you for your help !
Attached Files
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Connect FFT IP core and QSYS

October 10, 2017, 4:53 am
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Could anyone explain me how do I connect FFT IP core in QSYS? I have tried to use SGDMA but the bits/symbol doesn't match. I don't have DSP Builder.
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Asynchronous reset and synchronizers

October 10, 2017, 6:14 am
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Hello,

I'm looking for the proper way to constrain an asynchronous reset path, with a reset synchronizer. The Quartus Standard (and Pro) handbook touches this subject but barely, in the recommended practices ("Use Synchronized Asynchronous Reset" page 11-26 or 826 in version 2016.05.03).

Wherever I looked, there was only a mention of a set_false_path on the async reset, but in order to avoid metastability, the reset should also be released in a synchronous fashion (hence the resynchronizer). And for this to succeed, there should be a constrain to make sure the output, resynchronized reset (rst_n on the attached figure) is not violating the setup/hold time of the registers that are reset (reg1, reg2), correct?

So on the schematic in attachment, or the code below,
- reset_n is coming from an uncontrolled environment and its timing is unknown
- the path between reg3 and reg4 should be as short as possible, perhaps a min delay constraint must be added to maximize the recovery time before the setup of reg4 in case of metastability
- reg4's output should be stable when reset_n is released, and outputs a '1' synchronously to release the aclrn of the system registers reg1 and reg2

If there is no constraint, and I try to analyze the timing in TimeQuest, I see that the rst_n path is not producing any output, so this tool disregard any timing violation on the asynchronous reset of the system registers.

Has anyone faced the same problem, and found a good solution? A set_false_path on those paths seems a little careless in my opinion.

I'm quoting the Verilog code and the constraints given as example in the handbook:

Code:
module sync_async_reset (
    input clock,
    input reset_n,
    input data_a,
    input data_b,
    output out_a,
    output out_b
);
reg reg1, reg2;
reg reg3, reg4;
assign out_a = reg1;
assign out_b = reg2;
assign rst_n = reg4;


always @ (posedge clock, negedge reset_n)
begin
    if (!reset_n) begin
        reg3 <= 1’b0;
        reg4 <= 1’b0;
    end else begin
        reg3 <= 1’b1;
        reg4 <= reg3;
    end
end
   
always @ (posedge clock, negedge rst_n)
begin
    if (!rst_n) begin
        reg1 <= 1’b0;
        reg2 <= 1;b0;
    end else begin
        reg1 <= data_a;
        reg2 <= data_b;
    end
end
endmodule // sync_async_reset

To minimize the metastability effect between the two synchronization registers, and to increase
the MTBF, the registers should be located as close as possible in the device to minimize routing
delay. If possible, locate the registers in the same logic array block (LAB). Te input reset signal
(reset_n) must be excluded with a set_false_path command:

set_false_path -from [get_ports {reset_n}] -to [all_registers]
Attached Images
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Convert AHDL to Verilog

October 10, 2017, 7:29 am
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I have a design in AHDL for a keyboard scanner and I'm trying to convert this to Verilog.
The AHDL code is in the enclosed ZIP "kbd.zip". The Verilog code is shown hereunder.

The line "assign lresult = (sensecount == i) && sense[7 - i];" gives an error that lresult is driven by multiple gates. Anyone an idea how I can solve that?
Further remarks about the Verilog code also welcome.

Thanks


module kbd (sync,advance,mosi,eesel_n,sense,result,drv) ;


// Input Port Declarations
input sync;
input advance;
input mosi;
input eesel_n;
input [7 : 0] sense;


// Output Port Declarations
output result;
output [15 : 0] drv;


// Internal variables
reg [15 : 0] drvcount;
reg [7 : 0] sensecount;
wire [15 : 0] ldrv;
wire lresult;
genvar i;


always @(posedge sync)
begin
if (!eesel_n) drvcount <= 0;
else drvcount <= drvcount + 1;
end


for (i=0;i<15;i=i+1)
begin
assign ldrv[i] = (drvcount == i);
end
assign drv = !ldrv;


always @(negedge advance or posedge sync)
begin
if(sync) sensecount <= 0;
else sensecount <= sensecount + 1;
end


for (i=0;i<7;i=i+1)
begin
assign lresult = (sensecount == i) && sense[7 - i];
end


assign result = (eesel_n)? lresult : 1'bZ;


// add design description here
endmodule
Attached Files
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Host Channel Support for 17.0

October 10, 2017, 10:34 am
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Best I can gather, there should be support for host/FPGA channels as of 17.0 for cross communication. I cannot, however find any documentation on them, most importantly how to implement them from both sides. Is there support, and if so, where can I find documentation on how to implement it?
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Minimal Cost configuration - Cyclone IV

October 10, 2017, 1:19 pm
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I am working on an upgrade to a product that has been in production for ten years now, using a Cyclone II device. The existing FPGA is sufficient to the task, except it is at "end of life" and they want to be able to produce this product for another 10 years.

So I have migrated the design to a Cyclone IV device : EP4CE15F17C6

The FPGA design include a NIOS II CPU, which is the only processor in the system. Space is tight and I am trying to get everything to fit in the same basic board layout.

Where I have just run into a road block is the configuration device. The product had been using a EPCS device but it has been labeled "Last Buy"

As I understand it, the FPGA will require 4 Mbits. The executable code for the NIOS II is also stored in the configuration device and requires another 2 Mbits. So an 8 Mbit device would be ideal.

Apparently, there is no longer any such device.

I figured the best bet would be to use a EPCQ device.

While there are technically parts as small as 16 Mbits, anything under 256 Mbits has a 14 to 16 week lead time! That doesn't inspire me with confidence that the part will be available for a number of years down the road.

I am aware of other manufacturers making serial proms that would be compatible with the "Active Serial" configuration mode, but it is essential that the serial prom can also be written by the NIOS II CPU for a "remote upgrade" and I believe that this wouldn't work with the alternative devices.

What I am having trouble understanding is why the configuration device is going to end up costing more than the FPGA itself! The old design had a FPGA + Configuration solution that cost about $40. It is looking like a new solution is going to cost over $100!

Am I missing something?
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Nios II Eclipse in Windows 10

October 10, 2017, 12:04 pm
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I just got a new machine with Windows 10 64-bit. I previously had win 7 64 bit installed with Quartus prime 15.1 installed. I tried installing Quartus prime 15.1 on the windows 10 box. It installed. I found i had to apply the Cygwin patch as mentioned below
Updating Cygwin for Quartus II 13.1 on Windows 8.1

There is a compatibility issue that causes old versions of Cygwin to fail to run on Windows 8.1. This affects all of Altera’s tools that use Cygwin, such as Altera Monitor Program and Nios II EDS. To solve this issue, the Cygwin that is installed with Quartus II must be updated as follows:

  • Download the patch at ftp://ftp.altera.com/up/pub/Cygwin_P...gwin_patch.zip
  • Extract the contents of cygwin_patch.zip to your Quartus II install directory, overwriting existing files. Both 32-bit and 64-bit versions of Cygwin are included in the zip file; extract both of these versions to your Quartus II install folder. The default path to the Quartus II install folder is “C:\altera\13.1\quartus”.


I did this only for version 15.1. It seems to work for the quartus portion, it compiles. However, Nios does not compile properly. It says

make: *** [program_name.elf] Error 2
make: *** Deleting file `program_name.elf'

It dosn't give any other information. Has anyone else had success with nios in windows 10?

Mark
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Placement cannot find a legal solution

October 11, 2017, 3:30 am
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Hi,

I am targeting the a10gx using AOC and Quartus Prime, both v16.1.2 Build 203.

According to the logs my design is not overutilizing resources, but the building process fails during fitting:

Code:
Error (18999): Placement cannot find a legal solution
I found another post reporting the same problem https://www.alteraforum.com/forum/sh...ad.php?t=55881, but it doesn't help as I am using Linux for my compiling machine and targeting the a10gx.

The only thing I assume is that my design requires more resources than available and the tool is not showing correctly this, but this is just a guess.
As far as I know, error messages due to overutilization are different.

Perhaps anyone could give some hints on this?

The following link contains some logs (logs are too large to be attached to this post)
https://www.dropbox.com/s/izv7ld1bj5..._logs.zip?dl=0
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EPM1270GF256I-5 is supported by Quartus 15.1 ?

October 11, 2017, 4:06 am
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Hi all,

I'm a new developer of Altera devices, and I started working to a VHDL design for a EPM1270GF256I-5 CPLD.

I am unable to find if this CPLD is supported by recent version (15.1) of Quartus Prime
(seem to me it was not supported in my current 13.1 - free, 32 bit, since is not possible to select this device).


I have to be VERY sure of this - need to use existing license in my office ...


Thanks,

Stefano
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Testbench for 10G Ethernet PHY

October 11, 2017, 4:25 am
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Hello,
I just implemented a 10G Ethernet PHY design using the IP core: "1G/2.5G/5G/10G Multi-rate Ethernet PHY" + pll & reset controller.
The Ethernet PHY core should receive the serial data from an SFP+ modul (Stratix 10 SX FPGA)
Now, I need to simulate the design to check if everything is working fine.
I don't know which input data vector for the Ethernet PHY core I should use and which outputs should expect.

Thanks a lot
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most likely problem with devicetree, but why?

October 11, 2017, 6:16 am
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Hello all,

I have a project wherein the FPGA communicates directly with SDRAM. To enable this i need to run a few commands during boot. namely:
>setenv fpga2sdram_handoff 0x111
>run bridge_enable_handoff
>saveenv
>boot

I need to get these commands automated in the process, program the right rbf file and boot the linux kernel. I can always get 1 to work, but never everything at the same time.
I normally follow the steps in the following guides:
https://rocketboards.org/foswiki/Doc...sLab1Preloader
Short example of the steps i'd take
1) compile the entire project
2) using bsp-editor create a preloader
3) make a u-boot (i have done this in several ways, i have also tried using the u-boot supplied in the GSRD)
4) make a bootscript, in this bootscript i point to the right .rbf file and reserve some memory for the software running on the hps. I do this by adding "mem=800M" to the line "setenv mmcboot 'setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait; bootz ${loadaddr} - ${fdtaddr}';"
5) run the mkimage command on the boot.script to make it readable for the bootproces
6) make the kernel, again I have used different methods and i have also tried using the version supplied with the GSRD.
7) generate the device tree. mostly i use the sopc2dts command, followed by the dtc command to turn the dts into a dtb. as illustrated here: https://rocketboards.org/foswiki/vie...eTreeGenerator
8) place everything on the sd-card, using the dd command or something similar.

After I have done all this, the bridges are correctly set, memory is allocated, the rbf is programmed but the whole process is stuck at "starting kernel"
I have gotten the kernel to work once, but then all other features like ethernet, usb, fpga, ...were disabled and obviously that is not supposed to happen.
I already took a look at this thread (https://alteraforum.com/forum/showth...tarting+kernel) but it didn't offer much help.

The major problem here is: there are just so many guides on each individual step, taking very different approaches. I have tried many and most of them fail because of dead links or because i'm not using exactly the right linux distro (using centOS7 and ubuntu 16.04 LTS, or just SoCEDS on windows 10) or because some repositories are not available anymore, or ... or ...
But my case is so simple! compared to the GSRD i have just added 1 custom IP component and enabled the FPGA-SDRAM bridges. Why am I having so much trouble with this?



Thanks for the time and help!
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Parallel accesses to banked local memory

October 11, 2017, 7:20 am
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I've been attempting to bank local memory so that I can perform parallel access. I can't seem to get it to work. The compiler always either replicates the memory or generates the memory bank with stalls. I don't understand why the code snippet below doesn't generate a number of parallel BRAMs capable of being accessed concurrently.

#define L 64


__kernel __attribute__((task))
void test(
__global char * restrict message,
__global char * restrict decodedData
)
{

local char __attribute__((numbanks(L),
bankwidth(1))) msgMem[L][256];

int __attribute((register)) Lrji_row_sum[L];

//store data across L memory banks
for(uint k=0; k<256; k++)
{
for(uint r=0; r<L; r++)
{
msgMem[r][k]=message[(k*L)+r];
}
}

mem_fence(CLK_LOCAL_MEM_FENCE | CLK_GLOBAL_MEM_FENCE);

//accumulator for each memory bank
for(uint i=0; i<256; i++)
{
#pragma unroll
for(uint r=0; r<L; r++)
{
Lrji_row_sum[r]=msgMem[r][i];
}
}

for(uint r=0; r<L; r++)
{
decodedData[r] = Lrji_row_sum[r];
}

}


I'm using Quartus 17.0.1

Appreciate the help,
Jason
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Cyclone V E Instantiating Multiple ASMI Blocks

October 11, 2017, 8:46 am
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In our project we are wanting to utilize the "Altera Remote Update" IP to load secondary application images from an EPCQ device. In this IP there is an option to enable POF checking such that this secondary image is verified before being loaded. The POF checking option requires the instantiation of an ASMI Parallel Block to interface with the EPCQ device. However, also in our project is a QSYS block that instantiates an EPCQ controller which instantiates an additional ASMI Parallel Block. When running the fitter with the design, I get the error "Found 2 SPI Blocks in design -- only one SPI block is allowed". I am wondering if anyone knows of a way for these two functionalities to coexist on the same device, or a scheme to somehow mux the EPCQ control signals from the epcq controller and the remote update blocks. The issue is that the ASMI block instantiated by the EPCQ controller does not give access to these ASMI signals.

Attached are images of the QSYS instantiation of the epcq controller and resource utilization page.

Thanks
Attached Images
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MAX10 TSD - ADC Toolkit results in BSoD on Windows 10

October 11, 2017, 10:33 am
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A little background. I'm doing development on a custom board designed for a class. It uses the MAX10 10M50SAE144C8G. The board is used for a hardware security lab course and we're using the built in TSD to trigger some events.

So as a proof of concept, I wanted to just get some easy measurements from the ADC using the ADC Toolkit as described in this video (https://tinyurl.com/yc74buc). I got all of that working, and am able to look at the ADC data using the scope feature in the ADC Toolkit. The values do NOT match what is in the spec sheet, but that's another topic for another time. But I can heat up my device, cool it down, and I can get the data to change how I'd expect.

The issue I have is that when I scope the ADC data, after a little bit of time I get the blue screen of death (BSoD). It only happens when I use the ADC Toolkit and I start a measurement. Sometimes, I'm able to get a small sample and close the window without the BSoD. If I get a small sample and stop the scope, but do not close the window, I get BSoD.

Any ideas what is wrong? I searched around and couldn't find anyone else with this issue.

Thanks!
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How is the Quartus Prime offline help done?

October 11, 2017, 11:22 am
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Hi! Just a simple question that I have not been able to find an answer for:

When, in Quartus Prime 17.0, you go to Help -> Help Topics, a help web site opens up in you web browser. It is served locally from, in my case, file:///c:/intelfpga_lite/17.0/quartus/common/help/webhelp/index.htm

What web server is used? How is search done? It seems to send requests to google?
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