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Warning (332068): No clocks defined in design.

October 11, 2017, 2:23 pm
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Hi,

I have assigned clock, but still getting a warning message saying: Warning (332068): No clocks defined in design.

I have connected an external input(''clk") for clock, and assigned it to the global clock pin on MAXV CPLD. In addition, I got warning saying that: Warning (15610): No output dependent on input pin "clk" .

How to resolve this issue ?
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Footprint for UBGA 324 pin package

October 11, 2017, 5:30 pm
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I am looking for the recommended PCB footprint for the UBGA 324 pin package as used on the MAX 10 10M16DCU324I7G part.

I have found drawings and even Cadence Allegro .dra files for just about every other package, except that one.

can anyone point me at the proper document for this?

Thanks

Rod
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Confusion about task vs NDRange implementaions

October 12, 2017, 8:01 am
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I'm attempting to implement a simple barrel shifter. I'm able to get it to work using a task based approach but am unable to do so using an NDRange based kernel. I've posted both kernels below. I'd appreciate some insight into how the implementation of the NDRange approach differs from the task.

__kernel
__attribute__((reqd_work_group_size(360,1,1)))
__attribute__((max_work_group_size(360)))
void barrelShifter_nd(
__global unsigned char * restrict dataIn,
const uint shift,
__global unsigned char * restrict dataOut
)
{
char __attribute((register)) din[720];

uint gid = get_global_id(0);

din[gid] = dataIn[gid] & 0x1;
din[360+gid] = dataIn[gid] & 0x1;


dataOut[gid] = din[shift+gid];

}




__kernel
__attribute__((task))
void barrelShifter_task(
__global unsigned char * restrict dataIn,
const uint shift,
__global unsigned char * restrict dataOut
)
{
char __attribute((register)) din[720];

for(uint i=0; i<360; i++)
{
din[i] = dataIn[i] & 0x1;
din[360+i] = dataIn[i] & 0x1;
}

#pragma unroll
for(uint i=0; i<360; i++)
{
dataOut[i] = din[shift+i];
}

}
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How to instantiate a float point IP in OpenCL-HDL hybrid flow?

October 12, 2017, 7:13 pm
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I am putting a verilog module into OpenCL, and in the verilog, a float point ip is used.
Previously in pure HDL flow, I use .ip file with no problem. but now in OpenCL flow, seems .ip file is not supported. Then I am having problem instantiate this module.

I am using arria 10, and the ip is arria 10 naitive floating point adder with 3 stage pipeline.

What should I do? Please help.
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Hardware run result does no match with simulation

October 13, 2017, 1:55 am
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Hello all,

I am working on an OpenCL project for acceleration of image convolution. It produced correct output matrix in simulation, but when I put it in hardware run, the first 2 row of the output matrix did not match with the correct one but the rest did. I understand that the reasons in account for the difference of the results between simulation and hardware run can be 1) kernel channels 2) memory synchronization. However I won't have memory synchronization problem because the the kernels I used are task kernels. And I also made sure the number of channel reads equals to channel write.
Could anyone give advice on the reason that may cause this problem?

Any advice would be greatly appreciated!

Lancer Chiang
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Call a function from a function in VHDL

October 13, 2017, 6:36 am
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Hi guys, I think this is my first post and I am glad to belong to ALTERA forums.
Here is my problem: I've read some posts from other forums and I cannot find anything related to invoke a function from a function in VHDL. Is that possible???? Here is the thing, I created a ROM of 168 positions of std_logic_vectors (7 downto 0) and I did it in a function that returns a std_logic_vector (one of them) so I can read de data several times by calling the function whenever I want. The problem is that I do not know if I can read the data from another function, I have not tried yet, it is a little bit complicated to do it right now at work, I think I could try this weekend , but if you advise me it would be much better:D:D:D. Sorry for my english I speak spanish;)
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High-Z on Differential Port

October 13, 2017, 6:55 am
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Hi,

Following this example https://www.altera.com/en_US/pdfs/li...e/an/an754.pdf, I tried to implement a mipi-csi2
function on a Cyclone V. I have 2 pairs of 2 lines, one is single-ended for low-power mode and one is differential for
High-speed mode. My problem is to set the differential pair to High-Z when mipi bus is in low-power mode,
It seems to be impossible. Is there a way to manage this issue ?

Thanks
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quartus 2 is closing

October 13, 2017, 1:25 pm
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I try to open new project wizard but when I click to new project wizard my quartus close
Can any one help me
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Cyclone III - how to reconfigure from one application image to another?

October 13, 2017, 2:13 pm
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I have EPCS chip attached to FPGA, and have several images in it. Factory is at 0, loaded on power up. Then factory image automatically loads image located at page 8. It works properly. For this I just set remote_update accordingly on factory image start *if reconfiguration status bits are read as 0* (thus this reconfig to image at 8 happens only once, and system does not cycle if there's application image load error).

Now I put another image at address 0x10, and trying to reconfigure from application image loaded from 0x8 to this at 0x10. It does not work as I expected, because it seems I was wrong. Looking through scarce documentation I see that re-configuration should be performed through factory image. Documentation says:

Quote:
When Cyclone III devices successfully load the application image, the soft logic in the application image determines the arrival of remote system update. When a remote system update arrives, the soft logic receives the incoming data, writes it to the memory configuration memory devices, and triggers the system to load the factory reconfiguration. The factory image reads the remote system upgrade status register, determines the valid application image to load, writes the remote system upgrade control register accordingly, and initiates system reconfiguration.
Source at page 3.

I wonder how factory image determines valid application image to load, and how application image, which reconfigured to factory one, tells factory image which application image should be loaded.

Please advise.

Edit: This document, pages 36-37, says it is possible to *read* current image boot address, but writing application boot address can be performed only in factory mode. Thus how I, from application 1, tell factory config that it should load application 2? Is there any register to pass info in?
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Report Loop Analysis NDrange threads

October 13, 2017, 3:31 pm
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Hello everyone

Im struggling to find what means the Details tab in Loop Analysis section of the report, saying ND-range: Thread capacity = 303

example 2Dimension Kernel:

Code:
___Kernel(__global short const * restrict input_a,__global short const * restrict input_b)
short aux[100];
int row = get_global_id(1);
int col = get_global_id(0);
int width = get_global_size(0);

for(int j=get_global_id(1); j < get_global_size(0); j++){
   
        aux = input_a[row*width + col];
        input_b[row*width + j] += aux;
    }
I only can run a maximum of 303 work-items? And what causes that "constraint" on the code ? :confused:
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Profiling autorun kernel without --profile

October 13, 2017, 3:56 pm
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Hi, I have a multi-kernel design that goes

Reader -> (autorun) CU_0 -> (autorun) CU_1 -> (autorun) CU_2 -> Writer (where CU_0, CU_1 and CU_2 are the same).

And I'm attempting to get the execution time of every kernel in the design (have already used --profile but require run at full Freq). below is a snippet below, but I wanted to check that using the time_start2 - time_end1 is correct as I haven't found any examples of using events across multiple commandqueues and the fluctuation in results appears rather large.

Cheers Sam

Code:
#################### Averages #####################
Reader Execution Time
min 6812, avg 7308, max, 11493
Processing Execution Time
min 9135, avg 36094, max, 94796
Writer Execution Time
min 6614, avg 7063, max, 9013
Total Execution Time
min 22657, avg 50466, max, 110813
###################################################
Code:
...
  uint64_t min[4] = {0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF};
  uint64_t avg[4] = {0};
  uint64_t max[4] = {0};

#define N 200

for (uint i = 0; i < N; i++) {

    status = clEnqueueTask(queue1, kernel1, 0, NULL, &kernel_event1);
    status = clEnqueueTask(queue2, kernel2, 0, NULL, &kernel_event2);

    checkError(status, "Failed to launch kernel");
    clFinish(queue1);
    clFinish(queue2);

    uint64_t time_start1, time_end1, time_start2, time_end2;
    uint64_t reader_time_ms, processing_time_ms, writer_time_ms, total_time_ms;

    clGetEventProfilingInfo(kernel_event1, CL_PROFILING_COMMAND_START, sizeof(uint64_t), &time_start1, NULL);
    clGetEventProfilingInfo(kernel_event1, CL_PROFILING_COMMAND_END, sizeof(uint64_t), &time_end1, NULL);

    clGetEventProfilingInfo(kernel_event2, CL_PROFILING_COMMAND_START, sizeof(uint64_t), &time_start2, NULL);
    clGetEventProfilingInfo(kernel_event2, CL_PROFILING_COMMAND_END, sizeof(uint64_t), &time_end2, NULL);

    if (i > 5) {
        reader_time_ms =  (time_end1 - time_start1);
        avg[0] += reader_time_ms;
        if (reader_time_ms > max[0])
            max[0] = reader_time_ms;
        if (reader_time_ms < min[0])
            min[0] = reader_time_ms;

        processing_time_ms = (time_start2 - time_end1);
        avg[1] += processing_time_ms;
        if (processing_time_ms > max[1])
            max[1] = processing_time_ms;
        if (processing_time_ms < min[1])
            min[1] = processing_time_ms;
   
        writer_time_ms =  (time_end2 - time_start2);
        avg[2] += writer_time_ms;
        if (writer_time_ms > max[2])
            max[2] = writer_time_ms;
        if (writer_time_ms < min[2])
            min[2] = writer_time_ms;

        total_time_ms  =  (time_end2 - time_start1);
        avg[3] += total_time_ms;
        if (total_time_ms > max[3])
            max[3] = total_time_ms;
        if (total_time_ms < min[3])
            min[3] = total_time_ms;
    }
}

    printf("#################### Averages #####################\n");
    printf("Reader Execution Time\n");
    printf("min %" PRIu64 ", avg %" PRIu64 ", max, %" PRIu64 "\n",min[0], avg[0] / (N-5), max[0]);
    printf("Processing Execution Time\n");
    printf("min %" PRIu64 ", avg %" PRIu64 ", max, %" PRIu64 "\n",min[1], avg[1] / (N-5), max[1]);
    printf("Writer Execution Time\n");
    printf("min %" PRIu64 ", avg %" PRIu64 ", max, %" PRIu64 "\n",min[2], avg[2] / (N-5), max[2]);
    printf("Total Execution Time\n");
    printf("min %" PRIu64 ", avg %" PRIu64 ", max, %" PRIu64 "\n",min[3], avg[3] / (N-5), max[3]);
    printf("###################################################\n\n");

...
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Noise decoupling

October 14, 2017, 12:10 am
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I am giving RF power which is dc through terasic daughter card adc/dac to altera DE2-115 fpga but i am not able to see the dc in signal tap analyzer . it is showing some noise . So is there any way if i can block that high frequency noise component so that i can see the smooth dc in STA. I need to read the bit value of that particular dc signal which is not stable and changing forever.
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Mod5 Counter

October 14, 2017, 3:45 am
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I need to do a VHDL program and I need to replace the use of 74191 IC and with the aid of the the FPGA I need use the toogle switches to start the count in mod5. Till now this is the program that I've done can someone guide me what should I do next and another question how do I need to connect the pin from the pin planner.

library ieee;
use ieee.std_logic_1164.all;




entity assignment is
port(
Clock: IN STD_LOGIC;
count : BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0):= x"0000";
I : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
o : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) := x"0"

);end ENTITY;


architecture BEH of assignment is --


begin
process (I) --process is sensitive to A and B
variable clk_cnt : integer range 0 to 50000000 :=0;
variable x : integer range 0 to 8 :=0;

begin



if (clock'event and clock = '1') then
clk_cnt := clk_cnt + 1;


if (clk_cnt = 49999999) then
x:= x + 1;
end if;
end if;

if (x = 2) then
O<= "11011010";
end if;

if (x = 3) then
O<= "11110010";
end if;

if (x=4) then
O<= "01100110";
end if;

if (x=5) then
O<= "10110110";
end if;

if (x=6) then
O<= "10111110";
end if;

if (x=8) then
x:=2;
end if;

end process;


end ARCHITECTURE;
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FPGA Transceiver connection

October 14, 2017, 6:34 am
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I have designed Cyclone V based board.

I have connected SFP TX and RX pin in transceiver, as attached.

In this I need to clarify, whether REFCLKL[0,1]P, N should be connected to differential clock or no need.

How it will affect SFP data transfer. Please support.
Attached Images
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Cyclone V Configuration Devices

October 14, 2017, 11:12 am
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I've got a Terasic Cyclone V GX development board. I removed the EPCQ256 configuration device and am testing two other alternatives (Macronix MX25L257 and Cypress S25FL128). I created a simple project with some LEDs and am using JTAG indirect programming to program the devices (jic file).

In both cases Quartus will program the devices and verify without error, but in neither case will the FPGA configure properly at power up (active serial).

nCONFIG = 3.3V
CONFIG_DONE = 0V
nSTATUS = 2V (?)

Any thoughts?
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PCIE Pinout doubts and Problems Cyclone V

October 14, 2017, 12:29 pm
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Hi guys,
Well I have to communicate two FPGA cyclone V by PCIe, but I dont know if I can use all pins.


Here are some doubts about pins


- PRSNT#1 :This pin if a hot plugg detec, but If I conected by PCIe two FPGA, How should I use this pin??
- rest : Should I use a pull-up resisten to this pin?
- Wake : How should I use this pin?
- REFRENTCLOCK: I know that PCIE has clock embbed in his data (encoding 8b/10b makes it possible), so should I use a Clock?
- JTAG and SMbus: That are auxiliar signal, How should I use thata pins?


Help please, any infomation will be usefull to me


Regards
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Minimum fpga dev-kit/fpga

October 15, 2017, 5:46 am
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Hi Everyone, I am new to opencl and fpga programming. I would like to know some good fpga boards where i can test my some ideas. Looks to me opencl too have licensed attached. Also pls clear my confusion after reading so many pages on fpga's , Are intel and altera opencl same or do they have some differences (i know the merger). I come from SDR world. Thank you.
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Implementation of VHDL program on FPGA

October 15, 2017, 10:21 am
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Hello,
I try to implement a simple vhdl program " if the switch button is ON then the led has to be ON" on FPGA using Quartus but it doesn't work means the switch is ON but the led is still OFF. however, when i implement a block diagram using quartus on FPGA it works !!!. Is there an option which have to be activated on the tools? how can i solve the problem ?
Many thanks
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Getting 'Timing requirements not met' as critical warning

October 15, 2017, 11:35 am
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Hi, I have created a design and would like to compile the design in order to create a binary file for the CPLD. However when I try to compile the design, it outputs a warning saying that the timing requirements not met. It seems like it is complaining about the following component where the external clock is divided into a lower clock frequency that is used by the other components in the design:

Code:
entity clk_divider is
    generic (COUNTER_MAX : integer := 256000);
    port(
            clk_in  : in std_logic;
            reset  : in std_logic;
            clk_out : out std_logic
        );
end clk_divider;


---------------------------------------------------


architecture Behavioral of clk_divider is


    signal signal_level : std_logic := '0';
    signal counter : integer range 0 to COUNTER_MAX := 0;


begin
    clk_divider : process (clk_in, reset)
        begin


        if (reset = '1') then
            signal_level <= '0';
            counter <= 0;
        elsif rising_edge(clk_in) then
            if (counter = COUNTER_MAX) then
                signal_level <= not(signal_level);
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    clk_out <= signal_level;
end Behavioral;
The critical warning message shown during design compilation is shown below:

Code:
Critical Warning (332012): Synopsys Design Constraints File file not found: 'monitor.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name clk clk
    Info (332105): create_clock -period 1.000 -name clk_divider:clk_module|signal_level clk_divider:clk_module|signal_level
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -7.891
    Info (332119):    Slack      End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    -7.891            -123.541 clk
    Info (332119):    -1.602              -5.110 clk_divider:clk_module|signal_level
Info (332146): Worst-case hold slack is -0.816
    Info (332119):    Slack      End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    -0.816              -0.816 clk
    Info (332119):    1.732              0.000 clk_divider:clk_module|signal_level
Info (332146): Worst-case recovery slack is -4.190
    Info (332119):    Slack      End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    -4.190            -20.950 clk_divider:clk_module|signal_level
    Info (332119):    -3.654            -76.734 clk
Info (332146): Worst-case removal slack is 4.320
    Info (332119):    Slack      End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    4.320              0.000 clk
    Info (332119):    4.856              0.000 clk_divider:clk_module|signal_level
Info (332146): Worst-case minimum pulse width slack is -2.289
    Info (332119):    Slack      End Point TNS Clock
    Info (332119): ========= =================== =====================
    Info (332119):    -2.289              -2.289 clk
    Info (332119):    0.247              0.000 clk_divider:clk_module|signal_level
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
What is the reason for this warning message and how can I solve it? Also what does the slack numbers say about my design?

Thanks.
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bsp-generate-files SEVERE: null

October 15, 2017, 12:27 pm
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Thanks in advance. I know that I have done this command before and it has generated the "uboot" directory. But now I'm working on another project (just the GHRD for the Sodia Eval board) to embed to the QSPI and I get an error (see below).

My steps before this command were:
1. Use the GHRD for 16.1 for the Sodia - but utilize Q 17.0 - so I a) generate in QSYS b) recompile
2. Use the bsp-editor to specify that I want to boot from QSPI and generate
3. Start up the embedded-command-shell and
a) bsp-create-settings --preloader-settings-dir=hps_isw_handoff/soc_system_hps_0 --type=uboot --settings=software/settings.bsp
b) bsp-update-settings --settings=software/settings.bsp --set uboot.boot_device QSPI

THEN --> when I do the "bsp-generate-files" there is the error.

WHAT AM I MISSING ??

************************************************** ************************************************** ***********************
bsp-generate-files --settings=software/settings.bsp --bsp-dir=software/uboot

q16@nxp-System-Product-Name:~/SODIA/Q17.0-withGHRD-16.1/sodia_ghrd_v16.1.0$ bsp-generate-files --settings=software/settings.bsp --bsp-dir=software/uboot
INFO: Generating BSP files...
INFO: nios2-bsp-generate-files --settings software/settings.bsp --bsp-dir software/uboot
INFO: Initializing BSP components...
INFO: Finished initializing BSP components. Total time taken = 2 seconds
INFO: Searching for BSP components with category: os_software_element
INFO: Searching for BSP components with category: driver_element
INFO: Searching for BSP components with category: software_package_element
INFO: Generating BSP files in "/home/q16/SODIA/Q17.0-withGHRD-16.1/sodia_ghrd_v16.1.0/software/uboot"
INFO: Generated file "/home/q16/SODIA/Q17.0-withGHRD-16.1/sodia_ghrd_v16.1.0/software/settings.bsp"
SEVERE: null
java.lang.NullPointerException
at com.altera.embeddedsw.utils.MemoryMapUtils.getMemo ryMap(MemoryMapUtils.java:32)
at com.altera.embeddedsw.bsp.core.internal.generator. device_tree.DeviceTreeImporter.importModel(DeviceT reeImporter.java:44)
at com.altera.embeddedsw.bsp.core.internal.generator. device_tree.DeviceTreeGenerator.importPhase(Device TreeGenerator.java:50)
at com.altera.embeddedsw.bsp.AbstractBsp.generate(Abs tractBsp.java:1367)
at com.altera.embeddedsw.commandline.bsp.BspGenerateF ilesCommand.execute(BspGenerateFilesCommand.java:9 2)
at com.altera.embeddedsw.utilities.commandline.Abstra ctBuildCommandLine.executeCommand(AbstractBuildCom mandLine.java:150)
at com.altera.embeddedsw.commandline.bsp.BspGenerateF ilesCommand.main(BspGenerateFilesCommand.java:118)
SEVERE: nios2-bsp-generate-files failed.


************************************************** ************************************************** ***********************
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