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windrvr6.sys lead to blue Screen

November 1, 2017, 11:30 pm
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I am implementing Support Vector Machine(SVM) predict function on de5net_a7 but I have some problem that the program will lead blue screen on win10 and win7 system,
The OpenCL program working properly on GPU，and the sdk can generate .aocx file，my SDK version is 16.1，how can i solve this problem. Thank you very much.

This is my kernel code:
Code:
#define GSIZE 64
__attribute__((num_simd_work_items(4)))
__attribute__((reqd_work_group_size(1,1,64)))
__kernel void classification(__global uchar * restrict textures, __global uchar * restrict SVS,  __global float * restrict alphas,
                    float gamma,__global float * restrict result)
{
    uint gidx = get_global_id(0);    //img_w
    uint gidy = get_global_id(1);    //img_h
    uint gidz = get_global_id(2);    //sv_num
    int img_w = get_global_size(0);
    uint lid = get_local_id(2);    //64
    uint group_size_z = get_num_groups(2);
    uint group_id_z = get_group_id(2);
    __local uchar texture[90];
    __local float alpha_local[GSIZE];
    __local float res[GSIZE];
    __local float gamma_local;
    if(lid==0){
        gamma_local = gamma;
        #pragma unroll
        for(int i=0;i<90;i++){
            texture[i] = textures[(gidy*img_w+gidx)*90+i];
            if(i<GSIZE){
                alpha_local[i] = alphas[group_id_z*GSIZE+i];
            }
        }
    }
    barrier(CLK_LOCAL_MEM_FENCE);
    int temp = 0;
    int i=0;
    #pragma unroll
    for(i=0;i<86;i+=4){
        int t0 = SVS[gidz*90+i]-texture[i];
        int t1 = SVS[gidz*90+i+1]-texture[i+1];
        temp += t0*t0+t1*t1;
        t0 = SVS[gidz*90+i+2]-texture[i+2];
        t1 = SVS[gidz*90+i+3]-texture[i+3];
        temp += t0*t0+t1*t1;
    }
    #pragma unroll
    for(;i<90;i++){
        int t0 = SVS[gidz*90+i]-texture[i];
        temp += t0*t0;
    }
    res[lid] = alpha_local[lid]*exp(-1*gamma_local*(float)temp);
    barrier(CLK_LOCAL_MEM_FENCE);
    if(lid==0){
        float sum=0;
        #pragma unroll
        for(int i=0;i<GSIZE-3;i+=4){
            sum += res[i];
            sum += res[i+1];
            sum += res[i+2];
            sum += res[i+3];
        }
        result[(gidy*img_w+gidx)*group_size_z+group_id_z] = sum;
    }
}
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mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

October 30, 2017, 2:38 am
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Hi,

I am using a DE1-SoC board equipped with Cyclone V SoC, I have a custom circuit on FPGA with Avalon interface, I want to transfer some data from the DDR3 (of the HPS) to this circuit. I used an mSGDMA to do that. I am using linux and I began with a false driver so I control all of this from the user space using mmap() function.

In Qsys I activated the the F2S interfaces, I connected the read port of the mSGDMA to this interface (avalon than AXI), and the write port to my circuit. both of the ports are 32 bits data wide.
I have mmaped a region on SDRAM to write directly to it the source data, I mmaped the csr and descriptor reg too. the preloader and all headers file are updated according to the design.
The Linux stuck when the transfer begin.
I have used SignalTapII to find the problem.
first observation is the transfer begin, it transfers the eight beats of addresses then it reads one beat of data and it stuck.
second when I am using avalon on the F2S interface:
the address demanded by the mSGDMA (which is the same as my c program) is divided by 8 in the input of the F2S interface, which is not the problem when I choose an AXI interface.

I would like to know where is the problem, is there any one who face this problem yet.
If It is possible, is there any tutorial that shows the procedure to read data from F2S interface
Thanks
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No console message in uCLinux

October 30, 2017, 3:14 am
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Dear all,

We are preparing one design for Arria 10 GX Development kit. That design is having following components:
  • Nios II (Gen2) Processor with MMU enabled
  • DDR4 memory.
  • On-chip memory as a reset vector (offset 0x0), exception vector (offset 0x20) and fast TLB miss exception vector (offset 0x100).
  • JTAG UART alongwith interval timer are also there in design. As suggested at http://www.alterawiki.com/wiki/UClin...t_step_by_step in Altera wiki, interval timer has been assigned IRQ0 and JTAG UART IRQ1.
  • We have ensured that total address span does not exceed 512MB. (Not sure why do we need this limitation?)


We checked design without MMU and by using Eclipse, Hello world program works nicely. But when we enabled MMU and built uCLinux image with that, no output is printed.

Note that image is getting downloaded successfully and also processor is started. See below.


$ nios2-download -g linux.initramfs.gz
Using cable "USB-BlasterII [USB-1]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 4926KB in 8.7s (566.2KB/s)
Verified OK
Starting processor at address 0xC0000000


$ nios2-terminal.exe
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-BlasterII [USB-1]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)


No output after this. Could anybody give any hint to solve this?

Thank you,
Bhaumik
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If on-chip memory is too small to store the program data, what other options exist?

October 30, 2017, 3:26 am
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Looking for 125°C Automotive EPCS or EPCQ (replacement) version

October 30, 2017, 6:34 am
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Dear Community and Intel/Altera,




So, finally, my question: Do you have a solution to connect your automotive 125°C FPGAs to a 125°C Flash Chip by AS-Programming? Is there an existing compatible alternative?
(The Device-ID-Check, which seems not able to be disabled during JTAG-Jic-File Programming seems to kill all available alternatives (as Spansion is now Cypress), see https://www.altera.com/support/suppo...52015_587.html)

Thank you very much!
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Disable Device ID check during JTAG Programming

October 30, 2017, 6:42 am
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Hello Community, Altera, Intel,

sorry for multiple posts, but i would like to seperate discussions about 125°C Flash Memory.

I would like to use a 125° Automotive configuration flash IC (no matter which manufacturer). I attached this type to a Cyclone IV FPGA just for testing: http://www.mouser.com/ds/2/100/001-9..._25-775474.pdf . I, of course, disabled DEVICE ID Check for jic File generating. But i cannot flash this image to my fpga because the programming tool seems to check the flash id any way:

You may turn on the “Disable EPCS/EPCQ ID Check” option in the Convert Programming Files option when you want to generate programming files which disable the EPCS/EPCQ ID check performed by the FPGA when it configures from EPCS/EPCQ. This option will not disable the ID check performed during programming of the EPCS/EPCQ devices by Quartus® Prime software.

So, my question is: How can i disable ANY ID Checks so i can use a small automotive 125° flash chip? Is there a special command or option to disable checks during jtag ijc programming?

Thank you very much!

P.S. What is the point any way do disable ID Checks (for flash loaders for example?) but stimm to kill any direct programming feature by AS-Programming when using alternative flash chips (Automotive chips!) ?
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assertion failed! Pin_memory problem.

October 30, 2017, 9:38 am
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Hi
I'm encountering an assertion failed problem. The returned message is "MMD FATAL: acl_pcie_dma_windows.cpp:381: WDC_DMASGBufLock function failed."
I looked into the acl_pcie_dma_windows.cpp file and it was somthing about pin_memory:
Code:
379  assert(lock_size < MAXDWORD);
 380  WD_status = WDC_DMASGBufLock(m_device, lock_addr, lock_options, (DWORD)lock_size, &new_mem->dma );
 381  ACL_PCIE_ASSERT( WD_status == WD_STATUS_SUCCESS, "WDC_DMASGBufLock function failed.\n" );
It doesn't happened every time I execute my program, most of the time it would run successfully (without recompilation), but the frequency is increasing as I'm using more clCreateBuffer (which is the only thing I can think of that is related to pinning memory).
Anyone have idea of what does this error mean and how to solve it? Thanks a lot!
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MAX V CPLD Reset and OE

October 30, 2017, 3:16 pm
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Hi Guys,
I have a problem with the RESET and OE.
I noted the MAX V CPLD has assigned pin 44 as DEV_CLR and pin 43 as DEV_OE. I have set pin 44 as my global reset in my design.
However, after checking the output by logic analyzer, it looks like the reset was not working at all, and I have also checked the schematic by the using Netlist Viewer, the reset is connected to DATAD or DATAB on every DFF.
I'm wondering if I miss some setting for the reset? Could you please help me figure it out?
Thanks!
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NOR flash read write problem

October 30, 2017, 7:33 pm
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Hi all experts


I have a problem with NOR flash when it reads and writes.


Here is my parameters

Arria10 (with quartus prime standard edition)
Micron Serial NOR flash 1.8V (MT25QU01GBB
(There is limited images I can post, so I will put the link on reply)

Msel = 010 (hard wired) as below
(There is limited images I can post, so I will put the link on reply)

epcq_controller in qsys was set as below

("STANDARD" & "QUAD" both cases were tried)


devices & pin option was set as below


(I also tried "AUTO" for "EPCQL1024" & "1.8V" in configuration device)


When I tried to write .sof image into flash by using "NIOS II Flash Programmer"
Error message pops up as below


Do you have any idea or any suggestion for this issue?




--------------------------------------------------------------------------------------------------------
To debug this issue, read & write test was performed by using Memory Test template

Here is my result of Memory Test template (below)



If you have any idea or any suggestion, I appreciate your help.


Thank you for reading
Attached Images
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Question about Example 1-22 of Quartus Prime TimeQuest Timing Analyzer Cookbook

October 31, 2017, 6:57 am
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In Example 1-22 of "Quartus Prime TimeQuest Timing Analyzer Cookbook", the latency of clk_a and clk_b is specified. clk_a and clk_b are in the different clock_groups. However, if is normal that they are not used in set_input_delay and set_output_delay. Why should the latency and clock_groups for clk_a and clk_b be specified if they are used in the set_input_delay and set_out_delay?

Also
set input_max [expr $Td_max + $Tco_max]

set input_min [expr $Td_min + $Tco_min]

# Create the input delay constraints when clk_a is selected

set_input_delay \
-clock virtual_source_clk_a \

-max $input_max \

[get_ports datain]

set_input_delay \

-clock virtual_source_clk_a \

-min $input_min \

[get_ports datain]


Are there the differences in the clock paths missing in $input_max and $input_min?

Thanks
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time contain for a driver

October 31, 2017, 11:03 am
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hi,

I have a divider as following. I usually ignore the timing report for the divider. I started to check those timing report for the divider. There is a hold timing violation as shown in the screen capture. Hold timing violation means the data changes too quick after the sampling clock. So I have several questions about the report.

1) Does the timing report really mean that the clk_out change too quick after the sampling edge due to the loop back to the input?
2) I implemented the divider like this for many years. If the answer is yes to question 1, how should the divider be implemented to correct the timing violation?
3) If the answer is no to question 1, then why does the TimeQuest reports it as a violation? Should I ignore this violation by set as a node false path from clk_out to clk_out?


thanks
Peng

module divider
#(
// Parameter Declarations
parameter DIVIDER = 1000,
parameter CNT_WIDTH = 16
)

(
// Input Ports
input rst_n,
input sys_clk,
output reg clk_out
);

// timer counter
reg[CNT_WIDTH-1:0] counter;
always @(posedge sys_clk or negedge rst_n)
begin
if(!rst_n)
begin
counter<=0;
clk_out<=1'b0;
end
else
if(counter==DIVIDER-1)
begin
counter<=0;
clk_out<=~clk_out;
end
else
counter<=counter+1'b1;
end
endmodule
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Build error Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful

October 31, 2017, 9:39 pm
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I try to build the code.
But there are error messages in quartus_sh_compile.log
How to solve it?
I have uploaded the file quartus_sh_compile.log


Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 576 megabytes
Error: Processing ended: Wed Nov 01 09:30:37 2017
Error: Elapsed time: 01:01:10
Error: Total CPU time (on all processors): 00:00:01






Thanks,
Matt
Attached Files
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sdram addressing troubles

November 1, 2017, 1:53 am
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i'm working with SoCrates board.
In my project i use the HPS and two custom IP Cores(for example core1 and core2)

core2 have avalon slave(for configuration by hps) and avalon slave(for receiving data from core1)
core1 have avalon slave (for configuration by hps) and avalon master(for transmitting data to sdram and core2)

i connect av_master(core1) to sdram and core2, and now i have error because sdram use address (0x00000000 - 0xffffffff) and core2 slave (0x00000000 - 0x0000003f)
but in SoCrates board there is only 1Gb memory and therefore the sdram address must be in the range 0 to 0x3fffffff.

how can i solve this problem?
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Altera board libraries not found (as usual)

November 1, 2017, 7:21 am
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Hi guys, as usual Altera/Intel SDK never works out of the box. I have good experience with Quartus 16.0 and OpenCL SDK 16.0 but now I have installed Quartus 17.0 and OpenCL SDK 16.1 and I have added the registry dword at Software/Altera/OpenCL/Boards with the dll from the board package but nothing... When I run my application it can find the platforms but then it crashes when it tries to retrieve the devices for the FPGA one... Why is this happening?!
I have tried anything but the altera/intel pdf they provide doesn't tell more than the basic steps. There is no troubleshoot system. I am stuck...
Thank and sorry for asking such a common question.
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Arria 10 Dev Kit: unable to connect to ethernet as instructed in Quick Start Guide

November 1, 2017, 8:18 am
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Hi all,

We've just received a new Arria 10 GX FPGA Dev Kit. As the first step, we try to follow Quick Start Guide (https://www.altera.com/content/dam/a...ga_dev_kit.pdf) and connect to the board's Board Upgrade Portal. Unfortunately, we failed at Step 1. As instructed on the document, we power off the board, switch SW6.4 to ON position to load factory design (Step 1.1), and connect ethernet cable to the board (Step 1.2), and power it on (Step 1.3). As described in Step 1.3, we should be able to see the board showing "Connecting" on the LCD display, and, when an IP address is obtained, showing the IP address. However, after powering on the board, we saw nothing on the LCD display. We put it there for 30 minutes and nothing showed up.

Have anyone had a similar experience? Does anyone have any clue how to fix this? Any suggestion is much appreciated!
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Can't get PCIe (avalon-MM) reference design to work on Arria 10 Dev Kit.

November 1, 2017, 8:41 am
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Hi all,

Our research lab recently purchased an Arria 10 GX FPGA Dev Kit. We would like conduct some studies which require transferring data between the host computer and the FPGA via PCIe, so we started with the reference design found on Altera Wiki (http://www.alterawiki.com/wiki/Reference_Design:_Gen3x8_AVMM_DMA_-_Arria_10), to be sure we are doing the right thing, we followed the exact steps instructed in this Altera Tutorial video on Youtube (https://www.youtube.com/watch?v=CGs2Q3028ss).

We could successfully program the ref design onto the FPGA board. Since we have only one computer (referred to as machine#1) available, we use it as both the programming machine and the host machine. We first power off machine#1 -> detach the board from the machine#1 -> power on machine#1 and use machine#1 to program the FPGA -> power off machine#1 while keep the power of FPGA on -> plug in FPGA to machine#1 -> power on machine#1.

After doing the above, we can see that the Altera device show up in the output of
Code:
lspci | grep altera
When we typed lsmod, we can also see that altera_dma is loaded.

Unfortunately, when we install the software part of the ref design by sudo ./install, it always complain that chmod: /dev/altera_dma: No such directory of file. Executing ./run also failed because the device couldn't be found.

I found another thread on this forum (https://www.alteraforum.com/forum/sh...ad.php?t=54886) talking about a similar situation (the difference is that his board was a StratixV), but following the workaround there didn't help in my case.

At this point, I am not sure what to do to make this reference design work. Could anyone please give me some help? Any suggestion or hint is much appreciated!

Thank you very much!
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Arria 10 Dev Kit: unable to connect to ethernet as instructed in Quick Start Guide

November 1, 2017, 9:11 pm
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Hi all,

We've just received a new Arria 10 GX FPGA Dev Kit. As the first step, we try to follow Quick Start Guide (https://www.altera.com/content/dam/a...ga_dev_kit.pdf) and connect to the board's Board Upgrade Portal. Unfortunately, we failed at Step 1. As instructed on the document, we power off the board, switch SW6.4 to ON position to load factory design (Step 1.1), and connect ethernet cable to the board (Step 1.2), and power it on (Step 1.3). As described in Step 1.3, we should be able to see the board showing "Connecting" on the LCD display, and, when an IP address is obtained, showing the IP address. However, after powering on the board, we saw nothing on the LCD display. We put it there for 30 minutes and nothing showed up.

Have anyone had a similar experience? Does anyone have any clue how to fix this? Any suggestion is much appreciated!
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De-coupling capacitors recommendation for Cyclone 10 FPGA

November 1, 2017, 9:57 pm
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Hi,

We are planning to use 10CL016YU484C8G part in our design. We do not see any recommendation regarding number and values of de-coupling capacitors for each supply in the device datasheet. Can you please let us know the recommended values and number of de-coupling capacitors required for each power supply?

In our design, we have provided a 0.1µF capacitor for each supply pin. In addition to this, we have provided a 47µF capacitor for VCCINT supply and a 4.7µF for VCCD_PLL, VCCCA and each VCCO supplies. Please let us know if this is fine.

Regards
Raja
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local memory and private memory size?

November 1, 2017, 11:01 pm
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NDRange setting
WorkSize[3] = {56, 56, 96}
WorkGroupSize[3] = {14, 14, 1}


I would like to copy data from global memory to work group as local memory.
I also want to copy some data from global memory to work item private memory.
I don't know how many local memory I can create?
How to check how many local/private memory I can use?


The FPGA board is a10gx.


Thanks,
Matt
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windrvr6.sys lead to blue Screen

November 1, 2017, 11:30 pm
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I am implementing Support Vector Machine(SVM) predict function on de5net_a7 but I have some problem that the program will lead blue screen on win10 and win7 system,
The OpenCL program working properly on GPU，and the sdk can generate .aocx file，my SDK version is 16.1，how can i solve this problem. Thank you very much.

This is my kernel code:
Code:
#define GSIZE 64
__attribute__((num_simd_work_items(4)))
__attribute__((reqd_work_group_size(1,1,64)))
__kernel void classification(__global uchar * restrict textures, __global uchar * restrict SVS,  __global float * restrict alphas,
                    float gamma,__global float * restrict result)
{
    uint gidx = get_global_id(0);    //img_w
    uint gidy = get_global_id(1);    //img_h
    uint gidz = get_global_id(2);    //sv_num
    int img_w = get_global_size(0);
    uint lid = get_local_id(2);    //64
    uint group_size_z = get_num_groups(2);
    uint group_id_z = get_group_id(2);
    __local uchar texture[90];
    __local float alpha_local[GSIZE];
    __local float res[GSIZE];
    __local float gamma_local;
    if(lid==0){
        gamma_local = gamma;
        #pragma unroll
        for(int i=0;i<90;i++){
            texture[i] = textures[(gidy*img_w+gidx)*90+i];
            if(i<GSIZE){
                alpha_local[i] = alphas[group_id_z*GSIZE+i];
            }
        }
    }
    barrier(CLK_LOCAL_MEM_FENCE);
    int temp = 0;
    int i=0;
    #pragma unroll
    for(i=0;i<86;i+=4){
        int t0 = SVS[gidz*90+i]-texture[i];
        int t1 = SVS[gidz*90+i+1]-texture[i+1];
        temp += t0*t0+t1*t1;
        t0 = SVS[gidz*90+i+2]-texture[i+2];
        t1 = SVS[gidz*90+i+3]-texture[i+3];
        temp += t0*t0+t1*t1;
    }
    #pragma unroll
    for(;i<90;i++){
        int t0 = SVS[gidz*90+i]-texture[i];
        temp += t0*t0;
    }
    res[lid] = alpha_local[lid]*exp(-1*gamma_local*(float)temp);
    barrier(CLK_LOCAL_MEM_FENCE);
    if(lid==0){
        float sum=0;
        #pragma unroll
        for(int i=0;i<GSIZE-3;i+=4){
            sum += res[i];
            sum += res[i+1];
            sum += res[i+2];
            sum += res[i+3];
        }
        result[(gidy*img_w+gidx)*group_size_z+group_id_z] = sum;
    }
}
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