Max10: 10M16DAF256I7G ADC not working

November 2, 2017, 1:33 am

≫ Next: Why Quartus Prime Standard Edition ignores XCVR_REFCLK_PIN_TERMINATION assignment

≪ Previous: windrvr6.sys lead to blue Screen

Hi

I'm having trouble with on chip ADC from Max10 10M16DAF256IG7. I create an "ADC control only" using Qsys (PLL included) and monitor the signals using Signaltap. However I do not get any "adc_response_valid" on Signaltap. I tried a very similar code with DECA evaluation board (10M50DAF484C6) and it works fine. I understand that DECA evaluation board has Dual ADCs, while the 10M16DAF256 has only a single ADC. I did modify the ADC module in Qsys to fit the 10M16DAF256, but it does not work.

Attach is my project design.
Some helps on this problem please.

Thanks

Attached Files

adc.zip (144.2 KB)

↧

Why Quartus Prime Standard Edition ignores XCVR_REFCLK_PIN_TERMINATION assignment

November 2, 2017, 2:29 am

≫ Next: Quartus Crash

≪ Previous: Max10: 10M16DAF256I7G ADC not working

Hi,
I am trying to find error in design using Arria 10 transceivers and during the analysis of the Fitter report I found, that according to the ignored Assignments sheet, all XCVR_REFCLK_PIN_TERMINATION were ignored.

The ignored assignment from QSF file:
set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to clock_ref_135_mhz

Other assignment for the clock:
set_location_assignment PIN_L22 -to clock_ref_135_mhz
set_location_assignment PIN_L21 -to "clock_ref_135_mhz(n)"
set_instance_assignment -name IO_STANDARD LVDS -to clock_ref_135_mhz

Device assignment:
set_global_assignment -name DEVICE 10AX016E4F27E3SG

Pins L22 and L21 corresponds the transceiver reference clock.

If I use different value than AC_COUPLING than assignment is processed (do not appear in ignored assignments report). I tried to specify the assignment through both Pin planner or QSF file and both cases behaves in the same way.

I would like to know, why is the XCVR_REFCLK_PIN_TERMINATION ignored?

Thank you very much
Jan

↧

Quartus Crash

November 2, 2017, 2:58 am

≫ Next: Launch Transceiver Toolkit using tcl

≪ Previous: Why Quartus Prime Standard Edition ignores XCVR_REFCLK_PIN_TERMINATION assignment

Any suggestions? Of course I tried to delete /db and /incremental_db. The result is still the same

Quote:

Problem Details
Error:
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen5_phyclk_av.cpp, Line: 469
pll_lvds_output_atom && pll_lvds_output_atom->is_pll_lvds_output()
Stack Trace:
0x81dac: EMIF_GEN5_PHYCLK_AV::create_design + 0x3b4 (periph_emif)
0xfa88: PCC_ENV_IMPL::perform_op + 0x2ac (periph_pcc)
0xf746: PCC_ENV_IMPL::create_design + 0xda (periph_pcc)
0x2eab9: FSV_PERIPHERY_PLACEMENT_UTIL::do_auto_promote_io_s td + 0xd9 (fitter_fsv)
0x21920: FSV_EXPERT::auto_promote_io_std_and_create_complem ent_pins + 0x50 (fitter_fsv)
0x2570d: FSV_EXPERT::fitter_preparation_pre_fpp + 0xc9d (fitter_fsv)
0x238e6: FSV_EXPERT::fitter_preparation + 0x26 (fitter_fsv)
0x1dfff: FSV_EXPERT_BASE::fitter_preparation_run_family_fit ter_preparation + 0x4f (fitter_fsv)
0x1daf8: FSV_EXPERT_BASE::fitter_preparation + 0x68 (fitter_fsv)
0x1e750: FSV_EXPERT_BASE::invoke_fitter + 0x3b0 (fitter_fsv)
0x1c872: fsv_execute + 0x22 (fitter_fsv)
0xe900: fmain_start + 0x900 (FITTER_FMAIN)
0x41b1: qfit_execute_fit + 0x1bd (comp_qfit_legacy_flow)
0x5384: QFIT_FRAMEWORK::execute + 0x2a0 (comp_qfit_legacy_flow)
0x267f: qfit_legacy_flow_run_legacy_fitter_flow + 0x1c7 (comp_qfit_legacy_flow)
0x14410: TclInvokeStringCommand + 0xf0 (tcl86)
0x161e2: TclNRRunCallbacks + 0x62 (tcl86)
0x17a65: TclEvalEx + 0xa65 (tcl86)
0xa6f8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
0xa5646: Tcl_EvalFile + 0x36 (tcl86)
0x12606: qexe_evaluate_tcl_script + 0x376 (comp_qexe)
0x11864: qexe_do_tcl + 0x334 (comp_qexe)
0x16755: qexe_run_tcl_option + 0x585 (comp_qexe)
0x380c3: qcu_run_tcl_option + 0x1003 (comp_qcu)
0x160aa: qexe_run + 0x39a (comp_qexe)
0x16e51: qexe_standard_main + 0xc1 (comp_qexe)
0x2233: qfit2_main + 0x73 (quartus_fit)
0x12d68: msg_main_thread + 0x18 (CCL_MSG)
0x1454e: msg_thread_wrapper + 0x6e (CCL_MSG)
0x15b00: mem_thread_wrapper + 0x70 (ccl_mem)
0x12631: msg_exe_main + 0xa1 (CCL_MSG)
0x287e: __tmainCRTStartup + 0x10e (quartus_fit)
0x13d1: BaseThreadInitThunk + 0x21 (KERNEL32)
0x154f3: RtlUserThreadStart + 0x33 (ntdll)

End-trace

Executable: quartus_fit
Comment:
None

System Information
Platform: windows64
OS name: Windows 8.1
OS version: 6.3

Quartus Prime Information
Address bits: 64
Version: 17.0.2
Build: 602
Edition: Lite Edition

↧

Launch Transceiver Toolkit using tcl

November 2, 2017, 3:31 am

≫ Next: DE0-NANO Pin Out Voltage Warning

≪ Previous: Quartus Crash

Hi,

I am new to Quartus software. Is there any possible way to launch the transceiver toolkit GUI using tcl script without using the Quartus GUI? I can only launch the System Console using tcl shell. Or is there any tcl command in System Console for me to launch the transceiver toolkit?

Thanks.

↧

DE0-NANO Pin Out Voltage Warning

November 2, 2017, 6:29 am

≫ Next: Multi kernel function local memory resource

≪ Previous: Launch Transceiver Toolkit using tcl

Hallo

I am using DE0-NANO board for my project and i get the following warning from the pin out voltage. I am using 3.3 V LVTTL for all the pins and 8 mA
I am attaching my pin out file.

Warning (169177): 6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces.
Info (169178): Pin clk_enable uses I/O standard 3.3-V LVTTL at N9
Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at R8
Info (169178): Pin reset uses I/O standard 3.3-V LVTTL at E1
Info (169178): Pin BCLK uses I/O standard 3.3-V LVTTL at B7
Info (169178): Pin WS uses I/O standard 3.3-V LVTTL at A7
Info (169178): Pin Input uses I/O standard 3.3-V LVTTL at C8

This warning doesn't have any effect on the complitation, i am just concerned if it has any effect on the hardware i am connecting to. The input coming from my external hardware to development board GPIO pins are 3.3 V LVTTL

Attached Files

pinout.zip (1,002 Bytes)

↧

Multi kernel function local memory resource

November 2, 2017, 7:47 am

≫ Next: I_USB_ULPI_CLK of HPS atom "~GND" must be connected to a top-level pin

≪ Previous: DE0-NANO Pin Out Voltage Warning

I would like to implement CNN using OpenCL and run on FPGA.
The CNN implementation will contain 4 kernel function
layer1_kernel, supposed allocate 1 MB local memory
layer2_kernel, supposed allocate 1 MB local memory
layer3_kernel, supposed allocate 1 MB local memory
layer4_kernel, supposed allocate 1 MB local memory

Host program will call clEnqueueNDRangeKernel() function in sequence.
that is, pervious kernel need finished, then the next kernel will be enqueued.

What is the total RAM block resource to be used?
4MB or 1MB?

Thanks,
Matt

↧

I_USB_ULPI_CLK of HPS atom "~GND" must be connected to a top-level pin

November 2, 2017, 11:05 am

≫ Next: Incomplete list of devices in Convert Programming File

≪ Previous: Multi kernel function local memory resource

Hello!

I'm getting the error that the I_USB_ULPI_CLK port of the "HPS atom" "~GND" needs to be connected to a top-level pin. My problem is ... I can't seem to find this port anywhere in my design to know how to adjust its connectivity. Can anyone tell me what I'm missing?

I'm attaching a picture of the error message, as well as my top-level SOC.v file.

Thanks!

Dan

Attached Images

ulp.jpg (20.5 KB)

Attached Files

sockit_top.v (12.5 KB)

↧

Incomplete list of devices in Convert Programming File

November 2, 2017, 11:18 am

≫ Next: Registers in I/O cells

≪ Previous: I_USB_ULPI_CLK of HPS atom "~GND" must be connected to a top-level pin

Hi folks,

Can someone tell me why I don't have all the usual devices when choosing for the Flash Loader in the "Convert Programming File" window? (See screenshot 1)

If I go in "Add device" in the programmer, you will see that the list is more complete. I specifically need the "EP4CGXCF23", as otherwise it says: (See screenshot 2)

Code:

Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID.

Thank you in advance,

Carl

Attached Images

Capture.jpg (19.3 KB)
Capture2.jpg (19.3 KB)

↧

Registers in I/O cells

November 2, 2017, 12:21 pm

≫ Next: Error in Modulesim verilog

≪ Previous: Incomplete list of devices in Convert Programming File

Most Altera families have register(s) in the I/O cells. Obviously if I want full control of the plumbing I can instantiate the 'GPIO Lite' IP core and do everything explicitly, but I thought that for simple cases the tools would spot a signal coming in on a pin going straight to a register and use the register in the I/O rather than using up an LE.

However, with my current design it isn't doing that - the fitter resource report says "I/O registers 0/863 (0%)", and looking at the Technology Map viewer I can see my signals coming in through an "IO_IBUF" and then getting latched in a LE.

I'm currently working with MAX10 and Quartus Prime 17.0.2 Lite edition (design in VHDL), but I thought I'd seen this working in earlier projects (with Cyclone2/3 and much older versions of Quartus).

Am I missing a setting somewhere, or does this feature not exist?

↧

Error in Modulesim verilog

November 2, 2017, 11:20 pm

≫ Next: DE0 board EEPROM

≪ Previous: Registers in I/O cells

my program is compile successfully without saving but when i save the project transcript shows error unexpected integers error

module auto_segment
(output [6:0]hex 0,input clk);
integer count;
always@(posedge clk);
begin
if(count<9)
count<=count+1;
else
count<=0;
end
endmodule

↧

DE0 board EEPROM

November 2, 2017, 11:30 pm

≫ Next: Interrupts from HPS peripherals

≪ Previous: Error in Modulesim verilog

Hi,
can anyone plz tell me how to remove a program from the EEPROM of the FPGA on the DE0 board (erase the EEPROM content). The EEPROM seems to be not configuring but having stuck with one program causing the FPGA to generate the same output even when different programs are being loaded to it everytime. The EDA tool used is Quartus II v13.1.
Thanks :)

↧

Interrupts from HPS peripherals

November 3, 2017, 3:41 am

≫ Next: Example design producing errors

≪ Previous: DE0 board EEPROM

Board : DE-10 ( Cyclone V SoC )
OS : FreeRTOS

Hi, I'm writing a driver for FreeRTOS+TCP stack. I configured the EMAC1 and DMA peripherals.
At this moment, everything works fine, except that I don't get any interrupt from EMAC1.
So for the moment I poll the EMAC and DMA status bits. I see them come high, and I can clear them by writing 1's.

What I did is :

● Program the GIC to enable interrupt 152 ( ALT_INT_INTERRUPT_EMAC1_IRQ )
● Set the handler + data
● Set a priority and trigger level
● program the peripheral ( EMAC interrupt mask reg 15, and EMAC/DMA interrupt enable DMA register 7 )

As a test, I tried to get interrupt from UART-0. The device works fine, but I don't see interrupts neither.

The only interrupt that does work is interrupt 29 ( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE ). That timer is used to get a FreeRTOS system clock.

I asked the same question on the FreeRTOS forum, but without success.
See https://sourceforge.net/p/freertos/d...limit=250#d738

Thanks.

↧

Example design producing errors

November 3, 2017, 7:21 am

≫ Next: DE10 pins not found

≪ Previous: Interrupts from HPS peripherals

Hi everyone,

I downloaded several example designs from altera.com. I have the intelFPGA_pro 17.0 suite installed on my machine.
Compiling and running hello_world and vector_addition was ok.
As I am more interested in doing some HDL library, I tried the fourth example : OpenCL_library (to be found here).
I followed strictly the README.html. Producing double_lib.aoclib went ok. But when I tried to get the .aocx with

Code:

aoc device/example1.cl -o bin/example1.aocx -I device/lib1 -L device -l double_lib.aoclib

, the synthesis failed after some time (approx. 1 hour). I attached the quartus_sh_compile.log as I found some error in it but if you think another log file is worth some attention let me know.
The first error I encountered was:

Code:

Error (13661): VHDL Association List error at i_sfc_logic_c0_entry_test_builtin_c0_enter31.vhd(187): formal "reset_kind" does not exist File: /home_nfs/bourgea/project/xpress_rtl_lib1/library_example1/bin/example1/ip/kernel_system/kernel_system_example1_system/example1_system_140/synth/i_sfc_logic_c0_entry_test_builtin_c0_enter31.vhd Line: 187

The same error is repeated quite some times on other lines and other files. They all concern some

Code:

formal "reset_kind" does not exist

How can I fix this error ?

IMHO, this is not a huge bug but a design example not working out of the box is concerning.

some details about my tools :

Code:

$ aoc --version

Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler

Version 17.0.0 Build 290

Attached Files

quartus_sh_compile.log.txt (257.2 KB)

↧

DE10 pins not found

November 3, 2017, 2:52 pm

≫ Next: De-coupling capacitors recommendation for Cyclone 10 FPGA

≪ Previous: Example design producing errors

Hello,

I'm trying to build my first DE10 Nano design, and getting some critical fitter warnings that make no sense to me. Specifically, I get the "warning" that, "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details." Then I get the critical warning that, "No exact pin location assignment(s) for 75 pins of 138 total pins. ..." If I look up the "undefined" pins, many of them are HPS_DDR3xxx pins. If I try to assign these pins within the pin editor, I cannot. Instead, they have default locations (matching the schematic) that cannot be changed. There are other warnings as well, indicating that perhaps the DDR3 SDRAM wasn't set up properly, although at this point I have no idea what I might have missed.

I've attached both my top level file, as well as the fit report showing the various I/O errors and warnings I've been receiving.

Any suggestions?

Dan

Attached Files

fit.rpt.zip (77.5 KB)
sockit_top.v (12.3 KB)

↧

De-coupling capacitors recommendation for Cyclone 10 FPGA

November 1, 2017, 9:57 pm

≫ Next: local memory and private memory size?

≪ Previous: DE10 pins not found

Hi,

We are planning to use 10CL016YU484C8G part in our design. We do not see any recommendation regarding number and values of de-coupling capacitors for each supply in the device datasheet. Can you please let us know the recommended values and number of de-coupling capacitors required for each power supply?

In our design, we have provided a 0.1µF capacitor for each supply pin. In addition to this, we have provided a 47µF capacitor for VCCINT supply and a 4.7µF for VCCD_PLL, VCCCA and each VCCO supplies. Please let us know if this is fine.

Regards
Raja

↧

local memory and private memory size?

November 1, 2017, 11:01 pm

≫ Next: windrvr6.sys lead to blue Screen

≪ Previous: De-coupling capacitors recommendation for Cyclone 10 FPGA

NDRange setting
WorkSize[3] = {56, 56, 96}
WorkGroupSize[3] = {14, 14, 1}

I would like to copy data from global memory to work group as local memory.
I also want to copy some data from global memory to work item private memory.
I don't know how many local memory I can create?
How to check how many local/private memory I can use?

The FPGA board is a10gx.

Thanks,
Matt

↧

windrvr6.sys lead to blue Screen

November 1, 2017, 11:30 pm

≫ Next: Max10: 10M16DAF256I7G ADC not working

≪ Previous: local memory and private memory size?

I am implementing Support Vector Machine(SVM) predict function on de5net_a7 but I have some problem that the program will lead blue screen on win10 and win7 system,
The OpenCL program working properly on GPU，and the sdk can generate .aocx file，my SDK version is 16.1，how can i solve this problem. Thank you very much.

This is my kernel code:

Code:

#define GSIZE 64
__attribute__((num_simd_work_items(4)))
__attribute__((reqd_work_group_size(1,1,64)))
__kernel void classification(__global uchar * restrict textures, __global uchar * restrict SVS,  __global float * restrict alphas,
                    float gamma,__global float * restrict result)
{
    uint gidx = get_global_id(0);    //img_w
    uint gidy = get_global_id(1);    //img_h
    uint gidz = get_global_id(2);    //sv_num
    int img_w = get_global_size(0);
    uint lid = get_local_id(2);    //64
    uint group_size_z = get_num_groups(2);
    uint group_id_z = get_group_id(2);
    __local uchar texture[90];
    __local float alpha_local[GSIZE];
    __local float res[GSIZE];
    __local float gamma_local;
    if(lid==0){
        gamma_local = gamma;
        #pragma unroll
        for(int i=0;i<90;i++){
            texture[i] = textures[(gidy*img_w+gidx)*90+i];
            if(i<GSIZE){
                alpha_local[i] = alphas[group_id_z*GSIZE+i];
            }
        }
    }
    barrier(CLK_LOCAL_MEM_FENCE);
    int temp = 0;
    int i=0;
    #pragma unroll
    for(i=0;i<86;i+=4){
        int t0 = SVS[gidz*90+i]-texture[i];
        int t1 = SVS[gidz*90+i+1]-texture[i+1];
        temp += t0*t0+t1*t1;
        t0 = SVS[gidz*90+i+2]-texture[i+2];
        t1 = SVS[gidz*90+i+3]-texture[i+3];
        temp += t0*t0+t1*t1;
    }
    #pragma unroll
    for(;i<90;i++){
        int t0 = SVS[gidz*90+i]-texture[i];
        temp += t0*t0;
    }
    res[lid] = alpha_local[lid]*exp(-1*gamma_local*(float)temp);
    barrier(CLK_LOCAL_MEM_FENCE);
    if(lid==0){
        float sum=0;
        #pragma unroll
        for(int i=0;i<GSIZE-3;i+=4){
            sum += res[i];
            sum += res[i+1];
            sum += res[i+2];
            sum += res[i+3];
        }
        result[(gidy*img_w+gidx)*group_size_z+group_id_z] = sum;
    }
}