December 27, 2017, 6:57 am
Hi,
I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit.
But I want to simulation autogenerated verilog code which get after compilation. Simulation with Questa Sim.
I added all files from project (which generated by OpenCL FPGA compiler), from BSP too.
But QuestaSim get this error
Module 'twentynm_fp_mac_encrypted' is not define.
I can't find this module. Not in proj, not in BSP,not in Quartus. Can you tell me how can I solve this probem ?
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December 27, 2017, 2:28 am
Hello,
I have downloaded precompiled SD image for DE0-nano-soc devkit from terasic site, linux kernel ver: 3.13.0-00298-g3c7cbb9-dirty
Now I am trying to compile my custom driver for this linux.
I have cloned altera sources:
Do you know which kernel sources I need for this linux?
Quote:
linux-socfpga # git tag -l rel*
rel_12.12
rel_13.02_RC1
rel_13.02_RC10
rel_13.02_RC2
rel_13.02_RC3
rel_13.02_RC4
rel_13.02_RC5
rel_13.02_RC6
rel_13.02_RC7
rel_13.02_RC8
rel_13.02_RC9
rel_13.07_RC0
rel_13.07_RC1
rel_13.07_RC2
rel_13.07_RC3
rel_13.07_RC4
rel_13.07_RC5
rel_ghrd_RC1
rel_ghrd_RC10
rel_ghrd_RC2
rel_ghrd_RC3
rel_ghrd_RC4
rel_ghrd_RC5
rel_ghrd_RC6
rel_ghrd_RC7
rel_ghrd_RC8
rel_ghrd_RC9
rel_socfpga-3.10-ltsi_arria10_bringup_gsrd_ies
rel_socfpga-3.10-ltsi_arria10_bringup_ies
rel_socfpga-3.13-rel14.0_14.06.01
rel_socfpga-3.13-rel14.0_14.06.02
rel_socfpga-3.13-rel14.0_14.07.01
rel_socfpga-3.13_14.02.02
I have tried one of 3.13* but my driver's version is:
Quote:
vermagic: 3.13.0-00299
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December 27, 2017, 4:39 pm
I have two standalone fpga board.
I want force one board to send specific signal and hold about 10 sec and another board sample the incoming signal .
I have writen two jam files and work correctly at each board.
But when I open two cmd consoles and run two quartus_jli at each console.
The quartus_jli at second console is always blocked till the quartus_jli at first console finished it's job.
Are there any paramerters to make quartus_jli not block each other?
Or is the only way can work that to make a jtag daisy chain of two devices?
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December 27, 2017, 9:14 pm
Dear experts,
Now I am facing with a hardware issue on writing encription. When I wrote a non-volatile encription key with ekp-file to Arria10 device, it caused writing failure on Programmer. After that, I checked port status, and found TDO was always 1.8V, Vcc for JTAG.
Since TDO was always remained as 1.8V, I couldn't use JTAG port.
Once I used the target ekp-file for another device, and it worked correctly.
I revised file-name only for the ekp-file on this time.
Does anyone have any idea about such an issue?
Thanks,
Tetsuya
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December 28, 2017, 12:31 am
Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
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December 28, 2017, 12:46 am
Hi,
I want to make my own software to transfer datas from PC to FPGA using USB-Blaster II.
Can I make software using CyUSB SDK? I already checked my blaster ii by making simple c# project.
But device (blaster ii) is not recognized. USB control center software in SDK also couldn't find blaster device.
Anybody try this?
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December 28, 2017, 2:18 am
Hi,
In my application I will need implement high order (4), IIR, Butterworth, Low Pass filter, with cutoff frequency (-3dB) of ~1Hz and stop band of ~10Hz, with attenuation of -80dB. The input signal is sampled at rate of ~50ksps (32bits/sample).
The problem is that I need to select the right FPGA (Cyclone V) according to the filter resources. I haven't purchase yet the DSP builder (It takes time
) and the Simulink HDL coder but I can't delay the FPGA selection (will implemented on a costume board).
How can I estimate the resources to the IIR filter on those circumstances? I tried thought MATLAB filter editor and even managed to create some kind of VHDL code but I dont have the relationship to ALTERA hardware (the "FPGA automation" tab is shut).
Thanks a lot,
Idan
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December 28, 2017, 4:33 am
Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
↧
December 28, 2017, 4:55 am
Hi,
I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit.
But I want to simulation autogenerated verilog code which get after compilation. Simulation with Questa Sim.
I added all files from project (which generated by OpenCL FPGA compiler), from BSP too.
But QuestaSim get this error
Module 'twentynm_fp_mac_encrypted' is not define.
I can't find this module. Not in proj, not in BSP,not in Quartus. Can you tell me how can I solve this probem ?
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December 23, 2017, 11:07 pm
Dear,
I have a procedure (Sort) that read two numbers in each cycle. and return the max and the min. I am reading two numbers from mif file , the problem is that I want to write back the result returned from the PROCEDURE to the same location of the memory that I had read from. I expected it to be in the next cycle but the memory is not able to be inferred " can't infer memory for variable 'ram1' with attribute '"M4K"'. I listed the code below as reference. Many thanks.
ARCHITECTURE behave OF min_max IS
TYPE MEM IS ARRAY(0 TO 15) OF signed(9 DOWNTO 0);
signal ram1:MEM;
ATTRIBUTE ram_init_file: STRING;
ATTRIBUTE ram_init_file OF ram1: SIGNAL IS "bits.mif";
ATTRIBUTE ramstyle: STRING;
ATTRIBUTE ramstyle OF ram1: SIGNAL IS "M4K";
SIGNAL reg1sig,reg2sig,dataodd,dataeven,minsig,maxsig: signed(9 downto 0);
BEGIN
PROCESS (clock)
variable kk:integer range 0 to 7:=0;
BEGIN
IF rising_edge(clock) THEN
dataodd <= ram1(2*kk+1);
dataeven<=ram1(2*kk);
reg1sig<=dataodd;
reg2sig<=dataeven;
Sort(Reg1sig,reg2sig,maxsig,minsig); -- THE PROCEDURETAKES TWO NUMBERS AND RETURN TWO , IT WORKS WELL WITHOUT WRITING TO RAM1
ram1(2*kk+1) <= maxsig;
ram1(2*kk)<= minsig;
kk:=kk+1;
END IF;
OUT<=maxsig;
END PROCESS;
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December 28, 2017, 11:05 am
Dear Experts!
I'm developing a prototype device based on SoC Cyclone V, developed the circuit, layout the board, assembled the prototype, launched DDR3, SD. Prior to this, the FPGA project worked on debug board (DeoNano). Rested in Linux, or rather in the Ethernet part. Collected the kernel 3.11 ltsi, enabled CMA, compiled. I corrected dtb, ubut, rolled on the card according to the standard method. The kernel is loaded and i see eth0 is active (9031 Micrel is installed on it), its all: ... no way - the Ethernet does not get up.) I'm sinning on my motherboard. Returning to DeoNano. I'm still doing the same thing on rgmii1, I'm quiet again.What to do with a linux core to raise mikrel? I hope for your help.
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December 24, 2017, 10:31 am
Background : I have no prior experience in FPGA SoC or FPGA or CPLD however I have worked extensively on Raspberry Pi 3 Model B (Raspbian OS) and ARM M4 micro-controller (Bare Metal Programming).
I have a difficulty choosing between DE10-Nano Kit vs DE0-Nano-SoC Kit/Atlas-SoC Kit. All the difference I could find is in SoC and HDMI which is only output present in DE10-Nano Kit.
The difference I found out in SoC was 110K Logic Element (DE10-Nano Kit) vs 40K Logic Element (DE0-Nano Kit) and presence of 1 hard memory controller (DE0-Nano Kit) against no hard memory controller (DE10-Nano Kit). I have no idea how any of this will affect me and what would be their implications.
I plan to use Verilog HDL due to its relatedness to C/C++ (which I am familiar with).
I ultimately plan use this board fuzzy logic controller implementation, machine learning and machine vision.
I request experts to guide me in selection of appropriate board.
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December 24, 2017, 11:24 am
Hii Everyone,
I am using Quartus Prime Design suite 15.1.
I wrote a behavioral verilog code. When I compile it and see its netlist using Tools->netlist viewer->RTL viewer, I see the code is realized using some random gates and decoder logic.
I wanted to implement the logic only using 2:1 Mux. Is there any setting to do that.
Thank you,
Surya
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December 25, 2017, 6:51 am
Hi. I want create a TCL script which will be write into log file after compilation current revision of a project, current timestamp, current active signaltap file name and current revision ID. I have try get current signal tap file name with command
Code:
set stp [get_assignment_info [get_all_assignments -type global -name signaltap_file] - valie]
This command work correctly if I run it TCL shell in Quartus II window, but I have error when run this command in script as POST_FLOW_SCRIPT_FILE:
You must open a project before you can use this command.
Thanks for help.
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December 26, 2017, 6:51 am
Hello All!
I have a new design with Cyclone 10 LP family. I would like power the VCCA pins to 3,3V, but is not clear to me if it's possible.
In the "Cyclone 10 LP datasheet", C10LP51002 Table 1, says "Absolute Maximum .." for VCCA 3.75V.
In the "Cyclone 10 LP Pin Connection Guidelines", PCG-01021 Table 5, says "VCCA[1..4] You are required to connect these pins to 2.5 V, even if the PLL is not used...".
The question is, It's allowed connect VCCA to 3,3V?.
Thanks in advance.
Peio
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December 26, 2017, 7:36 am
Hello all,
Can anyone please tell me from where to find some of the sample examples/projects of Intel HLS compiler ?
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December 26, 2017, 10:03 am
Hi, I require clocks with different phase shifts. Theoretically, the outputs at each stage of the buffers in the buffer chain of DLL in ALTDLL megafunction should do it. However, ALTDLL outputs only dll_delayctrlout and the buffer clock outputs are not available. Is there any way to access them? Thanks.
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December 26, 2017, 10:58 am
I've just installed the QUARTUS II, and i am trying to run a simulation because i'm receiving the message below, can i have help solving this please? thanks
Device family: MAX7000S
Running quartus eda_testbench
>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test {--vector_source=C:/Users/tracy/Documents/test/Waveform.vwf} {--testbench_file=./simulation/qsim/test.vt}
PID = 8580
************************************************** *****************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Processing started: Tue Dec 26 18:51:19 2017
Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test --vector_source=C:/Users/tracy/Documents/test/Waveform.vwf --testbench_file=./simulation/qsim/test.vt
Generated Verilog Test Bench File ./simulation/qsim/test.vt for simulation
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Peak virtual memory: 375 megabytes
Processing ended: Tue Dec 26 18:51:21 2017
Elapsed time: 00:00:02
Total CPU time (on all processors): 00:00:02
Running quartus eda_func_netlist
>> quartus_eda --functional=on --simulation --tool=modelsim_oem --format=verilog test -c test
PID = 14608
************************************************** *****************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Processing started: Tue Dec 26 18:51:22 2017
Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog test -c test
Generated file test.vo in folder "C:/Users/tracy/Documents/test/simulation/modelsim/" for EDA simulation tool
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Peak virtual memory: 375 megabytes
Processing ended: Tue Dec 26 18:51:23 2017
Elapsed time: 00:00:01
Total CPU time (on all processors): 00:00:02
************************************************** *****************
Running quartus modelsim
>> vsim -c -do test.do
PID = 9300
Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl
# 10.1d
# do test.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module test
#
# Top level modules:
# test
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module test_vlg_sample_tst
# -- Compiling module test_vlg_check_tst
# -- Compiling module test_vlg_vec_tst
#
# Top level modules:
# test_vlg_vec_tst
# vsim -L max7000s_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.test_vlg_vec_tst
# Loading work.test_vlg_vec_tst
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(71): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(84): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(97): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(123): Instantiation of 'max_mcell' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(148): Instantiation of 'max_mcell' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(160): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(173): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test_vlg_sample_tst
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test_vlg_check_tst
# Error loading design
↧
December 27, 2017, 1:36 am
Im new using Altera boards I have two questions.
I check the Quartus_II_Introduction for verilog users. On the programming chapter it says that "DE0-CV, DE0-Nano and DE2-115 Boards" should have a RUN/PROG switch.
1.-Does the cyclone V GT FPGA board has such switch?
2.-Also where can I find the pin assignments for this board?
Thank you
↧
December 27, 2017, 2:28 am
Hello,
I have downloaded precompiled SD image for DE0-nano-soc devkit from terasic site, linux kernel ver: 3.13.0-00298-g3c7cbb9-dirty
Now I am trying to compile my custom driver for this linux.
I have cloned altera sources:
Do you know which kernel sources I need for this linux?
Quote:
linux-socfpga # git tag -l rel*
rel_12.12
rel_13.02_RC1
rel_13.02_RC10
rel_13.02_RC2
rel_13.02_RC3
rel_13.02_RC4
rel_13.02_RC5
rel_13.02_RC6
rel_13.02_RC7
rel_13.02_RC8
rel_13.02_RC9
rel_13.07_RC0
rel_13.07_RC1
rel_13.07_RC2
rel_13.07_RC3
rel_13.07_RC4
rel_13.07_RC5
rel_ghrd_RC1
rel_ghrd_RC10
rel_ghrd_RC2
rel_ghrd_RC3
rel_ghrd_RC4
rel_ghrd_RC5
rel_ghrd_RC6
rel_ghrd_RC7
rel_ghrd_RC8
rel_ghrd_RC9
rel_socfpga-3.10-ltsi_arria10_bringup_gsrd_ies
rel_socfpga-3.10-ltsi_arria10_bringup_ies
rel_socfpga-3.13-rel14.0_14.06.01
rel_socfpga-3.13-rel14.0_14.06.02
rel_socfpga-3.13-rel14.0_14.07.01
rel_socfpga-3.13_14.02.02
I have tried one of 3.13* but my driver's version is:
Quote:
vermagic: 3.13.0-00299
↧