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Altera cyclone 5 is not booting from spi

December 27, 2017, 2:52 am
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​I created one uart program in quatux 2,i added uart in qsys,on chip memor and serial flash loader .i compiled it in quarux 2 .it succesfully compiled.when i opening this project in nios and create new BSP than following error coming......
"entry section mapping not created because reset memory region not located at base address 0x1011040."
"the section mapping entry is missing. and required linker section mapping do not exists."

i selected reset vector field serial flash loader and for exception i selected on chip memory.

can anyone help me,how tio solve this problem.

thank you
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External SPI master clock connect to CPLD global clock network ?

December 27, 2017, 4:56 am
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When using SPI communication, where a CPLD is acting as the slave and a microcontroller is the master, would the SPI clock (SCK) be connected to a global clock network of the CPLD? I.e. one of the CLK ports (labelled with a falling edge in the Quartus pin planner) ?
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NIOS II Command Shell not working

December 27, 2017, 5:31 am
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Excuse me if I this is a dumb question I am brand new at trying to use the NIOS II SBT. I am running Quartus Prime 17 on Windows 10 and keep getting an error when trying to open the software build tools for NIOS II. I did not know if this was because it was on windows 10. https://www.altera.com/support/suppo...s-support.html
It was working the other day though, and I have tried multiple times to uninstall and re download Quartus. I found a workaround to open it by running the eclipse-nios2.exe file which then opens this (shown in the attached image) up.
I don't want to continue my work for no reason.
Thanks for any help
Attached Images
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Simulation problem with autogenerate verilog code

December 27, 2017, 6:57 am
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Hi,
I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit.
But I want to simulation autogenerated verilog code which get after compilation. Simulation with Questa Sim.

I added all files from project (which generated by OpenCL FPGA compiler), from BSP too.

But QuestaSim get this error
Module 'twentynm_fp_mac_encrypted' is not define.

I can't find this module. Not in proj, not in BSP,not in Quartus. Can you tell me how can I solve this probem ?
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How to run two quartus_jli without blocking each other

December 27, 2017, 4:39 pm
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I have two standalone fpga board.
I want force one board to send specific signal and hold about 10 sec and another board sample the incoming signal .
I have writen two jam files and work correctly at each board.
But when I open two cmd consoles and run two quartus_jli at each console.
The quartus_jli at second console is always blocked till the quartus_jli at first console finished it's job.
Are there any paramerters to make quartus_jli not block each other?
Or is the only way can work that to make a jtag daisy chain of two devices?
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Error on non-volatile encription for Arria10

December 27, 2017, 9:14 pm
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Dear experts,
Now I am facing with a hardware issue on writing encription. When I wrote a non-volatile encription key with ekp-file to Arria10 device, it caused writing failure on Programmer. After that, I checked port status, and found TDO was always 1.8V, Vcc for JTAG.
Since TDO was always remained as 1.8V, I couldn't use JTAG port.
Once I used the target ekp-file for another device, and it worked correctly.
I revised file-name only for the ekp-file on this time.

Does anyone have any idea about such an issue?

Thanks,
Tetsuya
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VIP Video input V4L2 driver

December 28, 2017, 12:31 am
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Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
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Can I make my own software to use USB-Blaster II with Cypress SDK?

December 28, 2017, 12:46 am
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Hi,

I want to make my own software to transfer datas from PC to FPGA using USB-Blaster II.
Can I make software using CyUSB SDK? I already checked my blaster ii by making simple c# project.
But device (blaster ii) is not recognized. USB control center software in SDK also couldn't find blaster device.
Anybody try this?
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Estimation IIR filter resources

December 28, 2017, 2:18 am
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Hi,
In my application I will need implement high order (4), IIR, Butterworth, Low Pass filter, with cutoff frequency (-3dB) of ~1Hz and stop band of ~10Hz, with attenuation of -80dB. The input signal is sampled at rate of ~50ksps (32bits/sample).
The problem is that I need to select the right FPGA (Cyclone V) according to the filter resources. I haven't purchase yet the DSP builder (It takes time…) and the Simulink HDL coder but I can't delay the FPGA selection (will implemented on a costume board).
How can I estimate the resources to the IIR filter on those circumstances? I tried thought MATLAB filter editor and even managed to create some kind of VHDL code but I don’t have the relationship to ALTERA hardware (the "FPGA automation" tab is shut).
Thanks a lot,
Idan
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VIP Video input V4L2 driver

December 28, 2017, 4:33 am
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Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
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Mirel 9031 don`t startup

December 28, 2017, 11:05 am
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Dear Experts!
I'm developing a prototype device based on SoC Cyclone V, developed the circuit, layout the board, assembled the prototype, launched DDR3, SD. Prior to this, the FPGA project worked on debug board (DeoNano). Rested in Linux, or rather in the Ethernet part. Collected the kernel 3.11 ltsi, enabled CMA, compiled. I corrected dtb, ubut, rolled on the card according to the standard method. The kernel is loaded and i see eth0 is active (9031 Micrel is installed on it), its all: ... no way - the Ethernet does not get up.) I'm sinning on my motherboard. Returning to DeoNano. I'm still doing the same thing on rgmii1, I'm quiet again.What to do with a linux core to raise mikrel? I hope for your help.
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Intel HLS (High Level Synthesis) compiler

December 26, 2017, 7:36 am
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Hello all,

Can anyone please tell me from where to find some of the sample examples/projects of Intel HLS compiler ?
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Buffer chain output from DLL in ALTDLL

December 26, 2017, 10:03 am
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Hi, I require clocks with different phase shifts. Theoretically, the outputs at each stage of the buffers in the buffer chain of DLL in ALTDLL megafunction should do it. However, ALTDLL outputs only dll_delayctrlout and the buffer clock outputs are not available. Is there any way to access them? Thanks.
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Run Functional Simulation Error

December 26, 2017, 10:58 am
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I've just installed the QUARTUS II, and i am trying to run a simulation because i'm receiving the message below, can i have help solving this please? thanks

Device family: MAX7000S
Running quartus eda_testbench
>> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test {--vector_source=C:/Users/tracy/Documents/test/Waveform.vwf} {--testbench_file=./simulation/qsim/test.vt}
PID = 8580
************************************************** *****************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Processing started: Tue Dec 26 18:51:19 2017
Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog test -c test --vector_source=C:/Users/tracy/Documents/test/Waveform.vwf --testbench_file=./simulation/qsim/test.vt
Generated Verilog Test Bench File ./simulation/qsim/test.vt for simulation
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Peak virtual memory: 375 megabytes
Processing ended: Tue Dec 26 18:51:21 2017
Elapsed time: 00:00:02
Total CPU time (on all processors): 00:00:02
Running quartus eda_func_netlist
>> quartus_eda --functional=on --simulation --tool=modelsim_oem --format=verilog test -c test
PID = 14608
************************************************** *****************
Running Quartus II 64-Bit EDA Netlist Writer
Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
Processing started: Tue Dec 26 18:51:22 2017
Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog test -c test
Generated file test.vo in folder "C:/Users/tracy/Documents/test/simulation/modelsim/" for EDA simulation tool
Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Peak virtual memory: 375 megabytes
Processing ended: Tue Dec 26 18:51:23 2017
Elapsed time: 00:00:01
Total CPU time (on all processors): 00:00:02
************************************************** *****************
Running quartus modelsim
>> vsim -c -do test.do
PID = 9300
Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# do test.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module test
#
# Top level modules:
# test
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module test_vlg_sample_tst
# -- Compiling module test_vlg_check_tst
# -- Compiling module test_vlg_vec_tst
#
# Top level modules:
# test_vlg_vec_tst
# vsim -L max7000s_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.test_vlg_vec_tst
# Loading work.test_vlg_vec_tst
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(71): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(84): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(97): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(123): Instantiation of 'max_mcell' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(148): Instantiation of 'max_mcell' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(160): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) test.vo(173): Instantiation of 'max_io' failed. The design unit was not found.
#
# Region: /test_vlg_vec_tst/i1
# Searched libraries:
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/altera_mf
# c:/altera/13.0sp1/modelsim_ase/altera/verilog/220model
# c:/altera/13.0sp1/modelsim_ase/altera/vhdl/sgate
# C:/Users/tracy/Documents/test/simulation/qsim/work
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test_vlg_sample_tst
# ** Error: (vsim-19) Failed to access library '/../altera/verilog/max' at "/../altera/verilog/max".
#
# No such file or directory. (errno = ENOENT)
# Loading work.test_vlg_check_tst
# Error loading design
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Problems to program Cyclone V GT FPGA

December 27, 2017, 1:36 am
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Im new using Altera boards I have two questions.
I check the Quartus_II_Introduction for verilog users. On the programming chapter it says that "DE0-CV, DE0-Nano and DE2-115 Boards" should have a RUN/PROG switch.

1.-Does the cyclone V GT FPGA board has such switch?
2.-Also where can I find the pin assignments for this board?

Thank you
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Linux sources for precompiled img

December 27, 2017, 2:28 am
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Hello,
I have downloaded precompiled SD image for DE0-nano-soc devkit from terasic site, linux kernel ver: 3.13.0-00298-g3c7cbb9-dirty

Now I am trying to compile my custom driver for this linux.



I have cloned altera sources:

Quote:
git clone https://github.com/altera-opensource/linux-socfpga.git
Do you know which kernel sources I need for this linux?

Quote:
linux-socfpga # git tag -l rel*
rel_12.12
rel_13.02_RC1
rel_13.02_RC10
rel_13.02_RC2
rel_13.02_RC3
rel_13.02_RC4
rel_13.02_RC5
rel_13.02_RC6
rel_13.02_RC7
rel_13.02_RC8
rel_13.02_RC9
rel_13.07_RC0
rel_13.07_RC1
rel_13.07_RC2
rel_13.07_RC3
rel_13.07_RC4
rel_13.07_RC5
rel_ghrd_RC1
rel_ghrd_RC10
rel_ghrd_RC2
rel_ghrd_RC3
rel_ghrd_RC4
rel_ghrd_RC5
rel_ghrd_RC6
rel_ghrd_RC7
rel_ghrd_RC8
rel_ghrd_RC9

rel_socfpga-3.10-ltsi_arria10_bringup_gsrd_ies
rel_socfpga-3.10-ltsi_arria10_bringup_ies
rel_socfpga-3.13-rel14.0_14.06.01
rel_socfpga-3.13-rel14.0_14.06.02
rel_socfpga-3.13-rel14.0_14.07.01
rel_socfpga-3.13_14.02.02
I have tried one of 3.13* but my driver's version is:
Quote:
vermagic: 3.13.0-00299
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Altera cyclone 5 is not booting from spi

December 27, 2017, 2:52 am
$
0
0
​I created one uart program in quatux 2,i added uart in qsys,on chip memor and serial flash loader .i compiled it in quarux 2 .it succesfully compiled.when i opening this project in nios and create new BSP than following error coming......
"entry section mapping not created because reset memory region not located at base address 0x1011040."
"the section mapping entry is missing. and required linker section mapping do not exists."

i selected reset vector field serial flash loader and for exception i selected on chip memory.

can anyone help me,how tio solve this problem.

thank you
↧
↧

External SPI master clock connect to CPLD global clock network ?

December 27, 2017, 4:56 am
$
0
0
When using SPI communication, where a CPLD is acting as the slave and a microcontroller is the master, would the SPI clock (SCK) be connected to a global clock network of the CPLD? I.e. one of the CLK ports (labelled with a falling edge in the Quartus pin planner) ?
↧

NIOS II Command Shell not working

December 27, 2017, 5:31 am
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Excuse me if I this is a dumb question I am brand new at trying to use the NIOS II SBT. I am running Quartus Prime 17 on Windows 10 and keep getting an error when trying to open the software build tools for NIOS II. I did not know if this was because it was on windows 10. https://www.altera.com/support/suppo...s-support.html
It was working the other day though, and I have tried multiple times to uninstall and re download Quartus. I found a workaround to open it by running the eclipse-nios2.exe file which then opens this (shown in the attached image) up.
I don't want to continue my work for no reason.
Thanks for any help
Attached Images
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Simulation problem with autogenerate verilog code

December 27, 2017, 6:57 am
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Hi,
I develope some CNN on openCL, compile with OpenCL FPGA compiler, and this CNN is work on the DevKit.
But I want to simulation autogenerated verilog code which get after compilation. Simulation with Questa Sim.

I added all files from project (which generated by OpenCL FPGA compiler), from BSP too.

But QuestaSim get this error
Module 'twentynm_fp_mac_encrypted' is not define.

I can't find this module. Not in proj, not in BSP,not in Quartus. Can you tell me how can I solve this probem ?
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