December 27, 2017, 4:39 pm
I have two standalone fpga board.
I want force one board to send specific signal and hold about 10 sec and another board sample the incoming signal .
I have writen two jam files and work correctly at each board.
But when I open two cmd consoles and run two quartus_jli at each console.
The quartus_jli at second console is always blocked till the quartus_jli at first console finished it's job.
Are there any paramerters to make quartus_jli not block each other?
Or is the only way can work that to make a jtag daisy chain of two devices?
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December 27, 2017, 9:14 pm
Dear experts,
Now I am facing with a hardware issue on writing encription. When I wrote a non-volatile encription key with ekp-file to Arria10 device, it caused writing failure on Programmer. After that, I checked port status, and found TDO was always 1.8V, Vcc for JTAG.
Since TDO was always remained as 1.8V, I couldn't use JTAG port.
Once I used the target ekp-file for another device, and it worked correctly.
I revised file-name only for the ekp-file on this time.
Does anyone have any idea about such an issue?
Thanks,
Tetsuya
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December 28, 2017, 12:31 am
Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
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December 28, 2017, 12:46 am
Hi,
I want to make my own software to transfer datas from PC to FPGA using USB-Blaster II.
Can I make software using CyUSB SDK? I already checked my blaster ii by making simple c# project.
But device (blaster ii) is not recognized. USB control center software in SDK also couldn't find blaster device.
Anybody try this?
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December 28, 2017, 2:18 am
Hi,
In my application I will need implement high order (4), IIR, Butterworth, Low Pass filter, with cutoff frequency (-3dB) of ~1Hz and stop band of ~10Hz, with attenuation of -80dB. The input signal is sampled at rate of ~50ksps (32bits/sample).
The problem is that I need to select the right FPGA (Cyclone V) according to the filter resources. I haven't purchase yet the DSP builder (It takes time
) and the Simulink HDL coder but I can't delay the FPGA selection (will implemented on a costume board).
How can I estimate the resources to the IIR filter on those circumstances? I tried thought MATLAB filter editor and even managed to create some kind of VHDL code but I dont have the relationship to ALTERA hardware (the "FPGA automation" tab is shut).
Thanks a lot,
Idan
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December 28, 2017, 4:33 am
Hi,
is there anywhere any driver for Frame Buffer II IP Core compatible with V4L2?
I managed to find frame-buffer driver for old IPCore altvipfb.c -- Altera Video and Image Processing(VIP) Frame Reader driver, but nothing for new ipcores and especially for "Writer-only" version of Framebuffer.
Any help would be appreciated!
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December 28, 2017, 7:23 am
I touch attribute "autorun" in HelloWorld project, write OpenCL program:
Code:
global int i;
global int j;
__attribute__((max_global_work_dim(0)))
__attribute__((autorun))
__kernel void hello_world()
{
i = 0;
j = 1;
while (1) ;
}
and fast see big ASSERT output in last Quartus version of aoc (16.1, 17.0):
Code:
Compiler Command: aoc -v device/hello_world.cl -o bin/hello_world.aocx
******* Error: Assert failure at d:/SJ/nightly/17.0/290/w64/p4/acl/llvm/lib/FPGAAnalysis/ACLMemoryDependenceAnalysis2.cpp(3543) *******
acl::ACLMemorySpaces::is_local_addrspace((cast<ACLMemInst>(I))->getPointerAddressSpace()) FAILED
Stack dump:
0. Program arguments: D:/intelFPGA_pro/17.0/hld/windows64/bin/aocl-opt --acle ljg7wk8o12ectgfpthjmnj8xmgf1qb17frkzwewi22etqs0o0cvorlvc
zrk7mipp8xd3egwiyx713svzw3kmlt8clxdbqoypaxbbyw0oygu1nsyzekh3nt0x0jpsmvypfxguwwdo880qqk8pachqllyc18a7q3wp12j7eqwipxw13swz1bp7tk71wyb3rb17frk
...
3ndpos3fcle0burjbtijz3gfuwwjz880qqkdoehdqlr8v0jpsmvpz3rj1wjdor2qmqw07akc -board c:/intelFPGA_pro/16.1/hld/board/alaric_hpc_16.1.2_b203_2ban
ks_256_stp/hardware/alaric_v3_prod_2banks_256/board_spec.xml -dbg-info-enabled --grif --soft-elementary-math=false --fas=false --wiicm-disa
ble=true hello_world.1.bc -o hello_world.kwgid.bc
1. Running pass 'Function Pass Manager' on module 'hello_world.1.bc'.
2. Running pass 'Pipeline Memory Dependence Analysis' on function '@hello_world'
0x000000013FEA8740 (0x00000000035F9870 0x0000000002BC9EE0 0x0000000002BDBF30 0x00000000035F9800)
0x0000000140364AB9 (0x0000000002BC9EE0 0x0000000002B6F750 0x0000000000000210 0x0000000000000000)
0x0000000140364C69 (0x0000000000000000 0x0000000000A6F901 0x0000000002B6F750 0x00000000034680C0)
0x0000000140364EDD (0x000000000000003A 0x0000000002F9E8E0 0x00000000000001D0 0x0000000000000000)
0x00000001403651E0 (0x000000000357F7F0 0x0000000000000998 0x0000000000000133 0x0000000000A6F940)
0x000000013F7FED58 (0x0000000000000001 0x0000001B3ED1F579 0x0000000000000001 0x0000000000000000)
0x00000001404EF0A6 (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000), ??4_Init_locks@std@@QEAAAEAV01@AEBV01@@Z(
) + 0x80A bytes(s)
0x00000000776959CD (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000), BaseThreadInitThunk() + 0xD bytes(s)
0x00000000778CA561 (0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000), RtlUserThreadStart() + 0x21 bytes(s)
If I declare and set to 0 only 1 of global variables "i" or "j", then .cl is compiled successfull, normal programmed to flash and runned on start of the my PC.
Where are problem ? In Altera recomendations aocl_programming_guide.pdf I can`t find a restrictions for amount of global variables and setting to its on fly.
In the standard opencl-1.0.pdf in section "6.5 Address Space Qualifiers" is quoted an example of using attribute "__global" for global variables:
These declaration in upper code is caused next compilation error:
Code:
... /device/hello_world.cl:21:15: error: global variables must have a constant or channel address space qualifier
__global int *p;
^
1 error generated.
Error: OpenCL parser FAILED.
Refer to hello_world/hello_world.log for details.
Altera (and Intel) isn`t love and not test global variables in its version of Khronos OpenCL ?
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December 28, 2017, 11:05 am
Dear Experts!
I'm developing a prototype device based on SoC Cyclone V, developed the circuit, layout the board, assembled the prototype, launched DDR3, SD. Prior to this, the FPGA project worked on debug board (DeoNano). Rested in Linux, or rather in the Ethernet part. Collected the kernel 3.11 ltsi, enabled CMA, compiled. I corrected dtb, ubut, rolled on the card according to the standard method. The kernel is loaded and i see eth0 is active (9031 Micrel is installed on it), its all: ... no way - the Ethernet does not get up.) I'm sinning on my motherboard. Returning to DeoNano. I'm still doing the same thing on rgmii1, I'm quiet again.What to do with a linux core to raise mikrel? I hope for your help.
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December 28, 2017, 11:11 pm
hi
i selected epcq controller ,nios 2 classic processor and onchip memory.
in quartux program compiled ,when i created BSP than reset vector address error coming .i attached all screenshots .
please provide me solution for this error.
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December 29, 2017, 1:14 am
Hi
I'm wondering if anyone know does Arria 10 GX suppot half-precision floating point (FP16) operation when programmed by OpenCL?
It's mentioned in the OpenCL programming guide, but nothing in the documentation of Arria 10 expect "Variable-precision digital signal processing (DSP) blocks integrated with hardened floating point".
A paper titled "An OpenCL Deep Learning Accelerator on Arria 10" mentioned that FP16 is not natively supported, but can be done by "shared exponent technique", which I have no idea how it's done in OpenCL.
Thanks:)
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December 29, 2017, 1:24 am
I am bit a bit confuse about this topic as in the "aocl_programming_guide.pdf" (2016.10.31), section "1.6.4.4 Restrictions in the Implementation of Intel FPGA SDK for OpenCL
Channels Extension", it says:
Quote:
Because you can only assign a single call site per channel ID, you cannot unroll loops containing channels. ...
However, in the "aocl-best-practices-guide.pdf", section "1.6.1.3 Simplifying Loop-Carried Dependency", the optimized example contains in line 18, an unroll pragma on a for-loop containing a channel call:
Code:
12 ...
13 for (unsigned i = 0; i < N; i++) {
14
15 // Ensure that we have enough space if we read from ALL channels
16 if (num_bytes <= (8-NUM_CH)) {
17 #pragma unroll
18 for (unsigned j = 0; j < NUM_CH; j++) {
19 bool valid = false;
20 uchar data_in = read_channel_nb_altera(CH_DATA_IN[j], &valid);
21 if (valid) {
22 storage <<= 8;
23 storage |= data_in;
24 num_bytes++;
25 }
26 }
27 }
28 ...
Which according to the correspoding report is successfully fully unrolled:
Code:
==================================================================================
Kernel: optimized
==================================================================================
The kernel is compiled for single work-item execution.
Loop Report:
+ Loop "Block1" (file optimized3.cl line 13)
| Pipelined well. Successive iterations are launched every cycle.
|
|
|-+ Fully unrolled loop (file optimized3.cl line 18)
Loop was fully unrolled due to "#pragma unroll" annotation.
Perhaps loops containing NON-blocking channel calls are not a problem for loop-unrolling?
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December 29, 2017, 7:37 am
Hello,
While searching for OpenCL SDK, the only link I found is "bundle" version 17.1 (combined with Quartus Prime) ... about 20Gb
Does exist "alone" version of the OpenCL SDK, that matches Quartus Prime 15.1.
Thanks in advance.
Pavel.
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December 29, 2017, 10:32 am
Hi everyone,
I was trying to examinate the example "Vector_add" available on "https://www.altera.com/support/support-resources/design-examples/design-software/opencl/vector-addition.html and I would like to say what "USE_SVM_API" stands for. Thanks for your help.
Best regards
Marco Montini
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December 30, 2017, 8:25 am
I am using the Deo Nano SoC and I want to initialize some register values at startup without hitting a reset button. If there is a way to do this, please show me. I need this for run time and not simulation.
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December 30, 2017, 9:37 am
Hi,
I have try this code in my NIOS code :
printf("NIOS %d is waiting for control signal\n",ALT_CPU_CPU_ID_VALUE);
I have implement 3 nios processor in my project. Why this ALT_CPU_CPU_ID_VALUE function always return 0 value? Each core always returned 0 values instead 1,2,3 ?
it should be show this message :
NIOS 0 is waiting for control signal
NIOS 1 is waiting for control signal
NIOS 2 is waiting for control signal
However the fact , the message look like this :
NIOS 0 is waiting for control signal
NIOS 0 is waiting for control signal
NIOS 0 is waiting for control signal
Need for advice.. Thank you
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December 30, 2017, 10:32 am
Hi,
i got other problem with my mutex. This is my code for two slaves processor (assume the OnChip address is fine ):
Code:
#include "sys/alt_stdio.h"
#include "system.h"
#include "stdio.h"
#include "alt_types.h"
#include "io.h"
#include "altera_avalon_mutex.h"
#define OnChip 0x00007000
int main()
{
alt_mutex_dev *s1;
#ifdef MUTEX_BASE
s1 = altera_avalon_mutex_open("/dev/mutex");
#endif
printf("NIOS %d is waiting for control signal\n",ALT_CPU_CPU_ID_VALUE);
// waiting for control signal
while(!IORD(OnChip,0x00));
while(altera_avalon_mutex_trylock(s1,ALT_CPU_CPU_ID_VALUE));
// printing data
printf("NIOS %d captured Mutex \n",ALT_CPU_CPU_ID_VALUE);
altera_avalon_mutex_unlock(s1);
return 0;
and this is my code for my top processor
Code:
#include "sys/alt_stdio.h"
#include "system.h"
#include "stdio.h"
#include "alt_types.h"
#include "io.h"
#include "altera_avalon_mutex.h"
#define OnChip 0x00007000
int main()
{
printf("NIOS top gives control signal\n");
IOWR(OnChip,0x00,1);
while(1);
return 0;
}
My expectation should be :
NIOS 1 captured mutex
NIOS 2 captured mutex
however the result is out of my expectation, the result shown in attachment.
here the text version of my result :
NNIIOOSS 22 ccaappptuuurreedd muutttexx
Need for advice. Thanks
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December 30, 2017, 12:15 pm
I bought a "Terasic Cyclone V GX Starter Kit" and I have to process a analog signal. I bought a "Terasic Highspeed AD/DA Card" and connected it via HSMC. Unfortunatly I realized that the inputs are transformer coupled but I need the absolute voltage (DC coupling). For my application I need a ADC with >40 MSPS and >=10 Bit resolution. Are there any advises which board to buy? Or is there a way to make my AD/DA card DC coupled? BTW: My input signal is 0-2 V and I'm not sure if a 2 Vpp input (specification of the AD/DA card) is suitable.
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December 30, 2017, 11:55 pm
Hi,I compiled project PipeCNN on the github with Intel OpenCL SDK for FPGA 17.1 and get the following error
In file included from /home/wangjf/PipeCNN/project/__all_sources.cl:2:
PipeCNN/project/device/conv_pipe.cl:75:24: error: Channel support is not enabled
channel channel_vec data_ch attribute((depth(0)));
Anyone got an idea? Thanks in advance!!:-P
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December 31, 2017, 4:58 am
Hi all,
I'm currently using the Quartus 2 V15 and created a schematic file which compiles ok. when attempting to simulate I have the following error:
**** Running the ModelSim simulation ****
c:/altera/15.0/modelsim_ae/win32aloem//vsim -c -do multiplier.do
Unable to checkout a license. Vsim is closing.
** Fatal: Invalid license environment. Application closing.
Unable to checkout a license. Make sure your license file environment variables are set correctly and then run 'lmutil lmdiag' to diagnose the problem.
Modelsim-Altera uses the following environment variables to check the licenses (listed in the order of preference)
1. MGLS_LICENSE_FILE
2. LM_LICENSE_FILE.
Error.
I have looked on the Altera website which indicates I do not need a license. does anyone have any recommendations?
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December 31, 2017, 6:56 am
I'm very new to the dev board, however i'm looking for the above.
I wish to add logic, use the DDR memory and create custom language code.
Is there an example to work from. Simplest appreciated as i'm a single developer.
Hopefully thanks.
Paul.
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