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How to verify Avalon-MM slave?

December 31, 2017, 9:16 am
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I have written my first Avalon-MM slave component. It shall interface with a Nios II as the master device.

I am a bit lost on how to verify it to make sure that the Nios II shall correctly communicate with it.

I have come across something called BFM, it seems to be a new discipline to use them. I am VHDL-person.

What steps should I take to learn and prepare a testbench to verify this Avalon-MM slave component.
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SD 3.0 host controller implementation using simplified spec (UHS-ii mode)

December 31, 2017, 1:17 pm
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Hello,I wish to develop a SD 3.0 host controller core in UHS-ii mode using just the simplified spec delivered by SD Association (I don't know whether there is another better free resource), and:1-till now, I still can't confirm if just that simplified spec is enough to get this core up, i hope not to go through a dead end road..2- the reason beside attempting to develop this core from the bottom point is the high license cost of SD controller, thus will i need to cover those huge fees even if i take this approach (develop my own core using simplified spec for just research purpose). But if i do need to, there is some practical way to get ride of it? (i will appreciate if you can also share with me the references if possible).3- Knowing that i'm not very familiarised with FPGA design, how much time it would take to complete this work?I will appreciate any help,thanks,Saad.
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Quartus II: Newbie help needed

January 1, 2018, 5:51 am
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Hi there


I'm a complete newbie; and don't really know what I doing yet :(

I downloaded Quartus II 13.0 (32 bit) awhile back and after experiencing problems with (Programmer) reading Jtag! I decided to try and workout where I was going wrong through watching related videos on Youtube.

After watching a few videos on the 'Wizard' topic? I noticed at the 'Family & Device' section? I was having a problem with the set-up wizard. I can only seem to select "Arria II GX" whereas the videos I watched had the more devices available.

I have board here fitted with an MAX7000. I was hoping to tinker with it; and possible learn the basics.

Is there a limitation on the free software I am using? As I've followed the YT video instructions.

Thanks

ps Quartus detects my USB Blaster/driver installed.
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Simple NIOS Max 10 ethernet

January 1, 2018, 8:00 am
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I'd like to implement a very simple ethernet interface for low-speed data transfer to replace RS232 communication. I have used Lantronix before, but that is still more complicated than what I need. I don't need to host a web page, but that might be nice in the future.

Here are some loose requirements:

- No operating system is desired.
- TCP/IP stack handled in C code for minimum development time
- Cheap PHY chip (or even better, no phy chip). Suggestions here?
- No DDR off-board memory
- 10/100 required. Gbit ethernet okay, but I don't want to lock myself into an expensive phy chip or a device that has transceivers
- Able to be used by a higher-end (bigger) Max 10 chip, perhaps the 10M40
- No licenses or OSes to purchase. BTW, is the triple speed ethernet IP provided by Intel free?

I saw the simple socket reference design. This is close to what I need, but I don't want DDR memory. I could change the Qsys project to use on-board memory instead, but I'm not sure how much it really needs. The Max 10 runs out of memory pretty quickly.

I would really appreciate any help. Thanks!
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Verilog coding help

January 1, 2018, 8:13 am
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Hi

I have a ep4ce6 fpga board and I am trying to make a counter that counts up to 2_999_999_999.I don't know why it's not working. Here is the code: (I am trying to make a 1 sec timer) What am I doing wrong. I am selecting a verilog file in
the Quartus Application. The code compiles but led does not light up every second.

module mycounter
(
input clk, //50MHz onboard clock PIN 23
input reset,

output led
);

reg [25:0] counter; //26 bit - count up to 50_000_000 to generate 1 sec
reg tmp;

//COUNT
always @(posedge clk)
if(~reset)
counter <=0;
else
counter <= counter + 1;

//COUNT Comparator
always @(*) tmp = (counter == 26'd49_999_999);//

assign led = tmp;//I want the led to light up every second - IT DOESN'T ???


endmodule

Thanks

Saleem
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a10gx board installation failed

January 1, 2018, 5:29 pm
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I follow to install,although at "Installing kernel driver module... " and "Installing board drivers..." gives "install: completed successfully" however there are some errors during install,so I am not really sure install truly successful.Here is install log: --------------------------------------------------------------- C:\Users\source>aocl installDo you want to install C:\intelFPGA_pro\17.1\hld\board\a10_ref? [y/n] y aocl install: Running install from c:/intelFPGA_pro/17.1/hld/board/a10_ref/windows64/libexec +------------------------------------------------------++ Performing initial checks... ++------------------------------------------------------++------------------------------------------------------++ Installing kernel driver module... ++------------------------------------------------------+WDREG utility v10.21. Build Aug 31 2010 14:21:54Processing HWID *WINDRVR6Installing a signed driver package for *WINDRVR6CM_Get_DevNode_Status ret value 0, status 1802401, problem 1cLOG ok: 1, ENTER: DriverPackageInstallALOG ok: 1, ENTER: DriverPackageInstallWLOG ok: 1, Looking for Model Section [DeviceList.NTamd64]...LOG ok: 1, RETURN: DriverPackageInstallW (0xE000024B)LOG ok: 1, RETURN: DriverPackageInstallA (0xE000024B) difx_install_preinstall_inf: err e000024b, last event 0, last error 0. UNKNOWNinstall: completed successfully+------------------------------------------------------++ Installing board drivers... ++------------------------------------------------------+WDREG utility v10.21. Build Aug 31 2010 14:21:54Processing HWID PCI\VEN_1172&DEV_2494&SUBSYS_A1511172&REV_01Instal ling a non-signed driver package for PCI\VEN_1172&DEV_2494&SUBSYS_A1511172&REV_01Device node (hwid:PCI\VEN_1172&DEV_2494&SUBSYS_A1511172&REV_01 ): does not exist and is not configured. Pre-installing.LOG ok: 1, ENTER: DriverPackagePreinstallALOG ok: 1, ENTER: DriverPackagePreinstallWLOG ok: 1, RETURN: DriverPackagePreinstallW (0xE000022F)LOG ok: 1, RETURN: DriverPackagePreinstallA (0xE000022F) difx_install_preinstall_inf: err e000022f, last event 0, last error 0. UNKNOWNinstall: completed successfully+------------------------------------------------------++ ****** SUCCESS! Please reboot your system +-------------------------------------------------------------------------------After install, I try to use aocl diagnose, and get diagnose.exe system error: can't find altera_a10_ref_mmd.dll---------------------Warning:No devices attached for package:C:\intelFPGA_pro\17.1\hld\board\a10_ref---------------------Even I reinstall 2 times and get same message.When I use clinfo in command, get-------------------Platform Name: Intel(R) FPGA SDK for OpenCL(TM)ERROR: clGetDeviceIDs(-1)-------------------
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[ModelSim] Where to see a log of the commands

January 2, 2018, 2:41 am
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Hi All,

Where can I see a log of all the commands, which ran in ModelSim ever by manual entering/typing in the Transcript window or by using ModelSim buttons?

Thank you!
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can anyone help me about altmemphy ddr2 problem? about how to contrl initialization?

January 2, 2018, 3:19 am
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hi,thx first.
i have download many pdf files,and modlesim can get waves,simulation OK,can clearly know how initialization works.but i have no idea about how to use the alememphy files to design a ddr2 chip.
such as use what order to initialization the ddr2,or read,or write?how to control signals such as local_address,local_write_req,local_read_req etc?which file is the top level entry?ddr2.v or ddr2_example_top.v?
■NOP (for 200 µs, programmable)
■ PCH
■ ELMR, register 2
■ ELMR, register 3
■ ELMR, register 1
■ LMR
■ PCH
■ ARF
■ ARF
■ LMR
■ ELMR, register 1
■ ELMR, register 1
how to contrl phy work to finish these work?
thx a lot,need help
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Arria 10 Transceiver Native PHY for simply connection.. problems!

January 2, 2018, 4:04 am
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Good 2018 to everyone!

I'm attempting to simulate (Quartus Prime 17.0.2+Altera Modelsim) a simply Transceiver application: TX/RX single lane at 5,250 Gbps link between arria10 boards

I'm started from A10_SIBoard_SuperliteII_Video_1_Lane_10Gbps demo example project , changing some parameters to adapt application to my rate

I use Basic (enhanced PCS) mode, 64/66 (2 controls bit) , data rate 5250 Mhz. Internal Scrambler could be set or not.. my change is resumed here:


Parameter SuperliteII_Video_1Lane_10Gbps My project
XTAL * 148.5 Mhz 125 Mhz -> ½ divider
ATX PLL in 148.5 Mhz 62.5 Mhz
ATX PLL out -> tx_serial_clk0 5197.5 Mhz 2625 Mhz
Serial line rate 10.395 Gbps 5.25 Gbps
Tx parallel words rate 157.5 Mhz 65.625 Mhz
Rx parallel words rate 157.5 Mhz 65.625 Mhz
Cdr_ref_clock (Clock & data recovery transceiver) 148.5 Mhz 62.5 Mhz
RX CDR reference clock frequency 148.5 Mhz 62.5 Mhz
RX PMA & RX PMA dividers 33 40


Then, I Try to simulate a simply loop (internal loop Serialpbken)

I have a bad behaviour:

1) the native IP resets seems too short: I program 70000 ns but IP resets give me very short times
2) the phy runs, it create the rx clocks well.. but the received words (simply 64 bit counter sequence for test) lost one word every 10 / 20... !!! I tried with and without scrambler, I fix control bits to 01 but
the phy works bad..... Have you similar experiences with this object???

Thank you to everyone for any suggestion

Phil
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NIOS2 flash programmer - cannot program flash device

January 2, 2018, 4:26 am
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I am trying to program a new flash device and it will not work. The flash device part is SST39VF3201C-70-4I-B3KE, I am trying this part as our current device is now obsolete and it's one of the only compatible alternatives. I am familiar with CFI query tables on flash devices and am aware that some devices need to use a CFI override file to correct any contents. However I am not sure if that will help me as the CFI table read from the device matches the contents displayed in the datasheet. I have tried it using the override file, however it seems pointless as it's the same information. Has anyone has a similar issue or can offer any solutions to program this device?

The debug information I get from the NIOS2 flash programmer is shown below:

Reading override file "nios2-flash-override-ST-new.txt"
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00000C58: verified
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: BF 00 5F 23 01 00 FF FF 01 00 02 00 FF FF FE 00 .._#............
10: FD 00 FF FF 70 00 FF FF FF FF FF FF 1A 00 01 00 ....p...........
20: 51 00 52 00 59 00 02 00 00 00 00 00 00 00 00 00 Q.R.Y...........
30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 03 00 ......'.6.......
40: 00 00 04 00 05 00 01 00 00 00 01 00 01 00 16 00 ................
CFI query table read from device:
10: 51 52 59 02 00 00 00 00 00 00 00 27 36 00 00 03 QRY........'6...
20: 00 04 05 01 00 01 01 16 01 00 00 00 03 07 00 20 ...............
30: 00 3E 00 00 01 00 00 00 00 00 00 00 00 FF FF FF .>..............
40: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
50: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
60: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
70: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
CFI extended table not present in device
Read autoselect code 00BF-235F (in 16 bit mode)
No CFI override data for [FLASH-00BF-235F]
Extended query table missing or too small
Leaving target processor paused

The override file listed in the debug information is empty at the time of programming so just ignore it.

As you can see the programmer just stops after recognising there is no extended query table but I don't know if that's the issue - any suggestions are greatly appreciated, thank you.
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Motor on DEO Board

January 2, 2018, 8:35 am
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Can I use dc motor on DEO Board on the GPIO pins?
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Stratix5 - VCCCORE to GND resistance is almost 0 ohm

January 2, 2018, 7:30 pm
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Hi,

We have designed a PCB for the Stratix V device.
We found the resistance between VCCCORE and GND is almost 0 ohm, thus we never powered it up.


To clarify the problem, FPGA was disassembled the from the PCB. We found that the resistance between VCCCORE and GND is 0.02ohm on the FPGA itself.


Is is normal? Can we continue to power up the PCB?


Thanks in advance.
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The result is right in emulator mode, but is wrong in FPGA

January 2, 2018, 10:17 pm
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My code result is right in emulator mode, but when I compiled it and run in FPGA, the result is wrong.

What reasons will cause the problem? And how to debug code in the situation? The code need 13 hours to compile.

Thank you very much!
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source ./init_opencl.sh takes a long time?

January 2, 2018, 11:22 pm
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Hi,I plan to execute opencl demo on de10-standard,the Linux can boot normaly，but when I use command "source ./init_opencl.sh" to load opencl linux kernel driver and setup env variable,the terminal don‘t have any response for a long time.
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SDI II receiver implementation problem

January 3, 2018, 12:42 am
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Hello and good year,

I would like to implement a SDI II (v14.0) receiver on my cyclone V (5CSXFC5C6U23I7), but when i compile I got this error :

Error: The pin driving the input 'DATAIN' of node 'SDI2_receiver:SDI_receiv_inst|SDI2_receiver_0002: sdi2_receiver_inst|altera_xcvr_native_av:u_phy|av_ xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pm a:inst_av_pma|av_rx_pma:av_rx_pma|rx_pmas[0].rx_pma.rx_pma_buf' must have a fanout of 1.
Info: No legal values found

I suspect a bad pin assignment for the SDI Rx input but I don't know why. I implement a SDI Transmitter the same way but it work well.
Do you have any ideas to solve my problem ?

Thanks a lot !
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LM_LICENSE_FILE and MGLS_LICENSE_FILE

January 3, 2018, 1:27 am
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Hi,

we are at kratos are working with Aviram Evron the Altera FAE engineer in Israel.
I am using Quartus version 15.1
I installed Modelsim version 17.1 ae edition.
I placed the license file and set the parameters LM_LICENSE_FILE and MGLS_LICENSE_FILE correctly (see attached picture).
when I launch the modelsim I get fatal error "unable to checkout license.." ( see picture as well)
I launched command 'lmutil lmdiag' and gives the same path as in the environment variables windows(see attached picture)
As you can see I have in the system variables LM_LICENSE_FILE in addition to the user variable LM_LICENSE_FILE I created - is that a problem?
Any idea why the software cannot ID the licence? (attached is also the license file)

please help,

Noam Fishman
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Gpio pins

January 3, 2018, 7:01 am
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I need a sample code to use GPIO pins to control stepper motor?
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NCO Simulation help

January 3, 2018, 9:11 am
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Hello,

I am new to FPGA/VHDL and I am trying to generate a sine wave using the Altera NCO IP Core. I have instantiated the IP component and I am using the test bench generated. When I try and simulate the design using modelsim I get numerous errors similar to the one below:

Error(suppressible): (Vsim-10000) nofile(39): unresolved defparam reference to 'acc' in acc.lpm direction.
Time : 0 ps iteration: 0 instance: /sine_ip_core/uo/nco_ii_0/ux000 File: nofile.


Does anyone have any suggestions to solving this issue?

Any help would be appreciated.

Kind regards
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HDMI IP core timing problems

January 3, 2018, 12:56 pm
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Hello,

I am trying to incorporate the HDMI 2.0 core onto an Arria 10 device (Quartus 17.0) and am having trouble with what I believe to be timing problems. The core worked great for TX, and was a little picky with RX on my original build. After incorporating the rest of the project which includes 8x GEN3 PCIe and a 10Gbps SFP+ transceiver, I am getting erratic behavior between builds. Sometimes no HDMI output, sometimes lower resolutions like 1080p will work but not 4k@30 and sometimes visa versa. When I say no output, I mean the monitor cannot detect a signal, I do see data going by with the scope. HDMI RX is also not working right, in that the core will not show vid locked. The only constraints I have in place for the HDMI portion are the ones automatically generated and the input clock of course. In addition to erratic behavior on the HDMI output, I also have trouble with my pixel clock randomly between builds. Pixel clock is generated from IO PLL and it sometimes outputs the wrong frequency (divide by 4 instead of 2 for example), and it will not recover between power cycles or recal. I am also experiencing long compile times ~50min not sure if that is normal or not for a project this size, or if that is evident of constraint problems?

Any advice as to where I should be looking for problems?

Thanks
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PHYs for HDMI RX, DisplayPort TX

January 3, 2018, 4:13 pm
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Using an Arria 10 SoC for HDMI inputs and DisplayPort outputs. We are planning to use Altera's IP cores.

Is it possible to use only 4 PHY channels, with the HDMI connected to the RX pins, and DisplayPort connected to TX pins? Or do the two protocols need to have their own separate PHY channels?

Regards,
Jason
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