Hi all ,What is the difference between quartus ii software and quartus prime software.
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Tools
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Software
Hello everyone ,I am new to the Altera FPGA family and I want work in DECA board .So please tell me which software I used either quartus prime or quartus ii.
Thanks in advance.
Thanks in advance.
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How to use nios ii c code to make LCD panel on DE2-115 show special characters?
Hello everyone,
I'm working on a project from terasic demo named DE2_115_SD_Card_Audio_Player.
It uses c code to control LCD display as below.
static FILE *fp=0;
bool LCD_TextOut(char *pText){
if (!fp)
return FALSE;
fwrite(pText, strlen(pText), 1, fp);
return TRUE;
}
If you type
I'm working on a project from terasic demo named DE2_115_SD_Card_Audio_Player.
It uses c code to control LCD display as below.
static FILE *fp=0;
bool LCD_TextOut(char *pText){
if (!fp)
return FALSE;
fwrite(pText, strlen(pText), 1, fp);
return TRUE;
}
If you type
LCD_TextOut("Hello World\n\n"),
then the LCD will show "Hello World" on the first line.
Now I have a problem that I want to make the LCD show special characters
such as Japnese characters which can't be typed in c code but are supported by LCD(HD44780).
then the LCD will show "Hello World" on the first line.
Now I have a problem that I want to make the LCD show special characters
such as Japnese characters which can't be typed in c code but are supported by LCD(HD44780).
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Object Detection Implementation CNN
Hi, everyone.
Currently, I am doing research on CNN object detection implementation using opencl and fpga.
But, i wonder is it any example code/library provided by Intel Altera?
Thank you
Currently, I am doing research on CNN object detection implementation using opencl and fpga.
But, i wonder is it any example code/library provided by Intel Altera?
Thank you
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Using Differential Inputs to Evaluate an Incremental Encoder
Hi,
I would like to read in and evaluate the signal of the incremental encoder from a motor.
I have the Deca Max 10 board; the signal input has a maximum of 2MHz.(Depending on engine speed)
When the engine is running slowly, everything works fine. But if the engine is moving faster, i start miscounting the signal. I suspect it's because the signal gets worse with increasing speed.
Currently I use simple IOs for the incremental encoder signals (A, A ', B, B'). I hope to get the problem under control by using genuine differential IOs of the FPGA. Do you think this premise is right?
Currently I fail in this task.
There are a few documents that deal with this topic but these confuse me more than they help
The documents are probably aimed more at people who are already very familiar with the technology
https://www.altera.com/en_US/pdfs/li...g_m10_gpio.pdf
https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_lvds.pdf
Are there perhaps documents that explain the different IO-standarts(for beginners) or even better a tutorial that explains how to implement / instantiate a "real" differential input?
Is LVDS the right IO standard for my purpose? And how can this be created in the Pin Planner. If I set a pin as LVDS, the pin-planner automatically creates the second input. E.g. a -> a(n).
But I can not use a(n) in the code.
Is it sufficient to specify the IOs as LVDS, or do I also need to instantiation an IP core from Altera GPIO Lite?
Currently, i implement the diffenrential function with simple code like this: a_diff <= a_p and (not a_n);
I'm stuck right now. What do I have to do? Where can I read what to do.
I hope someone can help me or provide a new approach.
I would like to read in and evaluate the signal of the incremental encoder from a motor.
I have the Deca Max 10 board; the signal input has a maximum of 2MHz.(Depending on engine speed)
When the engine is running slowly, everything works fine. But if the engine is moving faster, i start miscounting the signal. I suspect it's because the signal gets worse with increasing speed.
Currently I use simple IOs for the incremental encoder signals (A, A ', B, B'). I hope to get the problem under control by using genuine differential IOs of the FPGA. Do you think this premise is right?
Currently I fail in this task.
There are a few documents that deal with this topic but these confuse me more than they help
The documents are probably aimed more at people who are already very familiar with the technology
https://www.altera.com/en_US/pdfs/li...g_m10_gpio.pdf
https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_lvds.pdf
Are there perhaps documents that explain the different IO-standarts(for beginners) or even better a tutorial that explains how to implement / instantiate a "real" differential input?
Is LVDS the right IO standard for my purpose? And how can this be created in the Pin Planner. If I set a pin as LVDS, the pin-planner automatically creates the second input. E.g. a -> a(n).
But I can not use a(n) in the code.
Is it sufficient to specify the IOs as LVDS, or do I also need to instantiation an IP core from Altera GPIO Lite?
Currently, i implement the diffenrential function with simple code like this: a_diff <= a_p and (not a_n);
I'm stuck right now. What do I have to do? Where can I read what to do.
I hope someone can help me or provide a new approach.
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Kernel Report Occupancy
Hi mates!
Im struggling to understand what the occupancy means.. for my understanding its the amount of time spent by the kernel doing a memory access. Is it right?
So if my occupancy its 100% it says that im doing to much accesses?
Cumps
Im struggling to understand what the occupancy means.. for my understanding its the amount of time spent by the kernel doing a memory access. Is it right?
So if my occupancy its 100% it says that im doing to much accesses?
Cumps
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Using relative include path with NativeLink?
Hello all!
I've setup a Quartus Project (using Modelsim-AE) and moved all include files to a subfolder "./inc".
I also added a relative include path using this command:
set_global_assignment -name SEARCH_PATH ./inc
This works fine but my problem is: When starting a RTL simulation(via NativeLink)
Modelsim doesn't find the include files.
Is there any option in QuartusII to setup NativeLink such that ModelSim finds the inc files
at their new location?
I've setup a Quartus Project (using Modelsim-AE) and moved all include files to a subfolder "./inc".
I also added a relative include path using this command:
set_global_assignment -name SEARCH_PATH ./inc
This works fine but my problem is: When starting a RTL simulation(via NativeLink)
Modelsim doesn't find the include files.
Is there any option in QuartusII to setup NativeLink such that ModelSim finds the inc files
at their new location?
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Intel HLS (High Level Synthesis) compiler
Hello all,
I am using Intel HLS compiler Quartus Prime Lite edition and going through solved examples to learn more about the tool.
Has anyone implemented a particular example in Intel HLS which has C++ templates in the code ? To be more precise, I am looking for an example which fits generic programming coding style (in terms of data types)....
I will be grateful if anyone has tested one such algorithmmmm
I am using Intel HLS compiler Quartus Prime Lite edition and going through solved examples to learn more about the tool.
Has anyone implemented a particular example in Intel HLS which has C++ templates in the code ? To be more precise, I am looking for an example which fits generic programming coding style (in terms of data types)....
I will be grateful if anyone has tested one such algorithmmmm
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Error: Can't assign node "" to any location (ID: 176359)
Has anybody came across this error? After hours of searching, I can't find anything on this.
I only get this error when I try to drive 8 or more register from one of the ALTPLL output.
Error: Can't assign node "name_altpll:auto_generated|wire_pll1_clk[0]" to any location (ID: 176359)
I only get this error when I try to drive 8 or more register from one of the ALTPLL output.
Error: Can't assign node "name_altpll:auto_generated|wire_pll1_clk[0]" to any location (ID: 176359)
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Help with signed output from ROM
I am new to VHDL and FPGA and have been been trying to generate a sine wave by outputting the data from ROM. The ROM is single port and was generated using IP. The sine wave values were stored in a .Mif as signed decimals. When i read the ROM values it outputs my signed values as unsigned. I have tried converting the output from the ROM to signed but that didn't seem to work. Does anyone have any idea how to rectify this? At the moment i just have positive cycles of the sine wave showing in modelsim.
Any help would be appreciated
Kind regards,
Any help would be appreciated
Kind regards,
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Invalid memory implementation
Please I need a help in following two questions:
First : I need to read from memory one element at a time, however, memory locations is not sequential so I need two variables as indicators.
The problem is, when I use one indicator, the memory is implemented correctly, but when I add the other one ( k in example below ) the memory tend to be logic.
IF rising_edge(clock) and show='1' THEN
outvalues<=Memory1(i+k)-outvalues; -- +k here is the issue.
k:=k+1;
if k=3 then
i:=i+8;
end if;
end if;
So, what is the solution for such case? how I guide the synthesizer to implement it as a memory?
Second question is: is it possible to initialize 2D array as an image ? , As I know MIF files are one dimension only.
Thank you.
First : I need to read from memory one element at a time, however, memory locations is not sequential so I need two variables as indicators.
The problem is, when I use one indicator, the memory is implemented correctly, but when I add the other one ( k in example below ) the memory tend to be logic.
IF rising_edge(clock) and show='1' THEN
outvalues<=Memory1(i+k)-outvalues; -- +k here is the issue.
k:=k+1;
if k=3 then
i:=i+8;
end if;
end if;
So, what is the solution for such case? how I guide the synthesizer to implement it as a memory?
Second question is: is it possible to initialize 2D array as an image ? , As I know MIF files are one dimension only.
Thank you.
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C++ template in memory-mapped master
Hello all,
I have a code from the Intel HLS examples. There is a C++ file for the master test bench operators. That tutorial demonstrate use of the getInterfaceAtIndex(int) operator on a memory-mapped master. Howver, in that code there is C++ template usage with a function. I am trying to understand the purpose of template usage. I will be grateful if any one can tell about it... Below is the whole code
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include "HLS/hls.h"
using namespace std;
using namespace ihc;
typedef mm_master<unsigned int, dwidth<32>, awidth<64>, aspace<1>, latency<0>, maxburst<1> > mm_src_t;
typedef mm_master<unsigned int, dwidth<32>, awidth<64>, aspace<3>, latency<0>, maxburst<1> > mm_dst_t;
#define SEED 3
#define NUM_SAMPLES 8
//#define DUMP_BUFFERS
int verify_data(int *src, int *dst, int count, unsigned int x=0) {
int errors = 0;
for(int i = 0; i < count; i++) {
if(dst[i] != (src[i] + x)) {
errors++;
printf("mismatch at index %d: 0x%llx != 0x%llx\n", i, (unsigned long long)dst[i], (unsigned long long)src[i] + x);
}
}
return errors;
}
template<typename T> void dump_buffers(const char* title, T *ref, T *dst, unsigned size) {
#ifdef DUMP_BUFFERS
// Title
printf("%s:\n", title);
if(size == 0) return;
// Reference
printf(" REF:");
for(unsigned i=0; i<size-1; ++i) {
printf(" 0x%04x,", ref[i]);
if(i % 8 == 7) printf("\n ");
}
printf(" 0x%04x\n", ref[size-1]);
// Destination
printf(" DST:");
for(unsigned i=0; i<size-1; ++i) {
printf(" 0x%04x,", dst[i]);
if(i % 8 == 7) printf("\n ");
}
printf(" 0x%04x\n", dst[size-1]);
#endif
}
component void add_x(mm_src_t &src, mm_dst_t &dst, unsigned int x) {
*dst = *src + x;
}
int main () {
int x = 0;
int errors = 0;
int src_mem[NUM_SAMPLES];
int dst_mem[NUM_SAMPLES];
// initialize data
srand(SEED);
for (int i=0; i<NUM_SAMPLES; ++i) {
src_mem[i] = rand() % 2048;
dst_mem[i] = -1;
}
dump_buffers("Initial", src_mem, dst_mem, NUM_SAMPLES);
/*
1)
This code creates a new mm_master interface for each iteration of the loop.
*/
x = 0x10;
for (int i=0; i<NUM_SAMPLES; ++i) {
mm_src_t src_mm_i(&src_mem[i], 1*sizeof(int));
mm_dst_t dst_mm_i(&dst_mem[i], 1*sizeof(int));
ihc_hls_enqueue_noret(&add_x, src_mm_i, dst_mm_i, x);
}
ihc_hls_component_run_all(add_x);
dump_buffers("New mm_master for each index", src_mem, dst_mem, NUM_SAMPLES);
errors += verify_data(src_mem, dst_mem, NUM_SAMPLES, x);
/*
2)
This code demonstartes use of the getInterfaceAtIndex() function which can
be used to index into a mm_master object. This can be useful when iterating
over an array and invoking a component on different indices of the array.
*/
x = 0x20;
mm_src_t src_mm(src_mem, NUM_SAMPLES*sizeof(int));
mm_dst_t dst_mm(dst_mem, NUM_SAMPLES*sizeof(int));
for (int i=0; i<NUM_SAMPLES; ++i) {
ihc_hls_enqueue_noret(&add_x, src_mm.getInterfaceAtIndex(i), dst_mm.getInterfaceAtIndex(i), x);
}
ihc_hls_component_run_all(add_x);
dump_buffers("Use getInterfaceAtIndex()", src_mem, dst_mem, NUM_SAMPLES);
errors += verify_data(src_mem, dst_mem, NUM_SAMPLES, x);
if (errors) {
printf("FAILED with %d errors\n", errors);
} else {
printf("PASSED\n");
}
}
I have a code from the Intel HLS examples. There is a C++ file for the master test bench operators. That tutorial demonstrate use of the getInterfaceAtIndex(int) operator on a memory-mapped master. Howver, in that code there is C++ template usage with a function. I am trying to understand the purpose of template usage. I will be grateful if any one can tell about it... Below is the whole code
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include "HLS/hls.h"
using namespace std;
using namespace ihc;
typedef mm_master<unsigned int, dwidth<32>, awidth<64>, aspace<1>, latency<0>, maxburst<1> > mm_src_t;
typedef mm_master<unsigned int, dwidth<32>, awidth<64>, aspace<3>, latency<0>, maxburst<1> > mm_dst_t;
#define SEED 3
#define NUM_SAMPLES 8
//#define DUMP_BUFFERS
int verify_data(int *src, int *dst, int count, unsigned int x=0) {
int errors = 0;
for(int i = 0; i < count; i++) {
if(dst[i] != (src[i] + x)) {
errors++;
printf("mismatch at index %d: 0x%llx != 0x%llx\n", i, (unsigned long long)dst[i], (unsigned long long)src[i] + x);
}
}
return errors;
}
template<typename T> void dump_buffers(const char* title, T *ref, T *dst, unsigned size) {
#ifdef DUMP_BUFFERS
// Title
printf("%s:\n", title);
if(size == 0) return;
// Reference
printf(" REF:");
for(unsigned i=0; i<size-1; ++i) {
printf(" 0x%04x,", ref[i]);
if(i % 8 == 7) printf("\n ");
}
printf(" 0x%04x\n", ref[size-1]);
// Destination
printf(" DST:");
for(unsigned i=0; i<size-1; ++i) {
printf(" 0x%04x,", dst[i]);
if(i % 8 == 7) printf("\n ");
}
printf(" 0x%04x\n", dst[size-1]);
#endif
}
component void add_x(mm_src_t &src, mm_dst_t &dst, unsigned int x) {
*dst = *src + x;
}
int main () {
int x = 0;
int errors = 0;
int src_mem[NUM_SAMPLES];
int dst_mem[NUM_SAMPLES];
// initialize data
srand(SEED);
for (int i=0; i<NUM_SAMPLES; ++i) {
src_mem[i] = rand() % 2048;
dst_mem[i] = -1;
}
dump_buffers("Initial", src_mem, dst_mem, NUM_SAMPLES);
/*
1)
This code creates a new mm_master interface for each iteration of the loop.
*/
x = 0x10;
for (int i=0; i<NUM_SAMPLES; ++i) {
mm_src_t src_mm_i(&src_mem[i], 1*sizeof(int));
mm_dst_t dst_mm_i(&dst_mem[i], 1*sizeof(int));
ihc_hls_enqueue_noret(&add_x, src_mm_i, dst_mm_i, x);
}
ihc_hls_component_run_all(add_x);
dump_buffers("New mm_master for each index", src_mem, dst_mem, NUM_SAMPLES);
errors += verify_data(src_mem, dst_mem, NUM_SAMPLES, x);
/*
2)
This code demonstartes use of the getInterfaceAtIndex() function which can
be used to index into a mm_master object. This can be useful when iterating
over an array and invoking a component on different indices of the array.
*/
x = 0x20;
mm_src_t src_mm(src_mem, NUM_SAMPLES*sizeof(int));
mm_dst_t dst_mm(dst_mem, NUM_SAMPLES*sizeof(int));
for (int i=0; i<NUM_SAMPLES; ++i) {
ihc_hls_enqueue_noret(&add_x, src_mm.getInterfaceAtIndex(i), dst_mm.getInterfaceAtIndex(i), x);
}
ihc_hls_component_run_all(add_x);
dump_buffers("Use getInterfaceAtIndex()", src_mem, dst_mem, NUM_SAMPLES);
errors += verify_data(src_mem, dst_mem, NUM_SAMPLES, x);
if (errors) {
printf("FAILED with %d errors\n", errors);
} else {
printf("PASSED\n");
}
}
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Memory map error in software program
Hi,
I am using Arria 10 Soc.
My design has HPS & PIO's are connected thru Axi light weight bus to HPS.
I instantiated a simple dut @ top level & connected to PIO's and i wrote sample c program to verify the functionality and i am getting memory mapping error.
ALT_FPGA_BRIDGE_LWH2F_OFST=0xff200000
HW_REGS_SPAN 0x04000000
ERROR: mmap failed
Also followed the same steps mentioned@
https://www.altera.com/documentation...159073865.html
Can anyone help me to solve this error.
I am using Arria 10 Soc.
My design has HPS & PIO's are connected thru Axi light weight bus to HPS.
I instantiated a simple dut @ top level & connected to PIO's and i wrote sample c program to verify the functionality and i am getting memory mapping error.
ALT_FPGA_BRIDGE_LWH2F_OFST=0xff200000
HW_REGS_SPAN 0x04000000
ERROR: mmap failed
Also followed the same steps mentioned@
https://www.altera.com/documentation...159073865.html
Can anyone help me to solve this error.
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Not able to Read Program in Quartus-ii
Hi,
I am trying to read data from EPM712SQC100-7, using USB Blaster.
Quartus-II isable to detect Device when i press "AUTO DETECT". JTAG chain is OK and intact.
I am not able to read data as "EXAMINE" check box is disabled.
Only "Blank check" box is active.
Pls. help.
Thanks a Lot
Uday
I am trying to read data from EPM712SQC100-7, using USB Blaster.
Quartus-II isable to detect Device when i press "AUTO DETECT". JTAG chain is OK and intact.
I am not able to read data as "EXAMINE" check box is disabled.
Only "Blank check" box is active.
Pls. help.
Thanks a Lot
Uday
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Cyclone 5 fpga is not booting from spi flash
Hi all, I am trying to boot CYCLONE 5 (5CGTFD7D5F27I7N) FPGA from QSPI FLASH (EPCQ128SI16N) .I am doing following steps: 1. I compiled counter program for blinking LED in quartux2,assigned FPGA pins, generated.sof file, downloaded it in to FPGA its working. 2. I converted .sof file to .jic file for flash and loaded in to flash. I referred the document given below. https://www.altera.com/en_US/pdfs/li...e/an/an370.pdf. 3. In programming window, flash programmed successfully message appear. Info (209060): Started Programmer operation at Fri Jan 05 16:19:14 2018 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x02B030DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209018): Device 1 silicon ID is 0x18 Info (209044): Erasing ASP configuration device(s) Info (209023): Programming device(s) Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Fri Jan 05 16:20:40 2018 4. After that power off the board and again power on than FPGA not booting from flash. 5. Than first we checked power sequencing of power supplies and it found ok .Tramp is 20 millisecond as we observed on oscilloscope . 6. After power on we monitor nconfigpin, status, config done pin before FPGA programming. FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=LOW FPGA_nstatus = toggling FPGA_nCSO = HIGH 7. After FPGA configuration with.sof file FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=HIGH FPGA_nstatus = HIGH FPGA_nCSO = HIGH 8. After programing flash FPGA_nCONFIG = HIGH FPGA_CONFIG_DONE=HIGH FPGA_nstatus = HIGH FPGA_nCSO = toggling FPGA_DATA PIN = HIGH During flash programming: DCLK toggling (10 MHz observed in oscilloscope). BUT still FPGA not booting from SPI FLASH. Anybody has any idea if Cyclone V FPGA booting from the QSPI or not ? If booting from QSPI than wt is mistake in my above process? Any other thought or suggestions that can help understand the problem will be highly appreciated. Thanks & Regards DEEPAK KUMAR
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ALTPLL simulation model bug
Hello there,
I haven't double checked if this exists in this forum, but this confused me a week!
And I found it is a bug, so I should notice Altera to fix it in the future.
Please check the verilog simulation model for altpll module (it should be in altera_mf.v file, the laptop is not on my hand right now, so please search it, if it is not there)
When I use the "Cyclone 10 LP" device and generate ALTPLL IP in quartus 17.1.
The software will generate a pll top level for me, and the intend_family is defined as "Cyclone 10 LP".
In the verilog simulation model, this IP actually is instantiated from a general PLL module, and the instance name is pll2.
Please check the generate condition section before the instance pll2.
There is no condition matched for "Cyclone 10 LP", so no pll core is instantiated for device "Cyclone 10 LP".
And I got unconnection on my pll top level.
If you check the condition list, the family names are not in a good manner.
I think you should review the family name list and double check if missing anything or making any redundency.
I searched this issue for many days, but no helpfull feedback.
I dont know how others fix this, or if anyone found this before.
Thanks.
/Patrick
I haven't double checked if this exists in this forum, but this confused me a week!
And I found it is a bug, so I should notice Altera to fix it in the future.
Please check the verilog simulation model for altpll module (it should be in altera_mf.v file, the laptop is not on my hand right now, so please search it, if it is not there)
When I use the "Cyclone 10 LP" device and generate ALTPLL IP in quartus 17.1.
The software will generate a pll top level for me, and the intend_family is defined as "Cyclone 10 LP".
In the verilog simulation model, this IP actually is instantiated from a general PLL module, and the instance name is pll2.
Please check the generate condition section before the instance pll2.
There is no condition matched for "Cyclone 10 LP", so no pll core is instantiated for device "Cyclone 10 LP".
And I got unconnection on my pll top level.
If you check the condition list, the family names are not in a good manner.
I think you should review the family name list and double check if missing anything or making any redundency.
I searched this issue for many days, but no helpfull feedback.
I dont know how others fix this, or if anyone found this before.
Thanks.
/Patrick
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[QSYS] Wrong Avalon memory address generation?
Hi folks,
New year, new opportunities, new problems :P
Tl;dr: It looks like Qsys generates address outside of the address space (instead of 0x20, it makes it 0x400000020). Does anybody knows why and/or how to fix this?
I came upon the following problem. I have a Qsys system for a CycloneV (see attached screen shot) with some custom made FIFOs (I make the FIFOs myself because the Altera FIFOs are too slow for the application). The basis of this Qsys system originates from this tutorial. The FIFOs are used to buffer the data coming from the FPGA with the HPS as destination. The Avalon memory mapped interfaces (two data-out interfaces and two Control-Status-Register interfaces) of those FIFOs are at 0x0, 0x20, 0x40, and 0x60. Qsys accepts this system and has no problems generating it without significant warnings.
However, when I want to try to compile this system in Quartus, it starts producing errors. It has to do with the interconnect and addresses of these FIFOs. Instead of mapping the FIFOs to 0x0, 0x20, 0x40, and 0x60, it maps these interfaces to 0x400000000, 0x400000020, 0x400000040, and 0x400000060. Those addresses are, of course, out of the 32 bit address space of the Avalon buss, which results in problems. I have no clue why this happens for my custom IPs, while all other (Altera) IPs at the same Avalon h2f_lw buss are mapped to the right memory address. A sniplet of the errorous code generated by Quartus is shown below (in my case it is the file soc_system_lw_mm_interconnect_3_router.sv).
The parameter RG will therefore become 34, which is out of the 32 bit address space (and out of the 0 to 33 bits bitvector bit address (actually I don't understand why this bitvector is 34 bits wide instead of 32 but yeah...probably some extra status bits added by the Avalon bus or so)). If I see the code-part with the if-statements. It looks like it maps the FIFOs not from i.e. 0x00 to 0x1f but from 0x00 to 0x400000000.
I also tried to use the f2h_axi buss instead of the f2h_lw_axi bus, but that does result in the same problems.
Do you know where this problem originates from and/or how to fix this issue?
Thanks a lot :)
P.s: I have tried to 0x4000000Y0 addresses to 0xY0 addresses by hand. The thing does compile than, but there still seems to be problems with accessing the memory addresses via the HPS/unix. I therefore think that this is not the solution.
New year, new opportunities, new problems :P
Tl;dr: It looks like Qsys generates address outside of the address space (instead of 0x20, it makes it 0x400000020). Does anybody knows why and/or how to fix this?
I came upon the following problem. I have a Qsys system for a CycloneV (see attached screen shot) with some custom made FIFOs (I make the FIFOs myself because the Altera FIFOs are too slow for the application). The basis of this Qsys system originates from this tutorial. The FIFOs are used to buffer the data coming from the FPGA with the HPS as destination. The Avalon memory mapped interfaces (two data-out interfaces and two Control-Status-Register interfaces) of those FIFOs are at 0x0, 0x20, 0x40, and 0x60. Qsys accepts this system and has no problems generating it without significant warnings.
However, when I want to try to compile this system in Quartus, it starts producing errors. It has to do with the interconnect and addresses of these FIFOs. Instead of mapping the FIFOs to 0x0, 0x20, 0x40, and 0x60, it maps these interfaces to 0x400000000, 0x400000020, 0x400000040, and 0x400000060. Those addresses are, of course, out of the 32 bit address space of the Avalon buss, which results in problems. I have no clue why this happens for my custom IPs, while all other (Altera) IPs at the same Avalon h2f_lw buss are mapped to the right memory address. A sniplet of the errorous code generated by Quartus is shown below (in my case it is the file soc_system_lw_mm_interconnect_3_router.sv).
Code:
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h400000000 - 64'h0);
localparam PAD1 = log2ceil(64'h400000020 - 64'h20);
localparam PAD2 = log2ceil(64'h400000040 - 64'h40);
localparam PAD3 = log2ceil(64'h400000060 - 64'h60);
localparam PAD4 = log2ceil(64'h4010 - 64'h4000);
localparam PAD5 = log2ceil(64'h5010 - 64'h5000);
localparam PAD6 = log2ceil(64'h10008 - 64'h10000);
localparam PAD7 = log2ceil(64'h20008 - 64'h20000);
localparam PAD8 = log2ceil(64'h30100 - 64'h30000);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h400000060;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
[....]
// ( 0x0 .. 0x400000000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 35'h0 && read_transaction ) begin
src_channel = 9'b000100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x20 .. 0x400000020 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h20) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h400000020) )
&& read_transaction ) begin
src_channel = 9'b000000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h20;
end
// ( 0x40 .. 0x400000040 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h40) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h400000040) )
&& read_transaction ) begin
src_channel = 9'b001000000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h40;
end
// ( 0x60 .. 0x400000060 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data[PKT_ADDR_H:PKT_ADDR_L] >= 'h60) && (sink_data[PKT_ADDR_H:PKT_ADDR_L] < 'h400000060) )
&& read_transaction ) begin
src_channel = 9'b000001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
src_data[PKT_ADDR_H:PKT_ADDR_L] = sink_data[PKT_ADDR_H:PKT_ADDR_L] - 'h60;
endI also tried to use the f2h_axi buss instead of the f2h_lw_axi bus, but that does result in the same problems.
Do you know where this problem originates from and/or how to fix this issue?
Thanks a lot :)
P.s: I have tried to 0x4000000Y0 addresses to 0xY0 addresses by hand. The thing does compile than, but there still seems to be problems with accessing the memory addresses via the HPS/unix. I therefore think that this is not the solution.
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