Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Rtos + vic

January 9, 2018, 4:41 am
$
0
0
Does anybody know, will any of existing RTOS's work with VIC ?
May be someone knows official information of Altera engineers about this question?
↧
Search

Device change in * .pof file

January 9, 2018, 6:21 am
$
0
0
Hello,

Using Quartus and Atera USB programmer we have to load component PM7128AETI100 on pc with Win7 64 bit.
We have to load *.pof file created for device EPM7128AT100. EPM7128AT100 is not supported in Quartus. Can we change *.pof file device to device PM7128AET100 supported in Quartus?


Thanks,
↧
↧

How OpenCL handles multiple accelerators on FPGA

January 9, 2018, 8:37 am
$
0
0
Hi everyone,
I would have two questions about how OpenCL manages multiple accelerators into FPGA:
1) Can I access to two or more accelerators at the same time if I have only one PCIe bus?
2) OpenCL is able to do partial reconfiguration into the FPGA when I have more than one accelerator?
Thanks for your help

Marco Montini
↧

How OpenCL synthesizes hardware on FPGA

January 9, 2018, 9:00 am
$
0
0
Hi,
I have some doubts concerning how OpenCL synthesizes hardware into FPGA. Both in single work-item and NDRange kernels, in the "vector_add" example (available on https://www.altera.com/support/suppo...-addition.html) how is the hardware realized into FPGA? In the above example, the kernel (NDRange mode) executes one milion of sums and I would like to say how the hardware is realized into the FPGA (if I use the single-work item kernel instead of NDRange kernel how does the hardware change respect to NDRange case?). Thanks for your help

Marco Montini
↧

SPI Driver Master in Qsys

January 9, 2018, 9:14 am
$
0
0
Hi All.


I am using a SPI Master component in Qsys. The driver makes use of the alt_avalon_spi_command().
No problem about this.


The only problem i have is related to the read operation. Infact the slave would like to see have the MOSI signal at the moment of the read set to H.


Unfortunatly this is not what the driver does. Is possible in some way to modify the driver in order to get the signal in this High during read instead of Low?


Thank you.
Paolo.
↧
↧

SignalTap - II question

January 9, 2018, 10:42 am
$
0
0
Problem: Unable to view certain internal registers in SignalTap II


I've tried this (added this to my verilog file). I still don't see any of these registers/wire in SignalTap.

//one attribute
////////////////////////////////////////////////////////////////
(* keep *) reg [2:0] keep_reg_apple;
(* preserve *) reg [2:0] preserve_reg_apple;
(* noprune *) reg [2:0] noprune_reg_apple;


(* keep *) wire [2:0] keep_wire_apple;
(* preserve *) wire [2:0] preserve_wire_apple;
(* noprune *) wire [2:0] noprune_wire_apple;


reg [2:0] reg_apple_keep /* synthesis keep */;
reg [2:0] reg_apple_preserve /* synthesis preserve */;
reg [2:0] reg_apple_noprune /* synthesis noprune */;


wire [2:0] wire_apple_keep /* synthesis keep */;
wire [2:0] wire_apple_preserve /* synthesis preserve */;
wire [2:0] wire_apple_noprune /* synthesis noprune */;


//two attribute
////////////////////////////////////////////////////////////////
(* keep *)(* preserve *) reg [2:0] keep_preserve_reg_apple;
(* preserve *)(* noprune *) reg [2:0] preserve_noprune_reg_apple;
(* noprune *)(* keep *) reg [2:0] noprune_keep_reg_apple;


(* keep *)(* preserve *) wire [2:0] keep_preserve_wire_apple;
(* preserve *)(* noprune *) wire [2:0] preserve_noprune_wire_apple;
(* noprune *)(* keep *) wire [2:0] noprune_keep_wire_apple;


reg [2:0] reg_apple_keep_preserve /* synthesis keep */ /* synthesis preserve */;
reg [2:0] reg_apple_preserve_noprune /* synthesis preserve */ /* synthesis noprune */;
reg [2:0] reg_apple_noprune_keep /* synthesis noprune */ /* synthesis keep */;


wire [2:0] wire_apple_keep_preserve /* synthesis keep */ /* synthesis preserve */;
wire [2:0] wire_apple_preserve_noprune /* synthesis preserve */ /* synthesis noprune */;
wire [2:0] wire_apple_noprune_keep /* synthesis noprune */ /* synthesis keep */;


//all three
////////////////////////////////////////////////////////////////
(* keep *)(* preserve *)(* noprune *) reg [2:0] keep_preserve_noprune_reg_apple;
(* keep *)(* preserve *)(* noprune *) wire [2:0] keep_preserve_noprune_wire_apple;
reg [2:0] reg_apple_keep_preserve_noprune /* synthesis keep */ /* synthesis preserve */ /* synthesis noprune */;
wire [2:0] wire_apple_keep_preserve_noprune /* synthesis keep */ /* synthesis preserve */ /* synthesis noprune */;


What is going on? How do I fix this?
↧

Intel Triple-Speed Ethernet Link detect LED lines malfunctioning?

January 9, 2018, 10:48 am
$
0
0
Hello,

I've instantiated the Intel TSE IP Core in my design, testing on the Intel Arria 10 GX Development Kit board. From what I can tell it appears to be functioning: data can be sent and received, and the partner on the other side of the link shows auto-negotiation success and link up.

However, I'm getting weird behavior from the IP core's LEDs. After an Ethernet cable is unplugged the led_an (auto-negotiation success) and led_link/led_panel_link (link up) remain illuminated. led_crs (activity detect) works as you'd expect. Neither of the error LEDs are illuminated and I see no other hint of a problem.

If I unplug the cable, led_an and led_panel_link briefly turn off, but almost immediately re-illuminate even if the cable remains unplugged. led_link stays on no matter what.

Any clues as to what might be happening here? What information can I provide to help? Attached is an image of the cable unplug event. I'm stumped.

I'm setting the following registers, in this order, and confirmed they were set by reading them back.

Address <- Value
0x03 <- 0x04030201 // Mac upper
0x04 <- 0x00000605 // MAC lower
0x92 <- 0x00000D40 // Link timer lower
0x93 <- 0x00000003 // Link timer upper
0x80 <- 0x00009141 // PCS reset
0x02 <- 0x0000023B // TSE Control (TX_ENA, RX_ENA, ETH_SPEED, PROMIS_ENA, PAD_ENA, TX_ADDR_INS)
Attached Images
↧

Constraining timing on configurable PLL output for a range of frequencies

January 9, 2018, 10:50 am
$
0
0
Hi

I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly.

I am wondering about how to constrain the piece of design that runs on PLL output so that I have reliable operation within the max and min frequency range.

Previously I only constrained for the max case i.e. 300 MHz assuming that if this design is able to run at max then should be fine at min as well. However, I recently came across some
information indicating that my assumption might not be true and I may need to constrain for the lower limit as well. Now I don't fully understand how the lower limit of frequency will play
a role in possible malfunctioning of the design (it likely has to do with combinational delays) and don't know if the information I came across is true or applicable in my case or not.
This piece of logic running off from PLL output is standalone and doesn't have any dependence interfaces that might cause problems with it running slow or fast.

Google search isn't returning much, so just wondering if there's a way to constrain a design for max and min frequency output from PLL in sdc commands ?


Thanks
↧
Search

1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

January 9, 2018, 1:07 pm
$
0
0
I need to drive multiple 1.8V HSTL differential pairs from a Cyclone 10 LP FPGA. The output is DDR, source synchronous.

I am currently doing this with single-ended signals using the ALTDDIO_OUT megafunction. How do I best make each output pin differential instead of single-ended?

From the datasheet, I believe that only the CLKOUT pins support differential HSTL output. So, I must emulate it with two single-ended outputs with one inverted.

I don't seem to be able to tell the pin planner to make the pins a pair (like we do for LVDS).

Any guidance is much appreciated!
↧
↧

Running the program again

January 9, 2018, 1:56 pm
$
0
0
Is there any way that I can run the same program even after when I power off and power the board later by using SD Card on DE0 Board?
↧

DE10-Nano GHRD failure to generate

January 9, 2018, 2:00 pm
$
0
0
Hi All

I'm trying to recompile the standard GHRD for the Terasic De10-Nano Cyclone V SoC Board, and following the instructions (User Manual chapter 7) very carefully, it fails with a great number of errors (and four warnings), the first one a complaint about a missing file hps_AC_ROM.hex. This file does exist, in the soc_system/synthesis/submodules/ directory.

Has anyone met this? Or can give any useful pointer for what to try?

The source is from Terasic's DE10-Nano CD-ROM v 1.2.3 (but the versions of this CD do the same thing).

To repeat the error:

  1. Make a copy of the source:
    Code:
    cp -Rp cdrom/Demonstrations/SoC_FPGA/DE10_NANO_SoC_GHRD GHRDx
  2. Code:
    cd GHRDx
  3. Run quartus
  4. Open Project DE10_NANO_SoC_GHRD.qpf
  5. Tools > Qsys and open soc_system.qsys
  6. Generate > Generate HDL, (defaults for form: Verilog, no third-party, yes create block, sim model none, output dir ./soc_system)



The Generate HDL command fails with errors, the first of which is
Error: border: Error during execution of script generate_hps_sdram.tcl: seq: add_fileset_file: No such file /tmp/alt7540_4530398708016069914.dir/0003_seq_gen/hps_AC_ROM.hex

The compilation environment is a newly-configured Ubuntu 16.04 LTS server with
$ quartus_sh --version
Quartus Prime Shell
Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition

I tried it with 17.0 and got the same result: but 16.0 is what the manual says you need, and is what the source was made with.

I've managed to compile the simpler, non-Qsys examples and run them, but I've spent about five days getting nowhere with this.

Many thanks for any help and suggestions,
Jonathan.
↧

MAX10 Dual Purpose/JTAG issues

January 9, 2018, 2:46 pm
$
0
0
I am using an M08 device and trying to set up dual mode pins. I enabled JTAG pin sharing and disabled nCONFIG, nSTATUS...

I only needed two pins for my user mode (TCK and TMS), but I also added TDI and TDO to the port list and assigned them as std_logic (they are not connected to any signals in the code). This is because according to the config document, all JTAG pins must be assigned as single-ended IO.

On the board there are 10k pull-ups on TMS, JTAGEN, TDO, and TDI (and nSTATUS, CONFIG, and CONFIG_DONE), and 10k pull-down on TCK.

When I try to program the device with a .sof file, the programmer initially recognizes the part, but as soon as I click "Start" I get a "Failed" message and the tool no longer recognizes the device. When I cycle power (re-loading the old, non dual use code), the JTAG recognizes the device again.

What have I done wrong or missed? Is there a good way to prevent use of the JTAG pins in user mode when I want to re-program?


Thanks

Bret
↧

about xml file: soc_system_board_info.xml

January 9, 2018, 11:59 pm
$
0
0
Hi,

I have the DE1-SoC Board, Rev F.
I downloaded the HWrevF_SystemCD from terasic's website: www.terasic.com/downloads/cd-rom/de1-soc/DE1-SoC_v.5.1.1_HWrevF_SystemCD.zip
In the folder Demonstrations/SOC_FPGA/de1_soc_GHRD, I found the soc_system_board_info.xml file.
This file is used to generate the socfpga.dts file using sopc2dts tool.

But it contains the following lines:
Quote:
<I2CBus master="hps_0_i2c0">
<I2CChip addr="0x28" label="lcd" name="newhaven,nhd-0216k3z-nsw-bbw"></I2CChip>
Although, the DE1-SoC board does not contain any LCD display.

Is this xml file correct ?
↧
↧

BluePrint Platform Designer

January 10, 2018, 1:47 am
$
0
0
I heard about the Blueprint Designer tool from Quartus Prime features. I have installed Prime Lite Edition. Please tell me how can i download the Blue Print Platform Designer for pin planners?
↧

How to check whether a Cyclone IC is defect

January 10, 2018, 1:50 am
$
0
0
Dear Members!

I am working since 5 years with Cyclone II EP2C8 simple boards, I am developing some hobby projects at home.
Yesterday some strange thing happened to me, as I improved my VHDL code by using Quartus II, compiled and downloaded it into the fpga.
(more background: I added some new signals, thus the exploitage of the device was higher about from 42% to 43%)
After configuration, one of the multiple adding function (8 times 16bit) was not able to produce a value other then zero. There was no timing problem, because the result of the simultaneously working adder was taken after 100us. The inputs was stable and also appropriate latched.
This adder was worked before, and the changes what I made was not related this part. (I would like to point out, that during the using of the old code, I had some issues, that the result of the adder was sometimes 0 but only very rarely and only for a fraction of a second)

I thought first, that my code was wrong, but after 1 hour searching and trying, I did not get any result, the result was still zero.
Finally I changed the board, and I configured the other board, and that solved my problem, the adder worked. So I think inside the IC some gates was defect, and as I changed the code, this defect part of array was used.

Now the question: Anyone knows about a procedure, how to test a new shipped (or an old) Cyclone IC, whether every gate array inside the IC is completely working? I would imagine a checksum code, which goes all the gates thru, and if one of them not working, the result is other than expected.

Do Quartus II has a built in IC test feature?

Thank you for your answer in advance!
↧
Search

twentynm_fp_mac_encrypted simulation in questasim

January 10, 2018, 2:30 am
$
0
0
Hi,
I have some problem with simulaion fpga project with twentynm_fp_mac_encypted component.
How can I get HDL code for simulation of this component
or find full information about functions of this componet ?
Thank you
↧

Nstatus pin is toggling on power on

January 10, 2018, 3:26 am
$
0
0
HI,

I had designed one custom board with cyclone5 (5CGTFD7D5F27I7N) FPGA.
I am trying to boot FPGA from SPI flash.
FLASH programmed successfully by .jic file but at power on -off FPGA is not loading from SPI QUAD FLASH.
while observation we find that ,at power on nstatus pin is toggling.
But when we program fpga with .sof than nstatus going high.

so what is the reason for this and how to overcome it ??

tramp(between 1.1 and 3.3v)=22 millisecond in our board.
power sequencing is -> 1.1v -> 1.2v ->2.5v -> 3.3v.



Thanks & Regards
DEEPAK
↧
↧

Cyclone III FPGA Is not working above 400Mbps

January 10, 2018, 7:08 am
$
0
0
Hi All,

I am using Cyclone III: EP3C40F780C6N FPGA. We are using this for capturing the Image from the sensor.
As per the data sheet it should support up to 875 Mbps.
I am able to get the valid Image data up to 300 Mbps. After that my image data is getting skipped or not getting valid data from the FPGA even if the sensor is throwing valid data.
I have verified the eye opening in the FPGA receiver end and it is 110mV differential.

All the timing Constraints for the PLL & input clocks were added
Please help on this.

Thanks in Advance.
↧

May be BareMetal program as a host for OpenCL kernels ?

January 10, 2018, 7:27 am
$
0
0
For bare HPS may be fast compile and running OpenCL application ?
Windows, Linux have own interface libraries. Give Altera its for small programs ?
↧

Nallatech PCIe-385N documentation

January 10, 2018, 7:28 am
$
0
0
Hi,
Does anyone have any documentation or manuals on this card? Please hit me at 1736115 at gmail com if you do. I would really appreciate if you share with me anything you have.
I just got on a project where this card is used, and I'd like to sort things out, but there's absolutely no information about this device.
↧
Viewing all 19390 articles
Browse latest View live
Search