I found a new pipelined framework for high throughput design proposed in the document AN831 - Intel FPGA SDK for OpenCL Host PipelinedMultithread. I am using Arria 10 board and OpenCL SDK 16.1, does my platform support this new framework, especially for the host channel streaming feature?
In the document, he took Data Compression as an example, and mentioned read_channel_intel(host_to_dev) and write_channel_intel(dev_to_host,...), but how can I realize these channels? Where to find the related BSP and also, the related code?
Hellow every one i am new here i hope i can find someone to help me
So thank you in advance.
I am using Quartus prime for a project based on multipliers. I used LPM_mult from the IP catalog (with Qsys which replaced megawizard plugin..). The design is a simple structural architecture using LPMs as components. These LPMs folders are generated in the project directory containing vhdl files and packages. The design in quartus prime is synthetisable (no errors), but , once I move to modelsim to test and verify the design functionality I cant compile the associated vhdl LPMs files. In one hand, I received this kind of error messages library coef86_lpm_mult_170 is not found.
On the other hand, I tried to compile all the files in every folder generated by quartus. Simulation is set and I get this hierarchical (as attached) but when running the simulataion all signal assigned to LPM outputs are set in high impedence.
Please, can anyone help me? Is this due to the libraries miss? If so, how can I add them knowing that each LPM used has his own library name.
With the IntelFPGA SDK 17.0, the Dynamic Profiler for OpenCL GUI (report) is showing me only the kernel execution time but not the PCI transfers.
However, I remember seeing the PCI transfer with an older SDK version and another board,
Does somebody know how to show it, if it was removed or if it depends from board to board?
So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is responsible for managing the timing of reading and writing to the DMA buffers in the FX3. After reading data from the FX3, I need to wait until I receive a signal "mult_done", before I can write back to the FX3 as that signals the data is ready. However when the state machine reaches the point where it waits for mult_done to go high and continue to the write state, the problem occurs. The state machine seems to go to the write state (HPI_FPGA_write_to_usb), but then returns to the previous state (HPI_FPGA_wait_read_mult_done), then continues to alternate between these two states on each positive clock edge, (I've checked this using a scope and test pins).
The code for my state machine is more or less as follows, let me know if I can supply any further details as I'm still fairly new to quartus.
--HPI_FPGA mode state machine combo
HPI_FPGA_mode_fsm : process(clk_ddr, reset_n) begin
if(reset_n = '0')then
current_HPI_FPGA_state <= HPI_FPGA_idle;
elsif(clk_ddr'event and clk_ddr = '1')then
current_HPI_FPGA_state <= next_HPI_FPGA_state;
case current_HPI_FPGA_state is
.
.
.
.
when HPI_FPGA_wait_flagb => if(flagb_d = '1' and read_writeb_mode = '1')then
next_HPI_FPGA_state <= HPI_FPGA_wait_read_mult_done;
elsif(read_writeb_mode = '0' and flagb_d = '1') then
next_HPI_FPGA_state <= HPI_FPGA_write_to_usb;
else
next_HPI_FPGA_state <= HPI_FPGA_wait_flagb;
end if;
when HPI_FPGA_wait_read_mult_done =>
if(mult_done_sig = '1')then
next_HPI_FPGA_state <= HPI_FPGA_write_to_usb;
else
next_HPI_FPGA_state <= HPI_FPGA_wait_read_mult_done;
end if;
when HPI_FPGA_write_to_usb =>
if(flagb_d = '0' or pktend_sig = '0')then
next_HPI_FPGA_state <= HPI_FPGA_write_wr_delay;
else
next_HPI_FPGA_state <= HPI_FPGA_write_to_usb;
end if;
Has anyone tried generating a programming file (.jic) for the EPCQ128A flash memory for a Quartus project that was originally using the EPCS128 flash memory with Cyclone III FPGA? We are using Quartus 13 which doesn't have the EPCQ128A option so we generate the programming file for EPCQ128. However when using JTAG programmer there is an error "Can't recognize Silicon ID for Device 1". The .jic file generated for EPCQ128 however downloads to the EPCS128 flash without issues. We have eliminated the setup as the issue. As part of the troubleshooting, we also disabled the device ID check when generating the programming file. We repeated this exercise for the EPCS64 to EPCQ64A flash and there were no issues with generating the programming file for EPCQ64 and then downloading to the EPCQ64A flash.
Any thoughts on why the EPCQ128A is behaving differently?
I wrote a (relatively large) RTL module. It's optimized to calculate the square root for fixed point numbers in a very specific parameter range. I've implemented it without any internal state, only using combinatorics. What would be the right way to describe this in the RTL module description?
I would think I have to set IS_STALL_FREE and IS_FIXED_LATENCY to YES. But what about EXPECTED_LATENCY? Is it 0? Or 1?
I am using a dual-supply MAX10 with banks 1a, 1b and 2 powered from 2.5 V and all remaining banks, including bank 8, from 3.3 V. I cannot find anything in the documentation suggesting that this is wrong however running the IO assignment analysis process from within Quartus produces the following warning:
Warning (169202): Inconsistent VCCIO across multiple banks of configuration pins. The configuration pins are contained in 2 banks in 'Internal Configuration' configuration scheme and there are 2 different VCCIOs.
I assume it does not like the fact that my JTAG header (which is connected to IO bank 1b) is running at 2.5 V whilst the configuration control/status pins, eg, nCONFIG, nSTATUS, etc, (which are all in IO bank 8) are all running at 3.3 V. Can you confirm that this arrangement is completely acceptable? I realise it's a warning rather than an error but I don't really see why it is even a warning.
I'am an information technician and develope for (ASM,Pascal,C++,C#,php, nodejs) for 18 years now as a day job.
Back in 2001/2002 I developed an well desigend and fast Bitcoin miner for an XD2000i (Stratix III).
And now I got my hand on two Terasic TR5-F45M (5SGXEA7N2F45C2) or DE5Net and have a new project developing...
I develop on my old custom build PC
-CPU AMD FX 8350 (8-Core)
-RAM 16GB
-TR5-F45M (Stratix V)
-Windows 10 Pro 64
-Altera/Intel FPGA OpenCl SDK
-Visual Studio 2017
I have moved the whole "altera" folder and the project to an fast PCI-e SSD, and my compile times (first stage) dropped from 10 to 20 minutes to around 2 minutes.
The second stage now uses up to 100% of all 8 cores and aound 12 GB RAM, and that wasn't so before, I utilized around 12% to 25 % on average.
compiling still takes time, and I just sit here and wait.. but I wanted to tell you about this improvemnt.
Is there a way I can program a EPCQ4ASI8N to work with Cyclone I?
I have to keep some products which still use Cyclone I FPGA with EPCS4SI8N.
Due to EPCS4SI8N discontinuation, the EPCQ4ASI8N might be a possible alternative, as advised in PDN1708.
My problem is that the Cyclone 1 was supported until the Quartus 10.1 version, and the support for the EPCQ4ASI8N begins from Quartus 17.1.
I thought that the solution would be just to take de .pof file, generated by Quartus 10.1, and just program the new device EPCQ4ASI8N with the Quartus 17.1 programer, but I got the following message from Quartus 17.1 programer when I tried to change de device to EPCQ4A:
"Device EPCQ4A selected for replacement is incompatible with target device EPCS4 associated with programming file..."
So I don´t know how to generate the .pof in the old Quartus 10.1 since it does not support EPCQ4A yet.
Hi all,
I am going to design high speed application. Because my cyclone V development kit (DE10- Standard) have two output options is GPIO and HSMC. I would like to know what the different between them? Could I use GPIO pinout for high speed application? Is GPIO LVDS pinout?
and have a question about its HBM2 DRAM memory. When reading the overview of the device it looks as if the DRAM has been integrated into the FPGA. I looked at the Stratix 10MX product table and on the HBM2 high-bandwidth DRAM memory it has the units of GBytes and if you look to the right it has numbers such as 3.25, 8, 16. Now that's pretty impressive amount of memory and I question myself if I'm understanding things correctly. I must be missing something here!
Does the Stratix 10MX have GBytes on on-chip memory? If anyone has some information on "DRAM System-in-Package" and what it is let me know.
Hello,
I have Arria 10 SoC Development Kit (it contain 2GB DDR4 - 256Mb x 72 x single rank) and i want to configure NIOS system.
I saw some tutorials and finally made a system that contain NIOS-ii processor, On-Chip Mem, Timer, JTAG, system_id perp. My system will execute uC/OS Application.
However, On-Chip Memory is too small to run my application.
So, I want to change my On-Chip Memory component to External DRAM component but there are no document or tutorial to use it as NIOS processors memory. (or i can't find it)
I unpacked arria 10 document files that contain DDR4 example files. I executed it and it worked. but i can't make connection between these example and Nios processor.
Can anyone help me how can i configure External DRAM as Nios Processor memory?
Sorry for my english and explain skill. Thank you.
I'm trying to get a customised FFT1D example working. Basically it is the same as the example fft1d from the library, except I am adding in an RTL module which executes an XOR function. The idea is that fft1d runs normally, but also calls a function XOR which maps to the RTL module. This serves no real application - I'm doing this simply to learn the programming flow for combined OpenCL/RTL functionality.
I build the RTL library etc, and go to compile the highest level .cl file (fft1d.cl). Everything compiles fine, and it gets past the First Stage Compilation Successfully, but then fails with: 'Error: Compiler Error, unable to generate hardware.'.
I went digging through the log and eventually came upon 6 errors: Certain signals that are in my .xml file are missing from the synthesised fft1d.v file. (I didn't write the .v file, I assume the compilation process generates this from the .cl) In any case, the log has this:
Error (13305): Verilog HDL error at fft1d.v(8041): can't find port "clock" File: <my_file_path>
Error (13305): Verilog HDL error at fft1d.v(8042): can't find port "resetn" File: <my_file_path>
Error (13305): Verilog HDL error at fft1d.v(8043): can't find port "m_ready_in" File: <my_file_path>
Error (13305): Verilog HDL error at fft1d.v(8044): can't find port "m_valid_in" File: <my_file_path>
Error (13305): Verilog HDL error at fft1d.v(8045): can't find port "m_ready_out" File: <my_file_path>
Error (13305): Verilog HDL error at fft1d.v(8046): can't find port "m_valid_out" File: <my_file_path>
From the Programming Guide, section 12, these signals are all required for Avalon ST for RTL module to be included. I assumed that the compilation process took care of everything else, provided I had these in my .xml file. What have I missed?
is there any possibility to check by script if a .jic-file is encrypted or not?
Other FPGA-manufacturers has an code in the header but I can´t find any information about such code in ALTERA docs.
For some reason, the Altera's Triple Speed Ethernet (TSE) MAC strips off the VLAN tag word from incoming packet of 48 bytes. But it works with a longer packet of over 200 bytes. Did anyone see the same issue before?
I am using Arria V GX starter kit with Quartus Prime Standard edition software + Arria V GX Starter Kit tools.
I was trying to open Power monitor GUI coming with Arria V GX Starter Kit tools to measure the power ,
I got the following error image attached.Then after following the documentation i added the environmental variables and all...
Still am getting the same error.
Can anybody from Intel Altera can help me to figure this out.Its been 1 Week am facing this issue.
IN our board only one SPI FLASH (CONFIGURATION FLASH) is there which is connected to dedicated pins of FPGA,no CPLD ,no other flash is there.
1. I have created LED program in quartux2, generated .sof file, and programmed it in to FPGA its working the LEDs are blinking and CONFIG_DONE LED also glowing.
2. I converted .sof to .jic, and programmed to SPI flash, it IS successfully programmed .It means that program is successfully written on SPI FLASH.
3. While I press reset button(MAKING FPGA_NCONFIG LOW), than LED not blinking, CONFIG DONE LED also not glowing it means that FPGA is not able to fetch the program from SPI FLASH.
SAME PROCESS I TRIED IN TWO evaluation board as given below it is working -
I tried .JIC method on cyclone5 GT evaluation board and cyclone5 Gx .
In this board FPGA is booting from SPI flash after Power ON.
In both evaluation board CPLD is also in between FPGA and QSPI flash.
In our custum board CPLD is not used between FPGA and QSPI flash.
Is CPLD required for booting FPGA from flash or not ?
IN two board we have seen that .JIC is working ,in both board CPLD is there.
So my doubt is without CPLD it may be .jic process will not work , if some other process is there than you tell me that procedure through NIOS2 ,I will try that procedure in our board.
First of I'm very new to Altera so this is probably something very
simple but I just can't figure/google this one out.
I've set up a simple project that compiles fine, except I get this "No clocks defined in design" error
and thus cannot get the Fmax for my trial design.
Obviously somehow the compiler does not understand that there is a clock used in
my Verilog code or something, but I cannot figure out what to do.
I've copied those from the 'filtref' example from Quartus installation
and that project compiles fine and produces Fmax, but that project
has toplevel as schematic entry and I want/need Verilog/textfile only solution.
I've tried to find a complete example project that would be Verilog with
text only files but have not found one ... so a pointer would be highly
appreciated.
But the main question is how do I make Quartus recognize my clock?